1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 */
5
6 /*
7 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
8 * Based on code from spd_sdram.c
9 * Author: James Yang [at freescale.com]
10 */
11
12 #include <common.h>
13 #include <dm.h>
14 #include <i2c.h>
15 #include <fsl_ddr_sdram.h>
16 #include <fsl_ddr.h>
17
18 /*
19 * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
20 * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
21 * all Power SoCs. But it could be different for ARM SoCs. For example,
22 * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
23 * 0x00_8000_0000 ~ 0x00_ffff_ffff
24 * 0x80_8000_0000 ~ 0xff_ffff_ffff
25 */
26 #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
27 #ifdef CONFIG_MPC83xx
28 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
29 #else
30 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
31 #endif
32 #endif
33
34 #ifdef CONFIG_PPC
35 #include <asm/fsl_law.h>
36
37 void fsl_ddr_set_lawbar(
38 const common_timing_params_t *memctl_common_params,
39 unsigned int memctl_interleaved,
40 unsigned int ctrl_num);
41 #endif
42
43 void fsl_ddr_set_intl3r(const unsigned int granule_size);
44 #if defined(SPD_EEPROM_ADDRESS) || \
45 defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
46 defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
47 #if (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
48 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
49 [0][0] = SPD_EEPROM_ADDRESS,
50 };
51 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
52 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
53 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
54 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
55 };
56 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
57 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
58 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
59 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
60 };
61 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
62 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
63 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
64 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
65 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
66 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
67 };
68 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
69 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
70 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
71 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
72 [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */
73 };
74 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
75 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
76 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
77 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
78 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
79 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
80 [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */
81 [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */
82 };
83
84 #endif
85
86 #if defined(CONFIG_DM_I2C)
87 #define DEV_TYPE struct udevice
88 #else
89 /* Local udevice */
90 struct ludevice {
91 u8 chip;
92 };
93
94 #define DEV_TYPE struct ludevice
95
96 #endif
97
98 #define SPD_SPA0_ADDRESS 0x36
99 #define SPD_SPA1_ADDRESS 0x37
100
ddr_i2c_read(DEV_TYPE * dev,unsigned int addr,int alen,uint8_t * buf,int len)101 static int ddr_i2c_read(DEV_TYPE *dev, unsigned int addr,
102 int alen, uint8_t *buf, int len)
103 {
104 int ret;
105
106 #ifdef CONFIG_DM_I2C
107 ret = dm_i2c_read(dev, 0, buf, len);
108 #else
109 ret = i2c_read(dev->chip, addr, alen, buf, len);
110 #endif
111
112 return ret;
113 }
114
115 #ifdef CONFIG_SYS_FSL_DDR4
ddr_i2c_dummy_write(unsigned int chip_addr)116 static int ddr_i2c_dummy_write(unsigned int chip_addr)
117 {
118 uint8_t buf = 0;
119
120 #ifdef CONFIG_DM_I2C
121 struct udevice *dev;
122 int ret;
123
124 ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, chip_addr,
125 1, &dev);
126 if (ret) {
127 printf("%s: Cannot find udev for a bus %d\n", __func__,
128 CONFIG_SYS_SPD_BUS_NUM);
129 return ret;
130 }
131
132 return dm_i2c_write(dev, 0, &buf, 1);
133 #else
134 return i2c_write(chip_addr, 0, 1, &buf, 1);
135 #endif
136
137 return 0;
138 }
139 #endif
140
__get_spd(generic_spd_eeprom_t * spd,u8 i2c_address)141 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
142 {
143 int ret;
144 DEV_TYPE *dev;
145
146 #if defined(CONFIG_DM_I2C)
147 ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, i2c_address,
148 1, &dev);
149 if (ret) {
150 printf("%s: Cannot find udev for a bus %d\n", __func__,
151 CONFIG_SYS_SPD_BUS_NUM);
152 return;
153 }
154 #else /* Non DM I2C support - will be removed */
155 struct ludevice ldev = {
156 .chip = i2c_address,
157 };
158 dev = &ldev;
159
160 i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
161 #endif
162
163 #ifdef CONFIG_SYS_FSL_DDR4
164 /*
165 * DDR4 SPD has 384 to 512 bytes
166 * To access the lower 256 bytes, we need to set EE page address to 0
167 * To access the upper 256 bytes, we need to set EE page address to 1
168 * See Jedec standar No. 21-C for detail
169 */
170 ddr_i2c_dummy_write(SPD_SPA0_ADDRESS);
171 ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd, 256);
172 if (!ret) {
173 ddr_i2c_dummy_write(SPD_SPA1_ADDRESS);
174 ret = ddr_i2c_read(dev, 0, 1, (uchar *)((ulong)spd + 256),
175 min(256,
176 (int)sizeof(generic_spd_eeprom_t)
177 - 256));
178 }
179
180 #else
181 ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd,
182 sizeof(generic_spd_eeprom_t));
183 #endif
184
185 if (ret) {
186 if (i2c_address ==
187 #ifdef SPD_EEPROM_ADDRESS
188 SPD_EEPROM_ADDRESS
189 #elif defined(SPD_EEPROM_ADDRESS1)
190 SPD_EEPROM_ADDRESS1
191 #endif
192 ) {
193 printf("DDR: failed to read SPD from address %u\n",
194 i2c_address);
195 } else {
196 debug("DDR: failed to read SPD from address %u\n",
197 i2c_address);
198 }
199 memset(spd, 0, sizeof(generic_spd_eeprom_t));
200 }
201 }
202
203 __attribute__((weak, alias("__get_spd")))
204 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
205
206 /* This function allows boards to update SPD address */
update_spd_address(unsigned int ctrl_num,unsigned int slot,unsigned int * addr)207 __weak void update_spd_address(unsigned int ctrl_num,
208 unsigned int slot,
209 unsigned int *addr)
210 {
211 }
212
fsl_ddr_get_spd(generic_spd_eeprom_t * ctrl_dimms_spd,unsigned int ctrl_num,unsigned int dimm_slots_per_ctrl)213 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
214 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
215 {
216 unsigned int i;
217 unsigned int i2c_address = 0;
218
219 if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) {
220 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
221 return;
222 }
223
224 for (i = 0; i < dimm_slots_per_ctrl; i++) {
225 i2c_address = spd_i2c_addr[ctrl_num][i];
226 update_spd_address(ctrl_num, i, &i2c_address);
227 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
228 }
229 }
230 #else
fsl_ddr_get_spd(generic_spd_eeprom_t * ctrl_dimms_spd,unsigned int ctrl_num,unsigned int dimm_slots_per_ctrl)231 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
232 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
233 {
234 }
235 #endif /* SPD_EEPROM_ADDRESSx */
236
237 /*
238 * ASSUMPTIONS:
239 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
240 * - Same memory data bus width on all controllers
241 *
242 * NOTES:
243 *
244 * The memory controller and associated documentation use confusing
245 * terminology when referring to the orgranization of DRAM.
246 *
247 * Here is a terminology translation table:
248 *
249 * memory controller/documention |industry |this code |signals
250 * -------------------------------|-----------|-----------|-----------------
251 * physical bank/bank |rank |rank |chip select (CS)
252 * logical bank/sub-bank |bank |bank |bank address (BA)
253 * page/row |row |page |row address
254 * ??? |column |column |column address
255 *
256 * The naming confusion is further exacerbated by the descriptions of the
257 * memory controller interleaving feature, where accesses are interleaved
258 * _BETWEEN_ two seperate memory controllers. This is configured only in
259 * CS0_CONFIG[INTLV_CTL] of each memory controller.
260 *
261 * memory controller documentation | number of chip selects
262 * | per memory controller supported
263 * --------------------------------|-----------------------------------------
264 * cache line interleaving | 1 (CS0 only)
265 * page interleaving | 1 (CS0 only)
266 * bank interleaving | 1 (CS0 only)
267 * superbank interleraving | depends on bank (chip select)
268 * | interleraving [rank interleaving]
269 * | mode used on every memory controller
270 *
271 * Even further confusing is the existence of the interleaving feature
272 * _WITHIN_ each memory controller. The feature is referred to in
273 * documentation as chip select interleaving or bank interleaving,
274 * although it is configured in the DDR_SDRAM_CFG field.
275 *
276 * Name of field | documentation name | this code
277 * -----------------------------|-----------------------|------------------
278 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
279 * | interleaving
280 */
281
282 const char *step_string_tbl[] = {
283 "STEP_GET_SPD",
284 "STEP_COMPUTE_DIMM_PARMS",
285 "STEP_COMPUTE_COMMON_PARMS",
286 "STEP_GATHER_OPTS",
287 "STEP_ASSIGN_ADDRESSES",
288 "STEP_COMPUTE_REGS",
289 "STEP_PROGRAM_REGS",
290 "STEP_ALL"
291 };
292
step_to_string(unsigned int step)293 const char * step_to_string(unsigned int step) {
294
295 unsigned int s = __ilog2(step);
296
297 if ((1 << s) != step)
298 return step_string_tbl[7];
299
300 if (s >= ARRAY_SIZE(step_string_tbl)) {
301 printf("Error for the step in %s\n", __func__);
302 s = 0;
303 }
304
305 return step_string_tbl[s];
306 }
307
__step_assign_addresses(fsl_ddr_info_t * pinfo,unsigned int dbw_cap_adj[])308 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
309 unsigned int dbw_cap_adj[])
310 {
311 unsigned int i, j;
312 unsigned long long total_mem, current_mem_base, total_ctlr_mem;
313 unsigned long long rank_density, ctlr_density = 0;
314 unsigned int first_ctrl = pinfo->first_ctrl;
315 unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
316
317 /*
318 * If a reduced data width is requested, but the SPD
319 * specifies a physically wider device, adjust the
320 * computed dimm capacities accordingly before
321 * assigning addresses.
322 */
323 for (i = first_ctrl; i <= last_ctrl; i++) {
324 unsigned int found = 0;
325
326 switch (pinfo->memctl_opts[i].data_bus_width) {
327 case 2:
328 /* 16-bit */
329 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
330 unsigned int dw;
331 if (!pinfo->dimm_params[i][j].n_ranks)
332 continue;
333 dw = pinfo->dimm_params[i][j].primary_sdram_width;
334 if ((dw == 72 || dw == 64)) {
335 dbw_cap_adj[i] = 2;
336 break;
337 } else if ((dw == 40 || dw == 32)) {
338 dbw_cap_adj[i] = 1;
339 break;
340 }
341 }
342 break;
343
344 case 1:
345 /* 32-bit */
346 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
347 unsigned int dw;
348 dw = pinfo->dimm_params[i][j].data_width;
349 if (pinfo->dimm_params[i][j].n_ranks
350 && (dw == 72 || dw == 64)) {
351 /*
352 * FIXME: can't really do it
353 * like this because this just
354 * further reduces the memory
355 */
356 found = 1;
357 break;
358 }
359 }
360 if (found) {
361 dbw_cap_adj[i] = 1;
362 }
363 break;
364
365 case 0:
366 /* 64-bit */
367 break;
368
369 default:
370 printf("unexpected data bus width "
371 "specified controller %u\n", i);
372 return 1;
373 }
374 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
375 }
376
377 current_mem_base = pinfo->mem_base;
378 total_mem = 0;
379 if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) {
380 rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >>
381 dbw_cap_adj[first_ctrl];
382 switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl &
383 FSL_DDR_CS0_CS1_CS2_CS3) {
384 case FSL_DDR_CS0_CS1_CS2_CS3:
385 ctlr_density = 4 * rank_density;
386 break;
387 case FSL_DDR_CS0_CS1:
388 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
389 ctlr_density = 2 * rank_density;
390 break;
391 case FSL_DDR_CS2_CS3:
392 default:
393 ctlr_density = rank_density;
394 break;
395 }
396 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
397 rank_density, ctlr_density);
398 for (i = first_ctrl; i <= last_ctrl; i++) {
399 if (pinfo->memctl_opts[i].memctl_interleaving) {
400 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
401 case FSL_DDR_256B_INTERLEAVING:
402 case FSL_DDR_CACHE_LINE_INTERLEAVING:
403 case FSL_DDR_PAGE_INTERLEAVING:
404 case FSL_DDR_BANK_INTERLEAVING:
405 case FSL_DDR_SUPERBANK_INTERLEAVING:
406 total_ctlr_mem = 2 * ctlr_density;
407 break;
408 case FSL_DDR_3WAY_1KB_INTERLEAVING:
409 case FSL_DDR_3WAY_4KB_INTERLEAVING:
410 case FSL_DDR_3WAY_8KB_INTERLEAVING:
411 total_ctlr_mem = 3 * ctlr_density;
412 break;
413 case FSL_DDR_4WAY_1KB_INTERLEAVING:
414 case FSL_DDR_4WAY_4KB_INTERLEAVING:
415 case FSL_DDR_4WAY_8KB_INTERLEAVING:
416 total_ctlr_mem = 4 * ctlr_density;
417 break;
418 default:
419 panic("Unknown interleaving mode");
420 }
421 pinfo->common_timing_params[i].base_address =
422 current_mem_base;
423 pinfo->common_timing_params[i].total_mem =
424 total_ctlr_mem;
425 total_mem = current_mem_base + total_ctlr_mem;
426 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
427 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
428 } else {
429 /* when 3rd controller not interleaved */
430 current_mem_base = total_mem;
431 total_ctlr_mem = 0;
432 pinfo->common_timing_params[i].base_address =
433 current_mem_base;
434 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
435 unsigned long long cap =
436 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
437 pinfo->dimm_params[i][j].base_address =
438 current_mem_base;
439 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
440 current_mem_base += cap;
441 total_ctlr_mem += cap;
442 }
443 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
444 pinfo->common_timing_params[i].total_mem =
445 total_ctlr_mem;
446 total_mem += total_ctlr_mem;
447 }
448 }
449 } else {
450 /*
451 * Simple linear assignment if memory
452 * controllers are not interleaved.
453 */
454 for (i = first_ctrl; i <= last_ctrl; i++) {
455 total_ctlr_mem = 0;
456 pinfo->common_timing_params[i].base_address =
457 current_mem_base;
458 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
459 /* Compute DIMM base addresses. */
460 unsigned long long cap =
461 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
462 pinfo->dimm_params[i][j].base_address =
463 current_mem_base;
464 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
465 current_mem_base += cap;
466 total_ctlr_mem += cap;
467 }
468 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
469 pinfo->common_timing_params[i].total_mem =
470 total_ctlr_mem;
471 total_mem += total_ctlr_mem;
472 }
473 }
474 debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
475
476 return total_mem;
477 }
478
479 /* Use weak function to allow board file to override the address assignment */
480 __attribute__((weak, alias("__step_assign_addresses")))
481 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
482 unsigned int dbw_cap_adj[]);
483
484 unsigned long long
fsl_ddr_compute(fsl_ddr_info_t * pinfo,unsigned int start_step,unsigned int size_only)485 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
486 unsigned int size_only)
487 {
488 unsigned int i, j;
489 unsigned long long total_mem = 0;
490 int assert_reset = 0;
491 unsigned int first_ctrl = pinfo->first_ctrl;
492 unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
493 __maybe_unused int retval;
494 __maybe_unused bool goodspd = false;
495 __maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl;
496
497 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
498 common_timing_params_t *timing_params = pinfo->common_timing_params;
499 if (pinfo->board_need_mem_reset)
500 assert_reset = pinfo->board_need_mem_reset();
501
502 /* data bus width capacity adjust shift amount */
503 unsigned int dbw_capacity_adjust[CONFIG_SYS_NUM_DDR_CTLRS];
504
505 for (i = first_ctrl; i <= last_ctrl; i++)
506 dbw_capacity_adjust[i] = 0;
507
508 debug("starting at step %u (%s)\n",
509 start_step, step_to_string(start_step));
510
511 switch (start_step) {
512 case STEP_GET_SPD:
513 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
514 /* STEP 1: Gather all DIMM SPD data */
515 for (i = first_ctrl; i <= last_ctrl; i++) {
516 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i,
517 dimm_slots_per_ctrl);
518 }
519
520 case STEP_COMPUTE_DIMM_PARMS:
521 /* STEP 2: Compute DIMM parameters from SPD data */
522
523 for (i = first_ctrl; i <= last_ctrl; i++) {
524 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
525 generic_spd_eeprom_t *spd =
526 &(pinfo->spd_installed_dimms[i][j]);
527 dimm_params_t *pdimm =
528 &(pinfo->dimm_params[i][j]);
529 retval = compute_dimm_parameters(
530 i, spd, pdimm, j);
531 #ifdef CONFIG_SYS_DDR_RAW_TIMING
532 if (!j && retval) {
533 printf("SPD error on controller %d! "
534 "Trying fallback to raw timing "
535 "calculation\n", i);
536 retval = fsl_ddr_get_dimm_params(pdimm,
537 i, j);
538 }
539 #else
540 if (retval == 2) {
541 printf("Error: compute_dimm_parameters"
542 " non-zero returned FATAL value "
543 "for memctl=%u dimm=%u\n", i, j);
544 return 0;
545 }
546 #endif
547 if (retval) {
548 debug("Warning: compute_dimm_parameters"
549 " non-zero return value for memctl=%u "
550 "dimm=%u\n", i, j);
551 } else {
552 goodspd = true;
553 }
554 }
555 }
556 if (!goodspd) {
557 /*
558 * No valid SPD found
559 * Throw an error if this is for main memory, i.e.
560 * first_ctrl == 0. Otherwise, siliently return 0
561 * as the memory size.
562 */
563 if (first_ctrl == 0)
564 printf("Error: No valid SPD detected.\n");
565
566 return 0;
567 }
568 #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
569 case STEP_COMPUTE_DIMM_PARMS:
570 for (i = first_ctrl; i <= last_ctrl; i++) {
571 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
572 dimm_params_t *pdimm =
573 &(pinfo->dimm_params[i][j]);
574 fsl_ddr_get_dimm_params(pdimm, i, j);
575 }
576 }
577 debug("Filling dimm parameters from board specific file\n");
578 #endif
579 case STEP_COMPUTE_COMMON_PARMS:
580 /*
581 * STEP 3: Compute a common set of timing parameters
582 * suitable for all of the DIMMs on each memory controller
583 */
584 for (i = first_ctrl; i <= last_ctrl; i++) {
585 debug("Computing lowest common DIMM"
586 " parameters for memctl=%u\n", i);
587 compute_lowest_common_dimm_parameters
588 (i,
589 pinfo->dimm_params[i],
590 &timing_params[i],
591 CONFIG_DIMM_SLOTS_PER_CTLR);
592 }
593
594 case STEP_GATHER_OPTS:
595 /* STEP 4: Gather configuration requirements from user */
596 for (i = first_ctrl; i <= last_ctrl; i++) {
597 debug("Reloading memory controller "
598 "configuration options for memctl=%u\n", i);
599 /*
600 * This "reloads" the memory controller options
601 * to defaults. If the user "edits" an option,
602 * next_step points to the step after this,
603 * which is currently STEP_ASSIGN_ADDRESSES.
604 */
605 populate_memctl_options(
606 &timing_params[i],
607 &pinfo->memctl_opts[i],
608 pinfo->dimm_params[i], i);
609 /*
610 * For RDIMMs, JEDEC spec requires clocks to be stable
611 * before reset signal is deasserted. For the boards
612 * using fixed parameters, this function should be
613 * be called from board init file.
614 */
615 if (timing_params[i].all_dimms_registered)
616 assert_reset = 1;
617 }
618 if (assert_reset && !size_only) {
619 if (pinfo->board_mem_reset) {
620 debug("Asserting mem reset\n");
621 pinfo->board_mem_reset();
622 } else {
623 debug("Asserting mem reset missing\n");
624 }
625 }
626
627 case STEP_ASSIGN_ADDRESSES:
628 /* STEP 5: Assign addresses to chip selects */
629 check_interleaving_options(pinfo);
630 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
631 debug("Total mem %llu assigned\n", total_mem);
632
633 case STEP_COMPUTE_REGS:
634 /* STEP 6: compute controller register values */
635 debug("FSL Memory ctrl register computation\n");
636 for (i = first_ctrl; i <= last_ctrl; i++) {
637 if (timing_params[i].ndimms_present == 0) {
638 memset(&ddr_reg[i], 0,
639 sizeof(fsl_ddr_cfg_regs_t));
640 continue;
641 }
642
643 compute_fsl_memctl_config_regs
644 (i,
645 &pinfo->memctl_opts[i],
646 &ddr_reg[i], &timing_params[i],
647 pinfo->dimm_params[i],
648 dbw_capacity_adjust[i],
649 size_only);
650 }
651
652 default:
653 break;
654 }
655
656 {
657 /*
658 * Compute the amount of memory available just by
659 * looking for the highest valid CSn_BNDS value.
660 * This allows us to also experiment with using
661 * only CS0 when using dual-rank DIMMs.
662 */
663 unsigned int max_end = 0;
664
665 for (i = first_ctrl; i <= last_ctrl; i++) {
666 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
667 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
668 if (reg->cs[j].config & 0x80000000) {
669 unsigned int end;
670 /*
671 * 0xfffffff is a special value we put
672 * for unused bnds
673 */
674 if (reg->cs[j].bnds == 0xffffffff)
675 continue;
676 end = reg->cs[j].bnds & 0xffff;
677 if (end > max_end) {
678 max_end = end;
679 }
680 }
681 }
682 }
683
684 total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
685 0xFFFFFFULL) - pinfo->mem_base;
686 }
687
688 return total_mem;
689 }
690
__fsl_ddr_sdram(fsl_ddr_info_t * pinfo)691 phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
692 {
693 unsigned int i, first_ctrl, last_ctrl;
694 #ifdef CONFIG_PPC
695 unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
696 #endif
697 unsigned long long total_memory;
698 int deassert_reset = 0;
699
700 first_ctrl = pinfo->first_ctrl;
701 last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
702
703 /* Compute it once normally. */
704 #ifdef CONFIG_FSL_DDR_INTERACTIVE
705 if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */
706 total_memory = fsl_ddr_interactive(pinfo, 0);
707 } else if (fsl_ddr_interactive_env_var_exists()) {
708 total_memory = fsl_ddr_interactive(pinfo, 1);
709 } else
710 #endif
711 total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0);
712
713 /* setup 3-way interleaving before enabling DDRC */
714 switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) {
715 case FSL_DDR_3WAY_1KB_INTERLEAVING:
716 case FSL_DDR_3WAY_4KB_INTERLEAVING:
717 case FSL_DDR_3WAY_8KB_INTERLEAVING:
718 fsl_ddr_set_intl3r(
719 pinfo->memctl_opts[first_ctrl].
720 memctl_interleaving_mode);
721 break;
722 default:
723 break;
724 }
725
726 /*
727 * Program configuration registers.
728 * JEDEC specs requires clocks to be stable before deasserting reset
729 * for RDIMMs. Clocks start after chip select is enabled and clock
730 * control register is set. During step 1, all controllers have their
731 * registers set but not enabled. Step 2 proceeds after deasserting
732 * reset through board FPGA or GPIO.
733 * For non-registered DIMMs, initialization can go through but it is
734 * also OK to follow the same flow.
735 */
736 if (pinfo->board_need_mem_reset)
737 deassert_reset = pinfo->board_need_mem_reset();
738 for (i = first_ctrl; i <= last_ctrl; i++) {
739 if (pinfo->common_timing_params[i].all_dimms_registered)
740 deassert_reset = 1;
741 }
742 for (i = first_ctrl; i <= last_ctrl; i++) {
743 debug("Programming controller %u\n", i);
744 if (pinfo->common_timing_params[i].ndimms_present == 0) {
745 debug("No dimms present on controller %u; "
746 "skipping programming\n", i);
747 continue;
748 }
749 /*
750 * The following call with step = 1 returns before enabling
751 * the controller. It has to finish with step = 2 later.
752 */
753 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i,
754 deassert_reset ? 1 : 0);
755 }
756 if (deassert_reset) {
757 /* Use board FPGA or GPIO to deassert reset signal */
758 if (pinfo->board_mem_de_reset) {
759 debug("Deasserting mem reset\n");
760 pinfo->board_mem_de_reset();
761 } else {
762 debug("Deasserting mem reset missing\n");
763 }
764 for (i = first_ctrl; i <= last_ctrl; i++) {
765 /* Call with step = 2 to continue initialization */
766 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]),
767 i, 2);
768 }
769 }
770
771 #ifdef CONFIG_FSL_DDR_SYNC_REFRESH
772 fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl);
773 #endif
774
775 #ifdef CONFIG_PPC
776 /* program LAWs */
777 for (i = first_ctrl; i <= last_ctrl; i++) {
778 if (pinfo->memctl_opts[i].memctl_interleaving) {
779 switch (pinfo->memctl_opts[i].
780 memctl_interleaving_mode) {
781 case FSL_DDR_CACHE_LINE_INTERLEAVING:
782 case FSL_DDR_PAGE_INTERLEAVING:
783 case FSL_DDR_BANK_INTERLEAVING:
784 case FSL_DDR_SUPERBANK_INTERLEAVING:
785 if (i % 2)
786 break;
787 if (i == 0) {
788 law_memctl = LAW_TRGT_IF_DDR_INTRLV;
789 fsl_ddr_set_lawbar(
790 &pinfo->common_timing_params[i],
791 law_memctl, i);
792 }
793 #if CONFIG_SYS_NUM_DDR_CTLRS > 3
794 else if (i == 2) {
795 law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
796 fsl_ddr_set_lawbar(
797 &pinfo->common_timing_params[i],
798 law_memctl, i);
799 }
800 #endif
801 break;
802 case FSL_DDR_3WAY_1KB_INTERLEAVING:
803 case FSL_DDR_3WAY_4KB_INTERLEAVING:
804 case FSL_DDR_3WAY_8KB_INTERLEAVING:
805 law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
806 if (i == 0) {
807 fsl_ddr_set_lawbar(
808 &pinfo->common_timing_params[i],
809 law_memctl, i);
810 }
811 break;
812 case FSL_DDR_4WAY_1KB_INTERLEAVING:
813 case FSL_DDR_4WAY_4KB_INTERLEAVING:
814 case FSL_DDR_4WAY_8KB_INTERLEAVING:
815 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
816 if (i == 0)
817 fsl_ddr_set_lawbar(
818 &pinfo->common_timing_params[i],
819 law_memctl, i);
820 /* place holder for future 4-way interleaving */
821 break;
822 default:
823 break;
824 }
825 } else {
826 switch (i) {
827 case 0:
828 law_memctl = LAW_TRGT_IF_DDR_1;
829 break;
830 case 1:
831 law_memctl = LAW_TRGT_IF_DDR_2;
832 break;
833 case 2:
834 law_memctl = LAW_TRGT_IF_DDR_3;
835 break;
836 case 3:
837 law_memctl = LAW_TRGT_IF_DDR_4;
838 break;
839 default:
840 break;
841 }
842 fsl_ddr_set_lawbar(&pinfo->common_timing_params[i],
843 law_memctl, i);
844 }
845 }
846 #endif
847
848 debug("total_memory by %s = %llu\n", __func__, total_memory);
849
850 #if !defined(CONFIG_PHYS_64BIT)
851 /* Check for 4G or more. Bad. */
852 if ((first_ctrl == 0) && (total_memory >= (1ull << 32))) {
853 puts("Detected ");
854 print_size(total_memory, " of memory\n");
855 printf(" This U-Boot only supports < 4G of DDR\n");
856 printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
857 printf(" "); /* re-align to match init_dram print */
858 total_memory = CONFIG_MAX_MEM_MAPPED;
859 }
860 #endif
861
862 return total_memory;
863 }
864
865 /*
866 * fsl_ddr_sdram(void) -- this is the main function to be
867 * called by dram_init() in the board file.
868 *
869 * It returns amount of memory configured in bytes.
870 */
fsl_ddr_sdram(void)871 phys_size_t fsl_ddr_sdram(void)
872 {
873 fsl_ddr_info_t info;
874
875 /* Reset info structure. */
876 memset(&info, 0, sizeof(fsl_ddr_info_t));
877 info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
878 info.first_ctrl = 0;
879 info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
880 info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
881 info.board_need_mem_reset = board_need_mem_reset;
882 info.board_mem_reset = board_assert_mem_reset;
883 info.board_mem_de_reset = board_deassert_mem_reset;
884 remove_unused_controllers(&info);
885
886 return __fsl_ddr_sdram(&info);
887 }
888
889 #ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
fsl_other_ddr_sdram(unsigned long long base,unsigned int first_ctrl,unsigned int num_ctrls,unsigned int dimm_slots_per_ctrl,int (* board_need_reset)(void),void (* board_reset)(void),void (* board_de_reset)(void))890 phys_size_t fsl_other_ddr_sdram(unsigned long long base,
891 unsigned int first_ctrl,
892 unsigned int num_ctrls,
893 unsigned int dimm_slots_per_ctrl,
894 int (*board_need_reset)(void),
895 void (*board_reset)(void),
896 void (*board_de_reset)(void))
897 {
898 fsl_ddr_info_t info;
899
900 /* Reset info structure. */
901 memset(&info, 0, sizeof(fsl_ddr_info_t));
902 info.mem_base = base;
903 info.first_ctrl = first_ctrl;
904 info.num_ctrls = num_ctrls;
905 info.dimm_slots_per_ctrl = dimm_slots_per_ctrl;
906 info.board_need_mem_reset = board_need_reset;
907 info.board_mem_reset = board_reset;
908 info.board_mem_de_reset = board_de_reset;
909
910 return __fsl_ddr_sdram(&info);
911 }
912 #endif
913
914 /*
915 * fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the
916 * size of the total memory without setting ddr control registers.
917 */
918 phys_size_t
fsl_ddr_sdram_size(void)919 fsl_ddr_sdram_size(void)
920 {
921 fsl_ddr_info_t info;
922 unsigned long long total_memory = 0;
923
924 memset(&info, 0 , sizeof(fsl_ddr_info_t));
925 info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
926 info.first_ctrl = 0;
927 info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
928 info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
929 info.board_need_mem_reset = NULL;
930 remove_unused_controllers(&info);
931
932 /* Compute it once normally. */
933 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
934
935 return total_memory;
936 }
937