1 /*
2 * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <stdint.h>
10 #include <stdio.h>
11
12 #include <libfdt.h>
13
14 #include <platform_def.h>
15
16 #include <arch.h>
17 #include <arch_helpers.h>
18 #include <common/debug.h>
19 #include <drivers/delay_timer.h>
20 #include <drivers/generic_delay_timer.h>
21 #include <drivers/st/stm32mp_clkfunc.h>
22 #include <drivers/st/stm32mp1_clk.h>
23 #include <drivers/st/stm32mp1_rcc.h>
24 #include <dt-bindings/clock/stm32mp1-clksrc.h>
25 #include <lib/mmio.h>
26 #include <lib/spinlock.h>
27 #include <lib/utils_def.h>
28 #include <plat/common/platform.h>
29
30 #define MAX_HSI_HZ 64000000
31 #define USB_PHY_48_MHZ 48000000
32
33 #define TIMEOUT_US_200MS U(200000)
34 #define TIMEOUT_US_1S U(1000000)
35
36 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS
37 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS
38 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS
39 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS
40 #define OSCRDY_TIMEOUT TIMEOUT_US_1S
41
42 const char *stm32mp_osc_node_label[NB_OSC] = {
43 [_LSI] = "clk-lsi",
44 [_LSE] = "clk-lse",
45 [_HSI] = "clk-hsi",
46 [_HSE] = "clk-hse",
47 [_CSI] = "clk-csi",
48 [_I2S_CKIN] = "i2s_ckin",
49 };
50
51 enum stm32mp1_parent_id {
52 /* Oscillators are defined in enum stm32mp_osc_id */
53
54 /* Other parent source */
55 _HSI_KER = NB_OSC,
56 _HSE_KER,
57 _HSE_KER_DIV2,
58 _CSI_KER,
59 _PLL1_P,
60 _PLL1_Q,
61 _PLL1_R,
62 _PLL2_P,
63 _PLL2_Q,
64 _PLL2_R,
65 _PLL3_P,
66 _PLL3_Q,
67 _PLL3_R,
68 _PLL4_P,
69 _PLL4_Q,
70 _PLL4_R,
71 _ACLK,
72 _PCLK1,
73 _PCLK2,
74 _PCLK3,
75 _PCLK4,
76 _PCLK5,
77 _HCLK6,
78 _HCLK2,
79 _CK_PER,
80 _CK_MPU,
81 _CK_MCU,
82 _USB_PHY_48,
83 _PARENT_NB,
84 _UNKNOWN_ID = 0xff,
85 };
86
87 /* Lists only the parent clock we are interested in */
88 enum stm32mp1_parent_sel {
89 _I2C12_SEL,
90 _I2C35_SEL,
91 _STGEN_SEL,
92 _I2C46_SEL,
93 _SPI6_SEL,
94 _UART1_SEL,
95 _RNG1_SEL,
96 _UART6_SEL,
97 _UART24_SEL,
98 _UART35_SEL,
99 _UART78_SEL,
100 _SDMMC12_SEL,
101 _SDMMC3_SEL,
102 _QSPI_SEL,
103 _FMC_SEL,
104 _AXIS_SEL,
105 _MCUS_SEL,
106 _USBPHY_SEL,
107 _USBO_SEL,
108 _PARENT_SEL_NB,
109 _UNKNOWN_SEL = 0xff,
110 };
111
112 enum stm32mp1_pll_id {
113 _PLL1,
114 _PLL2,
115 _PLL3,
116 _PLL4,
117 _PLL_NB
118 };
119
120 enum stm32mp1_div_id {
121 _DIV_P,
122 _DIV_Q,
123 _DIV_R,
124 _DIV_NB,
125 };
126
127 enum stm32mp1_clksrc_id {
128 CLKSRC_MPU,
129 CLKSRC_AXI,
130 CLKSRC_MCU,
131 CLKSRC_PLL12,
132 CLKSRC_PLL3,
133 CLKSRC_PLL4,
134 CLKSRC_RTC,
135 CLKSRC_MCO1,
136 CLKSRC_MCO2,
137 CLKSRC_NB
138 };
139
140 enum stm32mp1_clkdiv_id {
141 CLKDIV_MPU,
142 CLKDIV_AXI,
143 CLKDIV_MCU,
144 CLKDIV_APB1,
145 CLKDIV_APB2,
146 CLKDIV_APB3,
147 CLKDIV_APB4,
148 CLKDIV_APB5,
149 CLKDIV_RTC,
150 CLKDIV_MCO1,
151 CLKDIV_MCO2,
152 CLKDIV_NB
153 };
154
155 enum stm32mp1_pllcfg {
156 PLLCFG_M,
157 PLLCFG_N,
158 PLLCFG_P,
159 PLLCFG_Q,
160 PLLCFG_R,
161 PLLCFG_O,
162 PLLCFG_NB
163 };
164
165 enum stm32mp1_pllcsg {
166 PLLCSG_MOD_PER,
167 PLLCSG_INC_STEP,
168 PLLCSG_SSCG_MODE,
169 PLLCSG_NB
170 };
171
172 enum stm32mp1_plltype {
173 PLL_800,
174 PLL_1600,
175 PLL_TYPE_NB
176 };
177
178 struct stm32mp1_pll {
179 uint8_t refclk_min;
180 uint8_t refclk_max;
181 uint8_t divn_max;
182 };
183
184 struct stm32mp1_clk_gate {
185 uint16_t offset;
186 uint8_t bit;
187 uint8_t index;
188 uint8_t set_clr;
189 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */
190 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */
191 };
192
193 struct stm32mp1_clk_sel {
194 uint16_t offset;
195 uint8_t src;
196 uint8_t msk;
197 uint8_t nb_parent;
198 const uint8_t *parent;
199 };
200
201 #define REFCLK_SIZE 4
202 struct stm32mp1_clk_pll {
203 enum stm32mp1_plltype plltype;
204 uint16_t rckxselr;
205 uint16_t pllxcfgr1;
206 uint16_t pllxcfgr2;
207 uint16_t pllxfracr;
208 uint16_t pllxcr;
209 uint16_t pllxcsgr;
210 enum stm32mp_osc_id refclk[REFCLK_SIZE];
211 };
212
213 /* Clocks with selectable source and non set/clr register access */
214 #define _CLK_SELEC(off, b, idx, s) \
215 { \
216 .offset = (off), \
217 .bit = (b), \
218 .index = (idx), \
219 .set_clr = 0, \
220 .sel = (s), \
221 .fixed = _UNKNOWN_ID, \
222 }
223
224 /* Clocks with fixed source and non set/clr register access */
225 #define _CLK_FIXED(off, b, idx, f) \
226 { \
227 .offset = (off), \
228 .bit = (b), \
229 .index = (idx), \
230 .set_clr = 0, \
231 .sel = _UNKNOWN_SEL, \
232 .fixed = (f), \
233 }
234
235 /* Clocks with selectable source and set/clr register access */
236 #define _CLK_SC_SELEC(off, b, idx, s) \
237 { \
238 .offset = (off), \
239 .bit = (b), \
240 .index = (idx), \
241 .set_clr = 1, \
242 .sel = (s), \
243 .fixed = _UNKNOWN_ID, \
244 }
245
246 /* Clocks with fixed source and set/clr register access */
247 #define _CLK_SC_FIXED(off, b, idx, f) \
248 { \
249 .offset = (off), \
250 .bit = (b), \
251 .index = (idx), \
252 .set_clr = 1, \
253 .sel = _UNKNOWN_SEL, \
254 .fixed = (f), \
255 }
256
257 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \
258 [_ ## _label ## _SEL] = { \
259 .offset = _rcc_selr, \
260 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \
261 .msk = _rcc_selr ## _ ## _label ## SRC_MASK, \
262 .parent = (_parents), \
263 .nb_parent = ARRAY_SIZE(_parents) \
264 }
265
266 #define _CLK_PLL(idx, type, off1, off2, off3, \
267 off4, off5, off6, \
268 p1, p2, p3, p4) \
269 [(idx)] = { \
270 .plltype = (type), \
271 .rckxselr = (off1), \
272 .pllxcfgr1 = (off2), \
273 .pllxcfgr2 = (off3), \
274 .pllxfracr = (off4), \
275 .pllxcr = (off5), \
276 .pllxcsgr = (off6), \
277 .refclk[0] = (p1), \
278 .refclk[1] = (p2), \
279 .refclk[2] = (p3), \
280 .refclk[3] = (p4), \
281 }
282
283 static const uint8_t stm32mp1_clks[][2] = {
284 { CK_PER, _CK_PER },
285 { CK_MPU, _CK_MPU },
286 { CK_AXI, _ACLK },
287 { CK_MCU, _CK_MCU },
288 { CK_HSE, _HSE },
289 { CK_CSI, _CSI },
290 { CK_LSI, _LSI },
291 { CK_LSE, _LSE },
292 { CK_HSI, _HSI },
293 { CK_HSE_DIV2, _HSE_KER_DIV2 },
294 };
295
296 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate)
297
298 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
299 _CLK_FIXED(RCC_DDRITFCR, 0, DDRC1, _ACLK),
300 _CLK_FIXED(RCC_DDRITFCR, 1, DDRC1LP, _ACLK),
301 _CLK_FIXED(RCC_DDRITFCR, 2, DDRC2, _ACLK),
302 _CLK_FIXED(RCC_DDRITFCR, 3, DDRC2LP, _ACLK),
303 _CLK_FIXED(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
304 _CLK_FIXED(RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R),
305 _CLK_FIXED(RCC_DDRITFCR, 6, DDRCAPB, _PCLK4),
306 _CLK_FIXED(RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4),
307 _CLK_FIXED(RCC_DDRITFCR, 8, AXIDCG, _ACLK),
308 _CLK_FIXED(RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4),
309 _CLK_FIXED(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4),
310
311 _CLK_SC_FIXED(RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1),
312 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
313 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
314 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
315 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
316 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
317 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
318 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
319 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
320 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
321 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
322
323 _CLK_SC_FIXED(RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2),
324 _CLK_SC_SELEC(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
325
326 _CLK_SC_FIXED(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID),
327
328 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
329 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
330 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
331
332 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL),
333 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
334 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
335 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL),
336 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
337 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5),
338 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5),
339 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5),
340 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5),
341 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5),
342 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
343
344 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
345 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
346
347 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
348 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
349 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
350 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
351 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
352 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
353 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
354 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
355 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
356 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
357 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
358
359 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5),
360 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5),
361 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5),
362 _CLK_SC_SELEC(RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL),
363 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5),
364
365 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
366 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
367 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
368 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
369 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
370
371 _CLK_SELEC(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
372 };
373
374 static const uint8_t i2c12_parents[] = {
375 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER
376 };
377
378 static const uint8_t i2c35_parents[] = {
379 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER
380 };
381
382 static const uint8_t stgen_parents[] = {
383 _HSI_KER, _HSE_KER
384 };
385
386 static const uint8_t i2c46_parents[] = {
387 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER
388 };
389
390 static const uint8_t spi6_parents[] = {
391 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q
392 };
393
394 static const uint8_t usart1_parents[] = {
395 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER
396 };
397
398 static const uint8_t rng1_parents[] = {
399 _CSI, _PLL4_R, _LSE, _LSI
400 };
401
402 static const uint8_t uart6_parents[] = {
403 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER
404 };
405
406 static const uint8_t uart234578_parents[] = {
407 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER
408 };
409
410 static const uint8_t sdmmc12_parents[] = {
411 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER
412 };
413
414 static const uint8_t sdmmc3_parents[] = {
415 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER
416 };
417
418 static const uint8_t qspi_parents[] = {
419 _ACLK, _PLL3_R, _PLL4_P, _CK_PER
420 };
421
422 static const uint8_t fmc_parents[] = {
423 _ACLK, _PLL3_R, _PLL4_P, _CK_PER
424 };
425
426 static const uint8_t ass_parents[] = {
427 _HSI, _HSE, _PLL2
428 };
429
430 static const uint8_t mss_parents[] = {
431 _HSI, _HSE, _CSI, _PLL3
432 };
433
434 static const uint8_t usbphy_parents[] = {
435 _HSE_KER, _PLL4_R, _HSE_KER_DIV2
436 };
437
438 static const uint8_t usbo_parents[] = {
439 _PLL4_R, _USB_PHY_48
440 };
441
442 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
443 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents),
444 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents),
445 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents),
446 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents),
447 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents),
448 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents),
449 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents),
450 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents),
451 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents),
452 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents),
453 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents),
454 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents),
455 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents),
456 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents),
457 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents),
458 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, ass_parents),
459 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mss_parents),
460 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents),
461 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents),
462 };
463
464 /* Define characteristic of PLL according type */
465 #define DIVN_MIN 24
466 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
467 [PLL_800] = {
468 .refclk_min = 4,
469 .refclk_max = 16,
470 .divn_max = 99,
471 },
472 [PLL_1600] = {
473 .refclk_min = 8,
474 .refclk_max = 16,
475 .divn_max = 199,
476 },
477 };
478
479 /* PLLNCFGR2 register divider by output */
480 static const uint8_t pllncfgr2[_DIV_NB] = {
481 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
482 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
483 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT,
484 };
485
486 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
487 _CLK_PLL(_PLL1, PLL_1600,
488 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
489 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
490 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID),
491 _CLK_PLL(_PLL2, PLL_1600,
492 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
493 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
494 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID),
495 _CLK_PLL(_PLL3, PLL_800,
496 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
497 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
498 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID),
499 _CLK_PLL(_PLL4, PLL_800,
500 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
501 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
502 _HSI, _HSE, _CSI, _I2S_CKIN),
503 };
504
505 /* Prescaler table lookups for clock computation */
506 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
507 static const uint8_t stm32mp1_mcu_div[16] = {
508 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
509 };
510
511 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */
512 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
513 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
514 static const uint8_t stm32mp1_mpu_apbx_div[8] = {
515 0, 1, 2, 3, 4, 4, 4, 4
516 };
517
518 /* div = /1 /2 /3 /4 */
519 static const uint8_t stm32mp1_axi_div[8] = {
520 1, 2, 3, 4, 4, 4, 4, 4
521 };
522
523 /* RCC clock device driver private */
524 static unsigned long stm32mp1_osc[NB_OSC];
525 static struct spinlock reg_lock;
526 static unsigned int gate_refcounts[NB_GATES];
527 static struct spinlock refcount_lock;
528
gate_ref(unsigned int idx)529 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx)
530 {
531 return &stm32mp1_clk_gate[idx];
532 }
533
clk_sel_ref(unsigned int idx)534 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx)
535 {
536 return &stm32mp1_clk_sel[idx];
537 }
538
pll_ref(unsigned int idx)539 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx)
540 {
541 return &stm32mp1_clk_pll[idx];
542 }
543
stm32mp1_clk_lock(struct spinlock * lock)544 static void stm32mp1_clk_lock(struct spinlock *lock)
545 {
546 if (stm32mp_lock_available()) {
547 /* Assume interrupts are masked */
548 spin_lock(lock);
549 }
550 }
551
stm32mp1_clk_unlock(struct spinlock * lock)552 static void stm32mp1_clk_unlock(struct spinlock *lock)
553 {
554 if (stm32mp_lock_available()) {
555 spin_unlock(lock);
556 }
557 }
558
stm32mp1_rcc_is_secure(void)559 bool stm32mp1_rcc_is_secure(void)
560 {
561 uintptr_t rcc_base = stm32mp_rcc_base();
562
563 return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_TZEN) != 0;
564 }
565
stm32mp1_rcc_is_mckprot(void)566 bool stm32mp1_rcc_is_mckprot(void)
567 {
568 uintptr_t rcc_base = stm32mp_rcc_base();
569
570 return (mmio_read_32(rcc_base + RCC_TZCR) & RCC_TZCR_MCKPROT) != 0;
571 }
572
stm32mp1_clk_rcc_regs_lock(void)573 void stm32mp1_clk_rcc_regs_lock(void)
574 {
575 stm32mp1_clk_lock(®_lock);
576 }
577
stm32mp1_clk_rcc_regs_unlock(void)578 void stm32mp1_clk_rcc_regs_unlock(void)
579 {
580 stm32mp1_clk_unlock(®_lock);
581 }
582
stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx)583 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx)
584 {
585 if (idx >= NB_OSC) {
586 return 0;
587 }
588
589 return stm32mp1_osc[idx];
590 }
591
stm32mp1_clk_get_gated_id(unsigned long id)592 static int stm32mp1_clk_get_gated_id(unsigned long id)
593 {
594 unsigned int i;
595
596 for (i = 0U; i < NB_GATES; i++) {
597 if (gate_ref(i)->index == id) {
598 return i;
599 }
600 }
601
602 ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id);
603
604 return -EINVAL;
605 }
606
stm32mp1_clk_get_sel(int i)607 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i)
608 {
609 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel);
610 }
611
stm32mp1_clk_get_fixed_parent(int i)612 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i)
613 {
614 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed);
615 }
616
stm32mp1_clk_get_parent(unsigned long id)617 static int stm32mp1_clk_get_parent(unsigned long id)
618 {
619 const struct stm32mp1_clk_sel *sel;
620 uint32_t j, p_sel;
621 int i;
622 enum stm32mp1_parent_id p;
623 enum stm32mp1_parent_sel s;
624 uintptr_t rcc_base = stm32mp_rcc_base();
625
626 for (j = 0U; j < ARRAY_SIZE(stm32mp1_clks); j++) {
627 if (stm32mp1_clks[j][0] == id) {
628 return (int)stm32mp1_clks[j][1];
629 }
630 }
631
632 i = stm32mp1_clk_get_gated_id(id);
633 if (i < 0) {
634 panic();
635 }
636
637 p = stm32mp1_clk_get_fixed_parent(i);
638 if (p < _PARENT_NB) {
639 return (int)p;
640 }
641
642 s = stm32mp1_clk_get_sel(i);
643 if (s == _UNKNOWN_SEL) {
644 return -EINVAL;
645 }
646 if (s >= _PARENT_SEL_NB) {
647 panic();
648 }
649
650 sel = clk_sel_ref(s);
651 p_sel = (mmio_read_32(rcc_base + sel->offset) & sel->msk) >> sel->src;
652 if (p_sel < sel->nb_parent) {
653 return (int)sel->parent[p_sel];
654 }
655
656 return -EINVAL;
657 }
658
stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll * pll)659 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll)
660 {
661 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr);
662 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK;
663
664 return stm32mp1_clk_get_fixed(pll->refclk[src]);
665 }
666
667 /*
668 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
669 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
670 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
671 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
672 */
stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll * pll)673 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll)
674 {
675 unsigned long refclk, fvco;
676 uint32_t cfgr1, fracr, divm, divn;
677 uintptr_t rcc_base = stm32mp_rcc_base();
678
679 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1);
680 fracr = mmio_read_32(rcc_base + pll->pllxfracr);
681
682 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
683 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
684
685 refclk = stm32mp1_pll_get_fref(pll);
686
687 /*
688 * With FRACV :
689 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
690 * Without FRACV
691 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
692 */
693 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) {
694 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >>
695 RCC_PLLNFRACR_FRACV_SHIFT;
696 unsigned long long numerator, denominator;
697
698 numerator = (((unsigned long long)divn + 1U) << 13) + fracv;
699 numerator = refclk * numerator;
700 denominator = ((unsigned long long)divm + 1U) << 13;
701 fvco = (unsigned long)(numerator / denominator);
702 } else {
703 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U));
704 }
705
706 return fvco;
707 }
708
stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id,enum stm32mp1_div_id div_id)709 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id,
710 enum stm32mp1_div_id div_id)
711 {
712 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
713 unsigned long dfout;
714 uint32_t cfgr2, divy;
715
716 if (div_id >= _DIV_NB) {
717 return 0;
718 }
719
720 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2);
721 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
722
723 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U);
724
725 return dfout;
726 }
727
get_clock_rate(int p)728 static unsigned long get_clock_rate(int p)
729 {
730 uint32_t reg, clkdiv;
731 unsigned long clock = 0;
732 uintptr_t rcc_base = stm32mp_rcc_base();
733
734 switch (p) {
735 case _CK_MPU:
736 /* MPU sub system */
737 reg = mmio_read_32(rcc_base + RCC_MPCKSELR);
738 switch (reg & RCC_SELR_SRC_MASK) {
739 case RCC_MPCKSELR_HSI:
740 clock = stm32mp1_clk_get_fixed(_HSI);
741 break;
742 case RCC_MPCKSELR_HSE:
743 clock = stm32mp1_clk_get_fixed(_HSE);
744 break;
745 case RCC_MPCKSELR_PLL:
746 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
747 break;
748 case RCC_MPCKSELR_PLL_MPUDIV:
749 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
750
751 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR);
752 clkdiv = reg & RCC_MPUDIV_MASK;
753 if (clkdiv != 0U) {
754 clock /= stm32mp1_mpu_div[clkdiv];
755 }
756 break;
757 default:
758 break;
759 }
760 break;
761 /* AXI sub system */
762 case _ACLK:
763 case _HCLK2:
764 case _HCLK6:
765 case _PCLK4:
766 case _PCLK5:
767 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR);
768 switch (reg & RCC_SELR_SRC_MASK) {
769 case RCC_ASSCKSELR_HSI:
770 clock = stm32mp1_clk_get_fixed(_HSI);
771 break;
772 case RCC_ASSCKSELR_HSE:
773 clock = stm32mp1_clk_get_fixed(_HSE);
774 break;
775 case RCC_ASSCKSELR_PLL:
776 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P);
777 break;
778 default:
779 break;
780 }
781
782 /* System clock divider */
783 reg = mmio_read_32(rcc_base + RCC_AXIDIVR);
784 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
785
786 switch (p) {
787 case _PCLK4:
788 reg = mmio_read_32(rcc_base + RCC_APB4DIVR);
789 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
790 break;
791 case _PCLK5:
792 reg = mmio_read_32(rcc_base + RCC_APB5DIVR);
793 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
794 break;
795 default:
796 break;
797 }
798 break;
799 /* MCU sub system */
800 case _CK_MCU:
801 case _PCLK1:
802 case _PCLK2:
803 case _PCLK3:
804 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR);
805 switch (reg & RCC_SELR_SRC_MASK) {
806 case RCC_MSSCKSELR_HSI:
807 clock = stm32mp1_clk_get_fixed(_HSI);
808 break;
809 case RCC_MSSCKSELR_HSE:
810 clock = stm32mp1_clk_get_fixed(_HSE);
811 break;
812 case RCC_MSSCKSELR_CSI:
813 clock = stm32mp1_clk_get_fixed(_CSI);
814 break;
815 case RCC_MSSCKSELR_PLL:
816 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P);
817 break;
818 default:
819 break;
820 }
821
822 /* MCU clock divider */
823 reg = mmio_read_32(rcc_base + RCC_MCUDIVR);
824 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
825
826 switch (p) {
827 case _PCLK1:
828 reg = mmio_read_32(rcc_base + RCC_APB1DIVR);
829 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
830 break;
831 case _PCLK2:
832 reg = mmio_read_32(rcc_base + RCC_APB2DIVR);
833 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
834 break;
835 case _PCLK3:
836 reg = mmio_read_32(rcc_base + RCC_APB3DIVR);
837 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
838 break;
839 case _CK_MCU:
840 default:
841 break;
842 }
843 break;
844 case _CK_PER:
845 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR);
846 switch (reg & RCC_SELR_SRC_MASK) {
847 case RCC_CPERCKSELR_HSI:
848 clock = stm32mp1_clk_get_fixed(_HSI);
849 break;
850 case RCC_CPERCKSELR_HSE:
851 clock = stm32mp1_clk_get_fixed(_HSE);
852 break;
853 case RCC_CPERCKSELR_CSI:
854 clock = stm32mp1_clk_get_fixed(_CSI);
855 break;
856 default:
857 break;
858 }
859 break;
860 case _HSI:
861 case _HSI_KER:
862 clock = stm32mp1_clk_get_fixed(_HSI);
863 break;
864 case _CSI:
865 case _CSI_KER:
866 clock = stm32mp1_clk_get_fixed(_CSI);
867 break;
868 case _HSE:
869 case _HSE_KER:
870 clock = stm32mp1_clk_get_fixed(_HSE);
871 break;
872 case _HSE_KER_DIV2:
873 clock = stm32mp1_clk_get_fixed(_HSE) >> 1;
874 break;
875 case _LSI:
876 clock = stm32mp1_clk_get_fixed(_LSI);
877 break;
878 case _LSE:
879 clock = stm32mp1_clk_get_fixed(_LSE);
880 break;
881 /* PLL */
882 case _PLL1_P:
883 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
884 break;
885 case _PLL1_Q:
886 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q);
887 break;
888 case _PLL1_R:
889 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R);
890 break;
891 case _PLL2_P:
892 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P);
893 break;
894 case _PLL2_Q:
895 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q);
896 break;
897 case _PLL2_R:
898 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R);
899 break;
900 case _PLL3_P:
901 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P);
902 break;
903 case _PLL3_Q:
904 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q);
905 break;
906 case _PLL3_R:
907 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R);
908 break;
909 case _PLL4_P:
910 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P);
911 break;
912 case _PLL4_Q:
913 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q);
914 break;
915 case _PLL4_R:
916 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R);
917 break;
918 /* Other */
919 case _USB_PHY_48:
920 clock = USB_PHY_48_MHZ;
921 break;
922 default:
923 break;
924 }
925
926 return clock;
927 }
928
__clk_enable(struct stm32mp1_clk_gate const * gate)929 static void __clk_enable(struct stm32mp1_clk_gate const *gate)
930 {
931 uintptr_t rcc_base = stm32mp_rcc_base();
932
933 if (gate->set_clr != 0U) {
934 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit));
935 } else {
936 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit));
937 }
938
939 VERBOSE("Clock %d has been enabled", gate->index);
940 }
941
__clk_disable(struct stm32mp1_clk_gate const * gate)942 static void __clk_disable(struct stm32mp1_clk_gate const *gate)
943 {
944 uintptr_t rcc_base = stm32mp_rcc_base();
945
946 if (gate->set_clr != 0U) {
947 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET,
948 BIT(gate->bit));
949 } else {
950 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit));
951 }
952
953 VERBOSE("Clock %d has been disabled", gate->index);
954 }
955
__clk_is_enabled(struct stm32mp1_clk_gate const * gate)956 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate)
957 {
958 uintptr_t rcc_base = stm32mp_rcc_base();
959
960 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit);
961 }
962
stm32mp1_clk_get_refcount(unsigned long id)963 unsigned int stm32mp1_clk_get_refcount(unsigned long id)
964 {
965 int i = stm32mp1_clk_get_gated_id(id);
966
967 if (i < 0) {
968 panic();
969 }
970
971 return gate_refcounts[i];
972 }
973
__stm32mp1_clk_enable(unsigned long id,bool secure)974 void __stm32mp1_clk_enable(unsigned long id, bool secure)
975 {
976 const struct stm32mp1_clk_gate *gate;
977 int i = stm32mp1_clk_get_gated_id(id);
978 unsigned int *refcnt;
979
980 if (i < 0) {
981 ERROR("Clock %d can't be enabled\n", (uint32_t)id);
982 panic();
983 }
984
985 gate = gate_ref(i);
986 refcnt = &gate_refcounts[i];
987
988 stm32mp1_clk_lock(&refcount_lock);
989
990 if (stm32mp_incr_shrefcnt(refcnt, secure) != 0) {
991 __clk_enable(gate);
992 }
993
994 stm32mp1_clk_unlock(&refcount_lock);
995 }
996
__stm32mp1_clk_disable(unsigned long id,bool secure)997 void __stm32mp1_clk_disable(unsigned long id, bool secure)
998 {
999 const struct stm32mp1_clk_gate *gate;
1000 int i = stm32mp1_clk_get_gated_id(id);
1001 unsigned int *refcnt;
1002
1003 if (i < 0) {
1004 ERROR("Clock %d can't be disabled\n", (uint32_t)id);
1005 panic();
1006 }
1007
1008 gate = gate_ref(i);
1009 refcnt = &gate_refcounts[i];
1010
1011 stm32mp1_clk_lock(&refcount_lock);
1012
1013 if (stm32mp_decr_shrefcnt(refcnt, secure) != 0) {
1014 __clk_disable(gate);
1015 }
1016
1017 stm32mp1_clk_unlock(&refcount_lock);
1018 }
1019
stm32mp_clk_enable(unsigned long id)1020 void stm32mp_clk_enable(unsigned long id)
1021 {
1022 __stm32mp1_clk_enable(id, true);
1023 }
1024
stm32mp_clk_disable(unsigned long id)1025 void stm32mp_clk_disable(unsigned long id)
1026 {
1027 __stm32mp1_clk_disable(id, true);
1028 }
1029
stm32mp_clk_is_enabled(unsigned long id)1030 bool stm32mp_clk_is_enabled(unsigned long id)
1031 {
1032 int i = stm32mp1_clk_get_gated_id(id);
1033
1034 if (i < 0) {
1035 panic();
1036 }
1037
1038 return __clk_is_enabled(gate_ref(i));
1039 }
1040
stm32mp_clk_get_rate(unsigned long id)1041 unsigned long stm32mp_clk_get_rate(unsigned long id)
1042 {
1043 int p = stm32mp1_clk_get_parent(id);
1044
1045 if (p < 0) {
1046 return 0;
1047 }
1048
1049 return get_clock_rate(p);
1050 }
1051
stm32mp1_ls_osc_set(bool enable,uint32_t offset,uint32_t mask_on)1052 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on)
1053 {
1054 uintptr_t address = stm32mp_rcc_base() + offset;
1055
1056 if (enable) {
1057 mmio_setbits_32(address, mask_on);
1058 } else {
1059 mmio_clrbits_32(address, mask_on);
1060 }
1061 }
1062
stm32mp1_hs_ocs_set(bool enable,uint32_t mask_on)1063 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on)
1064 {
1065 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR;
1066 uintptr_t address = stm32mp_rcc_base() + offset;
1067
1068 mmio_write_32(address, mask_on);
1069 }
1070
stm32mp1_osc_wait(bool enable,uint32_t offset,uint32_t mask_rdy)1071 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy)
1072 {
1073 uint64_t timeout;
1074 uint32_t mask_test;
1075 uintptr_t address = stm32mp_rcc_base() + offset;
1076
1077 if (enable) {
1078 mask_test = mask_rdy;
1079 } else {
1080 mask_test = 0;
1081 }
1082
1083 timeout = timeout_init_us(OSCRDY_TIMEOUT);
1084 while ((mmio_read_32(address) & mask_rdy) != mask_test) {
1085 if (timeout_elapsed(timeout)) {
1086 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n",
1087 mask_rdy, address, enable, mmio_read_32(address));
1088 return -ETIMEDOUT;
1089 }
1090 }
1091
1092 return 0;
1093 }
1094
stm32mp1_lse_enable(bool bypass,bool digbyp,uint32_t lsedrv)1095 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv)
1096 {
1097 uint32_t value;
1098 uintptr_t rcc_base = stm32mp_rcc_base();
1099
1100 if (digbyp) {
1101 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP);
1102 }
1103
1104 if (bypass || digbyp) {
1105 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP);
1106 }
1107
1108 /*
1109 * Warning: not recommended to switch directly from "high drive"
1110 * to "medium low drive", and vice-versa.
1111 */
1112 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >>
1113 RCC_BDCR_LSEDRV_SHIFT;
1114
1115 while (value != lsedrv) {
1116 if (value > lsedrv) {
1117 value--;
1118 } else {
1119 value++;
1120 }
1121
1122 mmio_clrsetbits_32(rcc_base + RCC_BDCR,
1123 RCC_BDCR_LSEDRV_MASK,
1124 value << RCC_BDCR_LSEDRV_SHIFT);
1125 }
1126
1127 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON);
1128 }
1129
stm32mp1_lse_wait(void)1130 static void stm32mp1_lse_wait(void)
1131 {
1132 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) {
1133 VERBOSE("%s: failed\n", __func__);
1134 }
1135 }
1136
stm32mp1_lsi_set(bool enable)1137 static void stm32mp1_lsi_set(bool enable)
1138 {
1139 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION);
1140
1141 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) {
1142 VERBOSE("%s: failed\n", __func__);
1143 }
1144 }
1145
stm32mp1_hse_enable(bool bypass,bool digbyp,bool css)1146 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css)
1147 {
1148 uintptr_t rcc_base = stm32mp_rcc_base();
1149
1150 if (digbyp) {
1151 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP);
1152 }
1153
1154 if (bypass || digbyp) {
1155 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP);
1156 }
1157
1158 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON);
1159 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) {
1160 VERBOSE("%s: failed\n", __func__);
1161 }
1162
1163 if (css) {
1164 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON);
1165 }
1166 }
1167
stm32mp1_csi_set(bool enable)1168 static void stm32mp1_csi_set(bool enable)
1169 {
1170 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION);
1171 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) {
1172 VERBOSE("%s: failed\n", __func__);
1173 }
1174 }
1175
stm32mp1_hsi_set(bool enable)1176 static void stm32mp1_hsi_set(bool enable)
1177 {
1178 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION);
1179 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) {
1180 VERBOSE("%s: failed\n", __func__);
1181 }
1182 }
1183
stm32mp1_set_hsidiv(uint8_t hsidiv)1184 static int stm32mp1_set_hsidiv(uint8_t hsidiv)
1185 {
1186 uint64_t timeout;
1187 uintptr_t rcc_base = stm32mp_rcc_base();
1188 uintptr_t address = rcc_base + RCC_OCRDYR;
1189
1190 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR,
1191 RCC_HSICFGR_HSIDIV_MASK,
1192 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv);
1193
1194 timeout = timeout_init_us(HSIDIV_TIMEOUT);
1195 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) {
1196 if (timeout_elapsed(timeout)) {
1197 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n",
1198 address, mmio_read_32(address));
1199 return -ETIMEDOUT;
1200 }
1201 }
1202
1203 return 0;
1204 }
1205
stm32mp1_hsidiv(unsigned long hsifreq)1206 static int stm32mp1_hsidiv(unsigned long hsifreq)
1207 {
1208 uint8_t hsidiv;
1209 uint32_t hsidivfreq = MAX_HSI_HZ;
1210
1211 for (hsidiv = 0; hsidiv < 4U; hsidiv++) {
1212 if (hsidivfreq == hsifreq) {
1213 break;
1214 }
1215
1216 hsidivfreq /= 2U;
1217 }
1218
1219 if (hsidiv == 4U) {
1220 ERROR("Invalid clk-hsi frequency\n");
1221 return -1;
1222 }
1223
1224 if (hsidiv != 0U) {
1225 return stm32mp1_set_hsidiv(hsidiv);
1226 }
1227
1228 return 0;
1229 }
1230
stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id,unsigned int clksrc,uint32_t * pllcfg,int plloff)1231 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id,
1232 unsigned int clksrc,
1233 uint32_t *pllcfg, int plloff)
1234 {
1235 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1236 uintptr_t rcc_base = stm32mp_rcc_base();
1237 uintptr_t pllxcr = rcc_base + pll->pllxcr;
1238 enum stm32mp1_plltype type = pll->plltype;
1239 uintptr_t clksrc_address = rcc_base + (clksrc >> 4);
1240 unsigned long refclk;
1241 uint32_t ifrge = 0U;
1242 uint32_t src, value, fracv;
1243
1244 /* Check PLL output */
1245 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) {
1246 return false;
1247 }
1248
1249 /* Check current clksrc */
1250 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK;
1251 if (src != (clksrc & RCC_SELR_SRC_MASK)) {
1252 return false;
1253 }
1254
1255 /* Check Div */
1256 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK;
1257
1258 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) /
1259 (pllcfg[PLLCFG_M] + 1U);
1260
1261 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) ||
1262 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) {
1263 return false;
1264 }
1265
1266 if ((type == PLL_800) && (refclk >= 8000000U)) {
1267 ifrge = 1U;
1268 }
1269
1270 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &
1271 RCC_PLLNCFGR1_DIVN_MASK;
1272 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &
1273 RCC_PLLNCFGR1_DIVM_MASK;
1274 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) &
1275 RCC_PLLNCFGR1_IFRGE_MASK;
1276 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) {
1277 return false;
1278 }
1279
1280 /* Fractional configuration */
1281 fracv = fdt_read_uint32_default(plloff, "frac", 0);
1282
1283 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT;
1284 value |= RCC_PLLNFRACR_FRACLE;
1285 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) {
1286 return false;
1287 }
1288
1289 /* Output config */
1290 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &
1291 RCC_PLLNCFGR2_DIVP_MASK;
1292 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &
1293 RCC_PLLNCFGR2_DIVQ_MASK;
1294 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &
1295 RCC_PLLNCFGR2_DIVR_MASK;
1296 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) {
1297 return false;
1298 }
1299
1300 return true;
1301 }
1302
stm32mp1_pll_start(enum stm32mp1_pll_id pll_id)1303 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id)
1304 {
1305 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1306 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
1307
1308 /* Preserve RCC_PLLNCR_SSCG_CTRL value */
1309 mmio_clrsetbits_32(pllxcr,
1310 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1311 RCC_PLLNCR_DIVREN,
1312 RCC_PLLNCR_PLLON);
1313 }
1314
stm32mp1_pll_output(enum stm32mp1_pll_id pll_id,uint32_t output)1315 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output)
1316 {
1317 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1318 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
1319 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT);
1320
1321 /* Wait PLL lock */
1322 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) {
1323 if (timeout_elapsed(timeout)) {
1324 ERROR("PLL%d start failed @ 0x%lx: 0x%x\n",
1325 pll_id, pllxcr, mmio_read_32(pllxcr));
1326 return -ETIMEDOUT;
1327 }
1328 }
1329
1330 /* Start the requested output */
1331 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
1332
1333 return 0;
1334 }
1335
stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id)1336 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id)
1337 {
1338 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1339 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr;
1340 uint64_t timeout;
1341
1342 /* Stop all output */
1343 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
1344 RCC_PLLNCR_DIVREN);
1345
1346 /* Stop PLL */
1347 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON);
1348
1349 timeout = timeout_init_us(PLLRDY_TIMEOUT);
1350 /* Wait PLL stopped */
1351 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) {
1352 if (timeout_elapsed(timeout)) {
1353 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n",
1354 pll_id, pllxcr, mmio_read_32(pllxcr));
1355 return -ETIMEDOUT;
1356 }
1357 }
1358
1359 return 0;
1360 }
1361
stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id,uint32_t * pllcfg)1362 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id,
1363 uint32_t *pllcfg)
1364 {
1365 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1366 uintptr_t rcc_base = stm32mp_rcc_base();
1367 uint32_t value;
1368
1369 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &
1370 RCC_PLLNCFGR2_DIVP_MASK;
1371 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &
1372 RCC_PLLNCFGR2_DIVQ_MASK;
1373 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &
1374 RCC_PLLNCFGR2_DIVR_MASK;
1375 mmio_write_32(rcc_base + pll->pllxcfgr2, value);
1376 }
1377
stm32mp1_pll_config(enum stm32mp1_pll_id pll_id,uint32_t * pllcfg,uint32_t fracv)1378 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id,
1379 uint32_t *pllcfg, uint32_t fracv)
1380 {
1381 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1382 uintptr_t rcc_base = stm32mp_rcc_base();
1383 enum stm32mp1_plltype type = pll->plltype;
1384 unsigned long refclk;
1385 uint32_t ifrge = 0;
1386 uint32_t src, value;
1387
1388 src = mmio_read_32(rcc_base + pll->rckxselr) &
1389 RCC_SELR_REFCLK_SRC_MASK;
1390
1391 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) /
1392 (pllcfg[PLLCFG_M] + 1U);
1393
1394 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) ||
1395 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) {
1396 return -EINVAL;
1397 }
1398
1399 if ((type == PLL_800) && (refclk >= 8000000U)) {
1400 ifrge = 1U;
1401 }
1402
1403 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &
1404 RCC_PLLNCFGR1_DIVN_MASK;
1405 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &
1406 RCC_PLLNCFGR1_DIVM_MASK;
1407 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) &
1408 RCC_PLLNCFGR1_IFRGE_MASK;
1409 mmio_write_32(rcc_base + pll->pllxcfgr1, value);
1410
1411 /* Fractional configuration */
1412 value = 0;
1413 mmio_write_32(rcc_base + pll->pllxfracr, value);
1414
1415 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT;
1416 mmio_write_32(rcc_base + pll->pllxfracr, value);
1417
1418 value |= RCC_PLLNFRACR_FRACLE;
1419 mmio_write_32(rcc_base + pll->pllxfracr, value);
1420
1421 stm32mp1_pll_config_output(pll_id, pllcfg);
1422
1423 return 0;
1424 }
1425
stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id,uint32_t * csg)1426 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg)
1427 {
1428 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
1429 uint32_t pllxcsg = 0;
1430
1431 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
1432 RCC_PLLNCSGR_MOD_PER_MASK;
1433
1434 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
1435 RCC_PLLNCSGR_INC_STEP_MASK;
1436
1437 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
1438 RCC_PLLNCSGR_SSCG_MODE_MASK;
1439
1440 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg);
1441
1442 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr,
1443 RCC_PLLNCR_SSCG_CTRL);
1444 }
1445
stm32mp1_set_clksrc(unsigned int clksrc)1446 static int stm32mp1_set_clksrc(unsigned int clksrc)
1447 {
1448 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4);
1449 uint64_t timeout;
1450
1451 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK,
1452 clksrc & RCC_SELR_SRC_MASK);
1453
1454 timeout = timeout_init_us(CLKSRC_TIMEOUT);
1455 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) {
1456 if (timeout_elapsed(timeout)) {
1457 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc,
1458 clksrc_address, mmio_read_32(clksrc_address));
1459 return -ETIMEDOUT;
1460 }
1461 }
1462
1463 return 0;
1464 }
1465
stm32mp1_set_clkdiv(unsigned int clkdiv,uintptr_t address)1466 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address)
1467 {
1468 uint64_t timeout;
1469
1470 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK,
1471 clkdiv & RCC_DIVR_DIV_MASK);
1472
1473 timeout = timeout_init_us(CLKDIV_TIMEOUT);
1474 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) {
1475 if (timeout_elapsed(timeout)) {
1476 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n",
1477 clkdiv, address, mmio_read_32(address));
1478 return -ETIMEDOUT;
1479 }
1480 }
1481
1482 return 0;
1483 }
1484
stm32mp1_mco_csg(uint32_t clksrc,uint32_t clkdiv)1485 static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv)
1486 {
1487 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4);
1488
1489 /*
1490 * Binding clksrc :
1491 * bit15-4 offset
1492 * bit3: disable
1493 * bit2-0: MCOSEL[2:0]
1494 */
1495 if ((clksrc & 0x8U) != 0U) {
1496 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON);
1497 } else {
1498 mmio_clrsetbits_32(clksrc_address,
1499 RCC_MCOCFG_MCOSRC_MASK,
1500 clksrc & RCC_MCOCFG_MCOSRC_MASK);
1501 mmio_clrsetbits_32(clksrc_address,
1502 RCC_MCOCFG_MCODIV_MASK,
1503 clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
1504 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON);
1505 }
1506 }
1507
stm32mp1_set_rtcsrc(unsigned int clksrc,bool lse_css)1508 static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css)
1509 {
1510 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR;
1511
1512 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) ||
1513 (clksrc != (uint32_t)CLK_RTC_DISABLED)) {
1514 mmio_clrsetbits_32(address,
1515 RCC_BDCR_RTCSRC_MASK,
1516 clksrc << RCC_BDCR_RTCSRC_SHIFT);
1517
1518 mmio_setbits_32(address, RCC_BDCR_RTCCKEN);
1519 }
1520
1521 if (lse_css) {
1522 mmio_setbits_32(address, RCC_BDCR_LSECSSON);
1523 }
1524 }
1525
stm32mp1_stgen_config(void)1526 static void stm32mp1_stgen_config(void)
1527 {
1528 uintptr_t stgen;
1529 uint32_t cntfid0;
1530 unsigned long rate;
1531 unsigned long long counter;
1532
1533 stgen = fdt_get_stgen_base();
1534 cntfid0 = mmio_read_32(stgen + CNTFID_OFF);
1535 rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K));
1536
1537 if (cntfid0 == rate) {
1538 return;
1539 }
1540
1541 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN);
1542 counter = (unsigned long long)mmio_read_32(stgen + CNTCVL_OFF);
1543 counter |= ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF)) << 32;
1544 counter = (counter * rate / cntfid0);
1545
1546 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter);
1547 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32));
1548 mmio_write_32(stgen + CNTFID_OFF, rate);
1549 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN);
1550
1551 write_cntfrq((u_register_t)rate);
1552
1553 /* Need to update timer with new frequency */
1554 generic_delay_timer_init();
1555 }
1556
stm32mp1_stgen_increment(unsigned long long offset_in_ms)1557 void stm32mp1_stgen_increment(unsigned long long offset_in_ms)
1558 {
1559 uintptr_t stgen;
1560 unsigned long long cnt;
1561
1562 stgen = fdt_get_stgen_base();
1563
1564 cnt = ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF) << 32) |
1565 mmio_read_32(stgen + CNTCVL_OFF);
1566
1567 cnt += (offset_in_ms * mmio_read_32(stgen + CNTFID_OFF)) / 1000U;
1568
1569 mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN);
1570 mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)cnt);
1571 mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(cnt >> 32));
1572 mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN);
1573 }
1574
stm32mp1_pkcs_config(uint32_t pkcs)1575 static void stm32mp1_pkcs_config(uint32_t pkcs)
1576 {
1577 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU);
1578 uint32_t value = pkcs & 0xFU;
1579 uint32_t mask = 0xFU;
1580
1581 if ((pkcs & BIT(31)) != 0U) {
1582 mask <<= 4;
1583 value <<= 4;
1584 }
1585
1586 mmio_clrsetbits_32(address, mask, value);
1587 }
1588
stm32mp1_clk_init(void)1589 int stm32mp1_clk_init(void)
1590 {
1591 uintptr_t rcc_base = stm32mp_rcc_base();
1592 unsigned int clksrc[CLKSRC_NB];
1593 unsigned int clkdiv[CLKDIV_NB];
1594 unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1595 int plloff[_PLL_NB];
1596 int ret, len;
1597 enum stm32mp1_pll_id i;
1598 bool lse_css = false;
1599 bool pll3_preserve = false;
1600 bool pll4_preserve = false;
1601 bool pll4_bootrom = false;
1602 const fdt32_t *pkcs_cell;
1603
1604 /* Check status field to disable security */
1605 if (!fdt_get_rcc_secure_status()) {
1606 mmio_write_32(rcc_base + RCC_TZCR, 0);
1607 }
1608
1609 ret = fdt_rcc_read_uint32_array("st,clksrc", clksrc,
1610 (uint32_t)CLKSRC_NB);
1611 if (ret < 0) {
1612 return -FDT_ERR_NOTFOUND;
1613 }
1614
1615 ret = fdt_rcc_read_uint32_array("st,clkdiv", clkdiv,
1616 (uint32_t)CLKDIV_NB);
1617 if (ret < 0) {
1618 return -FDT_ERR_NOTFOUND;
1619 }
1620
1621 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
1622 char name[12];
1623
1624 snprintf(name, sizeof(name), "st,pll@%d", i);
1625 plloff[i] = fdt_rcc_subnode_offset(name);
1626
1627 if (!fdt_check_node(plloff[i])) {
1628 continue;
1629 }
1630
1631 ret = fdt_read_uint32_array(plloff[i], "cfg",
1632 pllcfg[i], (int)PLLCFG_NB);
1633 if (ret < 0) {
1634 return -FDT_ERR_NOTFOUND;
1635 }
1636 }
1637
1638 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
1639 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
1640
1641 /*
1642 * Switch ON oscillator found in device-tree.
1643 * Note: HSI already ON after BootROM stage.
1644 */
1645 if (stm32mp1_osc[_LSI] != 0U) {
1646 stm32mp1_lsi_set(true);
1647 }
1648 if (stm32mp1_osc[_LSE] != 0U) {
1649 bool bypass, digbyp;
1650 uint32_t lsedrv;
1651
1652 bypass = fdt_osc_read_bool(_LSE, "st,bypass");
1653 digbyp = fdt_osc_read_bool(_LSE, "st,digbypass");
1654 lse_css = fdt_osc_read_bool(_LSE, "st,css");
1655 lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive",
1656 LSEDRV_MEDIUM_HIGH);
1657 stm32mp1_lse_enable(bypass, digbyp, lsedrv);
1658 }
1659 if (stm32mp1_osc[_HSE] != 0U) {
1660 bool bypass, digbyp, css;
1661
1662 bypass = fdt_osc_read_bool(_HSE, "st,bypass");
1663 digbyp = fdt_osc_read_bool(_HSE, "st,digbypass");
1664 css = fdt_osc_read_bool(_HSE, "st,css");
1665 stm32mp1_hse_enable(bypass, digbyp, css);
1666 }
1667 /*
1668 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
1669 * => switch on CSI even if node is not present in device tree
1670 */
1671 stm32mp1_csi_set(true);
1672
1673 /* Come back to HSI */
1674 ret = stm32mp1_set_clksrc(CLK_MPU_HSI);
1675 if (ret != 0) {
1676 return ret;
1677 }
1678 ret = stm32mp1_set_clksrc(CLK_AXI_HSI);
1679 if (ret != 0) {
1680 return ret;
1681 }
1682 ret = stm32mp1_set_clksrc(CLK_MCU_HSI);
1683 if (ret != 0) {
1684 return ret;
1685 }
1686
1687 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) &
1688 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) {
1689 pll3_preserve = stm32mp1_check_pll_conf(_PLL3,
1690 clksrc[CLKSRC_PLL3],
1691 pllcfg[_PLL3],
1692 plloff[_PLL3]);
1693 pll4_preserve = stm32mp1_check_pll_conf(_PLL4,
1694 clksrc[CLKSRC_PLL4],
1695 pllcfg[_PLL4],
1696 plloff[_PLL4]);
1697 }
1698
1699 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
1700 if (((i == _PLL3) && pll3_preserve) ||
1701 ((i == _PLL4) && pll4_preserve)) {
1702 continue;
1703 }
1704
1705 ret = stm32mp1_pll_stop(i);
1706 if (ret != 0) {
1707 return ret;
1708 }
1709 }
1710
1711 /* Configure HSIDIV */
1712 if (stm32mp1_osc[_HSI] != 0U) {
1713 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]);
1714 if (ret != 0) {
1715 return ret;
1716 }
1717 stm32mp1_stgen_config();
1718 }
1719
1720 /* Select DIV */
1721 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
1722 mmio_write_32(rcc_base + RCC_MPCKDIVR,
1723 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK);
1724 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR);
1725 if (ret != 0) {
1726 return ret;
1727 }
1728 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR);
1729 if (ret != 0) {
1730 return ret;
1731 }
1732 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR);
1733 if (ret != 0) {
1734 return ret;
1735 }
1736 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR);
1737 if (ret != 0) {
1738 return ret;
1739 }
1740 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR);
1741 if (ret != 0) {
1742 return ret;
1743 }
1744 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR);
1745 if (ret != 0) {
1746 return ret;
1747 }
1748 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR);
1749 if (ret != 0) {
1750 return ret;
1751 }
1752
1753 /* No ready bit for RTC */
1754 mmio_write_32(rcc_base + RCC_RTCDIVR,
1755 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK);
1756
1757 /* Configure PLLs source */
1758 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]);
1759 if (ret != 0) {
1760 return ret;
1761 }
1762
1763 if (!pll3_preserve) {
1764 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]);
1765 if (ret != 0) {
1766 return ret;
1767 }
1768 }
1769
1770 if (!pll4_preserve) {
1771 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]);
1772 if (ret != 0) {
1773 return ret;
1774 }
1775 }
1776
1777 /* Configure and start PLLs */
1778 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
1779 uint32_t fracv;
1780 uint32_t csg[PLLCSG_NB];
1781
1782 if (((i == _PLL3) && pll3_preserve) ||
1783 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) {
1784 continue;
1785 }
1786
1787 if (!fdt_check_node(plloff[i])) {
1788 continue;
1789 }
1790
1791 if ((i == _PLL4) && pll4_bootrom) {
1792 /* Set output divider if not done by the Bootrom */
1793 stm32mp1_pll_config_output(i, pllcfg[i]);
1794 continue;
1795 }
1796
1797 fracv = fdt_read_uint32_default(plloff[i], "frac", 0);
1798
1799 ret = stm32mp1_pll_config(i, pllcfg[i], fracv);
1800 if (ret != 0) {
1801 return ret;
1802 }
1803 ret = fdt_read_uint32_array(plloff[i], "csg", csg,
1804 (uint32_t)PLLCSG_NB);
1805 if (ret == 0) {
1806 stm32mp1_pll_csg(i, csg);
1807 } else if (ret != -FDT_ERR_NOTFOUND) {
1808 return ret;
1809 }
1810
1811 stm32mp1_pll_start(i);
1812 }
1813 /* Wait and start PLLs ouptut when ready */
1814 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
1815 if (!fdt_check_node(plloff[i])) {
1816 continue;
1817 }
1818
1819 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]);
1820 if (ret != 0) {
1821 return ret;
1822 }
1823 }
1824 /* Wait LSE ready before to use it */
1825 if (stm32mp1_osc[_LSE] != 0U) {
1826 stm32mp1_lse_wait();
1827 }
1828
1829 /* Configure with expected clock source */
1830 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]);
1831 if (ret != 0) {
1832 return ret;
1833 }
1834 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]);
1835 if (ret != 0) {
1836 return ret;
1837 }
1838 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]);
1839 if (ret != 0) {
1840 return ret;
1841 }
1842 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css);
1843
1844 /* Configure PKCK */
1845 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len);
1846 if (pkcs_cell != NULL) {
1847 bool ckper_disabled = false;
1848 uint32_t j;
1849
1850 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) {
1851 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]);
1852
1853 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) {
1854 ckper_disabled = true;
1855 continue;
1856 }
1857 stm32mp1_pkcs_config(pkcs);
1858 }
1859
1860 /*
1861 * CKPER is source for some peripheral clocks
1862 * (FMC-NAND / QPSI-NOR) and switching source is allowed
1863 * only if previous clock is still ON
1864 * => deactivated CKPER only after switching clock
1865 */
1866 if (ckper_disabled) {
1867 stm32mp1_pkcs_config(CLK_CKPER_DISABLED);
1868 }
1869 }
1870
1871 /* Switch OFF HSI if not found in device-tree */
1872 if (stm32mp1_osc[_HSI] == 0U) {
1873 stm32mp1_hsi_set(false);
1874 }
1875 stm32mp1_stgen_config();
1876
1877 /* Software Self-Refresh mode (SSR) during DDR initilialization */
1878 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR,
1879 RCC_DDRITFCR_DDRCKMOD_MASK,
1880 RCC_DDRITFCR_DDRCKMOD_SSR <<
1881 RCC_DDRITFCR_DDRCKMOD_SHIFT);
1882
1883 return 0;
1884 }
1885
stm32mp1_osc_clk_init(const char * name,enum stm32mp_osc_id index)1886 static void stm32mp1_osc_clk_init(const char *name,
1887 enum stm32mp_osc_id index)
1888 {
1889 uint32_t frequency;
1890
1891 if (fdt_osc_read_freq(name, &frequency) == 0) {
1892 stm32mp1_osc[index] = frequency;
1893 }
1894 }
1895
stm32mp1_osc_init(void)1896 static void stm32mp1_osc_init(void)
1897 {
1898 enum stm32mp_osc_id i;
1899
1900 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) {
1901 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i);
1902 }
1903 }
1904
sync_earlyboot_clocks_state(void)1905 static void sync_earlyboot_clocks_state(void)
1906 {
1907 if (!stm32mp_is_single_core()) {
1908 stm32mp1_clk_enable_secure(RTCAPB);
1909 }
1910 }
1911
stm32mp1_clk_probe(void)1912 int stm32mp1_clk_probe(void)
1913 {
1914 stm32mp1_osc_init();
1915
1916 sync_earlyboot_clocks_state();
1917
1918 return 0;
1919 }
1920