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Searched defs:sunxi_ccm_reg (Results 1 – 5 of 5) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-sunxi/
Dclock_sun50i_h6.h12 struct sunxi_ccm_reg { struct
13 u32 pll1_cfg; /* 0x000 pll1 (cpux) control */
14 u8 reserved_0x004[12];
15 u32 pll5_cfg; /* 0x010 pll5 (ddr) control */
16 u8 reserved_0x014[12];
17 u32 pll6_cfg; /* 0x020 pll6 (periph0) control */
18 u8 reserved_0x020[4];
19 u32 pll_periph1_cfg; /* 0x028 pll periph1 control */
20 u8 reserved_0x028[4];
21 u32 pll7_cfg; /* 0x030 pll7 (gpu) control */
[all …]
Dclock_sun8i_a83t.h16 struct sunxi_ccm_reg { struct
17 u32 pll1_c0_cfg; /* 0x00 c1cpu# pll control */
18 u32 pll1_c1_cfg; /* 0x04 c1cpu# pll control */
19 u32 pll2_cfg; /* 0x08 pll2 audio control */
20 u32 reserved1;
21 u32 pll3_cfg; /* 0x10 pll3 video0 control */
22 u32 reserved2;
23 u32 pll4_cfg; /* 0x18 pll4 ve control */
24 u32 reserved3;
25 u32 pll5_cfg; /* 0x20 pll5 ddr control */
[all …]
Dclock_sun9i.h11 struct sunxi_ccm_reg { struct
12 u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */
13 u32 pll2_c1_cfg; /* 0x04 c1cpu# pll configuration */
14 u32 pll3_audio_cfg; /* 0x08 audio pll configuration */
15 u32 pll4_periph0_cfg; /* 0x0c peripheral0 pll configuration */
16 u32 pll5_ve_cfg; /* 0x10 videoengine pll configuration */
17 u32 pll6_ddr_cfg; /* 0x14 ddr pll configuration */
18 u32 pll7_video0_cfg; /* 0x18 video0 pll configuration */
19 u32 pll8_video1_cfg; /* 0x1c video1 pll configuration */
20 u32 pll9_gpu_cfg; /* 0x20 gpu pll configuration */
[all …]
Dclock_sun6i.h13 struct sunxi_ccm_reg { struct
14 u32 pll1_cfg; /* 0x00 pll1 control */
15 u32 reserved0;
16 u32 pll2_cfg; /* 0x08 pll2 control */
17 u32 reserved1;
18 u32 pll3_cfg; /* 0x10 pll3 control */
19 u32 reserved2;
20 u32 pll4_cfg; /* 0x18 pll4 control */
21 u32 reserved3;
22 u32 pll5_cfg; /* 0x20 pll5 control */
[all …]
Dclock_sun4i.h13 struct sunxi_ccm_reg { struct
14 u32 pll1_cfg; /* 0x00 pll1 control */
15 u32 pll1_tun; /* 0x04 pll1 tuning */
16 u32 pll2_cfg; /* 0x08 pll2 control */
17 u32 pll2_tun; /* 0x0c pll2 tuning */
18 u32 pll3_cfg; /* 0x10 pll3 control */
19 u8 res0[0x4];
20 u32 pll4_cfg; /* 0x18 pll4 control */
21 u8 res1[0x4];
22 u32 pll5_cfg; /* 0x20 pll5 control */
[all …]