1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4 */
5
6 #include <config.h>
7 #include <common.h>
8 #include <cpu_func.h>
9 #include <linux/compiler.h>
10 #include <linux/kernel.h>
11 #include <linux/log2.h>
12 #include <asm/arcregs.h>
13 #include <asm/arc-bcr.h>
14 #include <asm/cache.h>
15
16 /*
17 * [ NOTE 1 ]:
18 * Data cache (L1 D$ or SL$) entire invalidate operation or data cache disable
19 * operation may result in unexpected behavior and data loss even if we flush
20 * data cache right before invalidation. That may happens if we store any context
21 * on stack (like we store BLINK register on stack before function call).
22 * BLINK register is the register where return address is automatically saved
23 * when we do function call with instructions like 'bl'.
24 *
25 * There is the real example:
26 * We may hang in the next code as we store any BLINK register on stack in
27 * invalidate_dcache_all() function.
28 *
29 * void flush_dcache_all() {
30 * __dc_entire_op(OP_FLUSH);
31 * // Other code //
32 * }
33 *
34 * void invalidate_dcache_all() {
35 * __dc_entire_op(OP_INV);
36 * // Other code //
37 * }
38 *
39 * void foo(void) {
40 * flush_dcache_all();
41 * invalidate_dcache_all();
42 * }
43 *
44 * Now let's see what really happens during that code execution:
45 *
46 * foo()
47 * |->> call flush_dcache_all
48 * [return address is saved to BLINK register]
49 * [push BLINK] (save to stack) ![point 1]
50 * |->> call __dc_entire_op(OP_FLUSH)
51 * [return address is saved to BLINK register]
52 * [flush L1 D$]
53 * return [jump to BLINK]
54 * <<------
55 * [other flush_dcache_all code]
56 * [pop BLINK] (get from stack)
57 * return [jump to BLINK]
58 * <<------
59 * |->> call invalidate_dcache_all
60 * [return address is saved to BLINK register]
61 * [push BLINK] (save to stack) ![point 2]
62 * |->> call __dc_entire_op(OP_FLUSH)
63 * [return address is saved to BLINK register]
64 * [invalidate L1 D$] ![point 3]
65 * // Oops!!!
66 * // We lose return address from invalidate_dcache_all function:
67 * // we save it to stack and invalidate L1 D$ after that!
68 * return [jump to BLINK]
69 * <<------
70 * [other invalidate_dcache_all code]
71 * [pop BLINK] (get from stack)
72 * // we don't have this data in L1 dcache as we invalidated it in [point 3]
73 * // so we get it from next memory level (for example DDR memory)
74 * // but in the memory we have value which we save in [point 1], which
75 * // is return address from flush_dcache_all function (instead of
76 * // address from current invalidate_dcache_all function which we
77 * // saved in [point 2] !)
78 * return [jump to BLINK]
79 * <<------
80 * // As BLINK points to invalidate_dcache_all, we call it again and
81 * // loop forever.
82 *
83 * Fortunately we may fix that by using flush & invalidation of D$ with a single
84 * one instruction (instead of flush and invalidation instructions pair) and
85 * enabling force function inline with '__attribute__((always_inline))' gcc
86 * attribute to avoid any function call (and BLINK store) between cache flush
87 * and disable.
88 *
89 *
90 * [ NOTE 2 ]:
91 * As of today we only support the following cache configurations on ARC.
92 * Other configurations may exist in HW (for example, since version 3.0 HS
93 * supports SL$ (L2 system level cache) disable) but we don't support it in SW.
94 * Configuration 1:
95 * ______________________
96 * | |
97 * | ARC CPU |
98 * |______________________|
99 * ___|___ ___|___
100 * | | | |
101 * | L1 I$ | | L1 D$ |
102 * |_______| |_______|
103 * on/off on/off
104 * ___|______________|____
105 * | |
106 * | main memory |
107 * |______________________|
108 *
109 * Configuration 2:
110 * ______________________
111 * | |
112 * | ARC CPU |
113 * |______________________|
114 * ___|___ ___|___
115 * | | | |
116 * | L1 I$ | | L1 D$ |
117 * |_______| |_______|
118 * on/off on/off
119 * ___|______________|____
120 * | |
121 * | L2 (SL$) |
122 * |______________________|
123 * always must be on
124 * ___|______________|____
125 * | |
126 * | main memory |
127 * |______________________|
128 *
129 * Configuration 3:
130 * ______________________
131 * | |
132 * | ARC CPU |
133 * |______________________|
134 * ___|___ ___|___
135 * | | | |
136 * | L1 I$ | | L1 D$ |
137 * |_______| |_______|
138 * on/off must be on
139 * ___|______________|____ _______
140 * | | | |
141 * | L2 (SL$) |-----| IOC |
142 * |______________________| |_______|
143 * always must be on on/off
144 * ___|______________|____
145 * | |
146 * | main memory |
147 * |______________________|
148 */
149
150 DECLARE_GLOBAL_DATA_PTR;
151
152 /* Bit values in IC_CTRL */
153 #define IC_CTRL_CACHE_DISABLE BIT(0)
154
155 /* Bit values in DC_CTRL */
156 #define DC_CTRL_CACHE_DISABLE BIT(0)
157 #define DC_CTRL_INV_MODE_FLUSH BIT(6)
158 #define DC_CTRL_FLUSH_STATUS BIT(8)
159
160 #define OP_INV BIT(0)
161 #define OP_FLUSH BIT(1)
162 #define OP_FLUSH_N_INV (OP_FLUSH | OP_INV)
163
164 /* Bit val in SLC_CONTROL */
165 #define SLC_CTRL_DIS 0x001
166 #define SLC_CTRL_IM 0x040
167 #define SLC_CTRL_BUSY 0x100
168 #define SLC_CTRL_RGN_OP_INV 0x200
169
170 #define CACHE_LINE_MASK (~(gd->arch.l1_line_sz - 1))
171
172 /*
173 * We don't want to use '__always_inline' macro here as it can be redefined
174 * to simple 'inline' in some cases which breaks stuff. See [ NOTE 1 ] for more
175 * details about the reasons we need to use always_inline functions.
176 */
177 #define inlined_cachefunc inline __attribute__((always_inline))
178
179 static inlined_cachefunc void __ic_entire_invalidate(void);
180 static inlined_cachefunc void __dc_entire_op(const int cacheop);
181
pae_exists(void)182 static inline bool pae_exists(void)
183 {
184 /* TODO: should we compare mmu version from BCR and from CONFIG? */
185 #if (CONFIG_ARC_MMU_VER >= 4)
186 union bcr_mmu_4 mmu4;
187
188 mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR);
189
190 if (mmu4.fields.pae)
191 return true;
192 #endif /* (CONFIG_ARC_MMU_VER >= 4) */
193
194 return false;
195 }
196
icache_exists(void)197 static inlined_cachefunc bool icache_exists(void)
198 {
199 union bcr_di_cache ibcr;
200
201 ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
202 return !!ibcr.fields.ver;
203 }
204
icache_enabled(void)205 static inlined_cachefunc bool icache_enabled(void)
206 {
207 if (!icache_exists())
208 return false;
209
210 return !(read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE);
211 }
212
dcache_exists(void)213 static inlined_cachefunc bool dcache_exists(void)
214 {
215 union bcr_di_cache dbcr;
216
217 dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
218 return !!dbcr.fields.ver;
219 }
220
dcache_enabled(void)221 static inlined_cachefunc bool dcache_enabled(void)
222 {
223 if (!dcache_exists())
224 return false;
225
226 return !(read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE);
227 }
228
slc_exists(void)229 static inlined_cachefunc bool slc_exists(void)
230 {
231 if (is_isa_arcv2()) {
232 union bcr_generic sbcr;
233
234 sbcr.word = read_aux_reg(ARC_BCR_SLC);
235 return !!sbcr.fields.ver;
236 }
237
238 return false;
239 }
240
slc_data_bypass(void)241 static inlined_cachefunc bool slc_data_bypass(void)
242 {
243 /*
244 * If L1 data cache is disabled SL$ is bypassed and all load/store
245 * requests are sent directly to main memory.
246 */
247 return !dcache_enabled();
248 }
249
ioc_exists(void)250 static inline bool ioc_exists(void)
251 {
252 if (is_isa_arcv2()) {
253 union bcr_clust_cfg cbcr;
254
255 cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
256 return cbcr.fields.c;
257 }
258
259 return false;
260 }
261
ioc_enabled(void)262 static inline bool ioc_enabled(void)
263 {
264 /*
265 * We check only CONFIG option instead of IOC HW state check as IOC
266 * must be disabled by default.
267 */
268 if (is_ioc_enabled())
269 return ioc_exists();
270
271 return false;
272 }
273
__slc_entire_op(const int op)274 static inlined_cachefunc void __slc_entire_op(const int op)
275 {
276 unsigned int ctrl;
277
278 if (!slc_exists())
279 return;
280
281 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
282
283 if (!(op & OP_FLUSH)) /* i.e. OP_INV */
284 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
285 else
286 ctrl |= SLC_CTRL_IM;
287
288 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
289
290 if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */
291 write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1);
292 else
293 write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1);
294
295 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
296 read_aux_reg(ARC_AUX_SLC_CTRL);
297
298 /* Important to wait for flush to complete */
299 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
300 }
301
slc_upper_region_init(void)302 static void slc_upper_region_init(void)
303 {
304 /*
305 * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist
306 * only if PAE exists in current HW. So we had to check pae_exist
307 * before using them.
308 */
309 if (!pae_exists())
310 return;
311
312 /*
313 * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0
314 * as we don't use PAE40.
315 */
316 write_aux_reg(ARC_AUX_SLC_RGN_END1, 0);
317 write_aux_reg(ARC_AUX_SLC_RGN_START1, 0);
318 }
319
__slc_rgn_op(unsigned long paddr,unsigned long sz,const int op)320 static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
321 {
322 #ifdef CONFIG_ISA_ARCV2
323
324 unsigned int ctrl;
325 unsigned long end;
326
327 if (!slc_exists())
328 return;
329
330 /*
331 * The Region Flush operation is specified by CTRL.RGN_OP[11..9]
332 * - b'000 (default) is Flush,
333 * - b'001 is Invalidate if CTRL.IM == 0
334 * - b'001 is Flush-n-Invalidate if CTRL.IM == 1
335 */
336 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
337
338 /* Don't rely on default value of IM bit */
339 if (!(op & OP_FLUSH)) /* i.e. OP_INV */
340 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
341 else
342 ctrl |= SLC_CTRL_IM;
343
344 if (op & OP_INV)
345 ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */
346 else
347 ctrl &= ~SLC_CTRL_RGN_OP_INV;
348
349 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
350
351 /*
352 * Lower bits are ignored, no need to clip
353 * END needs to be setup before START (latter triggers the operation)
354 * END can't be same as START, so add (l2_line_sz - 1) to sz
355 */
356 end = paddr + sz + gd->arch.slc_line_sz - 1;
357
358 /*
359 * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1)
360 * are always == 0 as we don't use PAE40, so we only setup lower ones
361 * (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START)
362 */
363 write_aux_reg(ARC_AUX_SLC_RGN_END, end);
364 write_aux_reg(ARC_AUX_SLC_RGN_START, paddr);
365
366 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
367 read_aux_reg(ARC_AUX_SLC_CTRL);
368
369 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
370
371 #endif /* CONFIG_ISA_ARCV2 */
372 }
373
arc_ioc_setup(void)374 static void arc_ioc_setup(void)
375 {
376 /* IOC Aperture start is equal to DDR start */
377 unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
378 /* IOC Aperture size is equal to DDR size */
379 long ap_size = CONFIG_SYS_SDRAM_SIZE;
380
381 /* Unsupported configuration. See [ NOTE 2 ] for more details. */
382 if (!slc_exists())
383 panic("Try to enable IOC but SLC is not present");
384
385 /* Unsupported configuration. See [ NOTE 2 ] for more details. */
386 if (!dcache_enabled())
387 panic("Try to enable IOC but L1 D$ is disabled");
388
389 if (!is_power_of_2(ap_size) || ap_size < 4096)
390 panic("IOC Aperture size must be power of 2 and bigger 4Kib");
391
392 /* IOC Aperture start must be aligned to the size of the aperture */
393 if (ap_base % ap_size != 0)
394 panic("IOC Aperture start must be aligned to the size of the aperture");
395
396 flush_n_invalidate_dcache_all();
397
398 /*
399 * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
400 * so setting 0x11 implies 512M, 0x12 implies 1G...
401 */
402 write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
403 order_base_2(ap_size / 1024) - 2);
404
405 write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
406 write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
407 write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
408 }
409
read_decode_cache_bcr_arcv2(void)410 static void read_decode_cache_bcr_arcv2(void)
411 {
412 #ifdef CONFIG_ISA_ARCV2
413
414 union bcr_slc_cfg slc_cfg;
415
416 if (slc_exists()) {
417 slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
418 gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
419
420 /*
421 * We don't support configuration where L1 I$ or L1 D$ is
422 * absent but SL$ exists. See [ NOTE 2 ] for more details.
423 */
424 if (!icache_exists() || !dcache_exists())
425 panic("Unsupported cache configuration: SLC exists but one of L1 caches is absent");
426 }
427
428 #endif /* CONFIG_ISA_ARCV2 */
429 }
430
read_decode_cache_bcr(void)431 void read_decode_cache_bcr(void)
432 {
433 int dc_line_sz = 0, ic_line_sz = 0;
434 union bcr_di_cache ibcr, dbcr;
435
436 /*
437 * We don't care much about I$ line length really as there're
438 * no per-line ops on I$ instead we only do full invalidation of it
439 * on occasion of relocation and right before jumping to the OS.
440 * Still we check insane config with zero-encoded line length in
441 * presense of version field in I$ BCR. Just in case.
442 */
443 ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
444 if (ibcr.fields.ver) {
445 ic_line_sz = 8 << ibcr.fields.line_len;
446 if (!ic_line_sz)
447 panic("Instruction exists but line length is 0\n");
448 }
449
450 dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
451 if (dbcr.fields.ver) {
452 gd->arch.l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
453 if (!dc_line_sz)
454 panic("Data cache exists but line length is 0\n");
455 }
456 }
457
cache_init(void)458 void cache_init(void)
459 {
460 read_decode_cache_bcr();
461
462 if (is_isa_arcv2())
463 read_decode_cache_bcr_arcv2();
464
465 if (is_isa_arcv2() && ioc_enabled())
466 arc_ioc_setup();
467
468 if (is_isa_arcv2() && slc_exists())
469 slc_upper_region_init();
470 }
471
icache_status(void)472 int icache_status(void)
473 {
474 return icache_enabled();
475 }
476
icache_enable(void)477 void icache_enable(void)
478 {
479 if (icache_exists())
480 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
481 ~IC_CTRL_CACHE_DISABLE);
482 }
483
icache_disable(void)484 void icache_disable(void)
485 {
486 if (!icache_exists())
487 return;
488
489 __ic_entire_invalidate();
490
491 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
492 IC_CTRL_CACHE_DISABLE);
493 }
494
495 /* IC supports only invalidation */
__ic_entire_invalidate(void)496 static inlined_cachefunc void __ic_entire_invalidate(void)
497 {
498 if (!icache_enabled())
499 return;
500
501 /* Any write to IC_IVIC register triggers invalidation of entire I$ */
502 write_aux_reg(ARC_AUX_IC_IVIC, 1);
503 /*
504 * As per ARC HS databook (see chapter 5.3.3.2)
505 * it is required to add 3 NOPs after each write to IC_IVIC.
506 */
507 __builtin_arc_nop();
508 __builtin_arc_nop();
509 __builtin_arc_nop();
510 read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
511 }
512
invalidate_icache_all(void)513 void invalidate_icache_all(void)
514 {
515 __ic_entire_invalidate();
516
517 /*
518 * If SL$ is bypassed for data it is used only for instructions,
519 * so we need to invalidate it too.
520 * TODO: HS 3.0 supports SLC disable so we need to check slc
521 * enable/disable status here.
522 */
523 if (is_isa_arcv2() && slc_data_bypass())
524 __slc_entire_op(OP_INV);
525 }
526
dcache_status(void)527 int dcache_status(void)
528 {
529 return dcache_enabled();
530 }
531
dcache_enable(void)532 void dcache_enable(void)
533 {
534 if (!dcache_exists())
535 return;
536
537 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
538 ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
539 }
540
dcache_disable(void)541 void dcache_disable(void)
542 {
543 if (!dcache_exists())
544 return;
545
546 __dc_entire_op(OP_FLUSH_N_INV);
547
548 /*
549 * As SLC will be bypassed for data after L1 D$ disable we need to
550 * flush it first before L1 D$ disable. Also we invalidate SLC to
551 * avoid any inconsistent data problems after enabling L1 D$ again with
552 * dcache_enable function.
553 */
554 if (is_isa_arcv2())
555 __slc_entire_op(OP_FLUSH_N_INV);
556
557 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
558 DC_CTRL_CACHE_DISABLE);
559 }
560
561 /* Common Helper for Line Operations on D-cache */
__dcache_line_loop(unsigned long paddr,unsigned long sz,const int cacheop)562 static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz,
563 const int cacheop)
564 {
565 unsigned int aux_cmd;
566 int num_lines;
567
568 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
569 aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
570
571 sz += paddr & ~CACHE_LINE_MASK;
572 paddr &= CACHE_LINE_MASK;
573
574 num_lines = DIV_ROUND_UP(sz, gd->arch.l1_line_sz);
575
576 while (num_lines-- > 0) {
577 #if (CONFIG_ARC_MMU_VER == 3)
578 write_aux_reg(ARC_AUX_DC_PTAG, paddr);
579 #endif
580 write_aux_reg(aux_cmd, paddr);
581 paddr += gd->arch.l1_line_sz;
582 }
583 }
584
__before_dc_op(const int op)585 static inlined_cachefunc void __before_dc_op(const int op)
586 {
587 unsigned int ctrl;
588
589 ctrl = read_aux_reg(ARC_AUX_DC_CTRL);
590
591 /* IM bit implies flush-n-inv, instead of vanilla inv */
592 if (op == OP_INV)
593 ctrl &= ~DC_CTRL_INV_MODE_FLUSH;
594 else
595 ctrl |= DC_CTRL_INV_MODE_FLUSH;
596
597 write_aux_reg(ARC_AUX_DC_CTRL, ctrl);
598 }
599
__after_dc_op(const int op)600 static inlined_cachefunc void __after_dc_op(const int op)
601 {
602 if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
603 while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
604 }
605
__dc_entire_op(const int cacheop)606 static inlined_cachefunc void __dc_entire_op(const int cacheop)
607 {
608 int aux;
609
610 if (!dcache_enabled())
611 return;
612
613 __before_dc_op(cacheop);
614
615 if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
616 aux = ARC_AUX_DC_IVDC;
617 else
618 aux = ARC_AUX_DC_FLSH;
619
620 write_aux_reg(aux, 0x1);
621
622 __after_dc_op(cacheop);
623 }
624
__dc_line_op(unsigned long paddr,unsigned long sz,const int cacheop)625 static inline void __dc_line_op(unsigned long paddr, unsigned long sz,
626 const int cacheop)
627 {
628 if (!dcache_enabled())
629 return;
630
631 __before_dc_op(cacheop);
632 __dcache_line_loop(paddr, sz, cacheop);
633 __after_dc_op(cacheop);
634 }
635
invalidate_dcache_range(unsigned long start,unsigned long end)636 void invalidate_dcache_range(unsigned long start, unsigned long end)
637 {
638 if (start >= end)
639 return;
640
641 /*
642 * ARCv1 -> call __dc_line_op
643 * ARCv2 && L1 D$ disabled -> nothing
644 * ARCv2 && L1 D$ enabled && IOC enabled -> nothing
645 * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op
646 */
647 if (!is_isa_arcv2() || !ioc_enabled())
648 __dc_line_op(start, end - start, OP_INV);
649
650 if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass())
651 __slc_rgn_op(start, end - start, OP_INV);
652 }
653
flush_dcache_range(unsigned long start,unsigned long end)654 void flush_dcache_range(unsigned long start, unsigned long end)
655 {
656 if (start >= end)
657 return;
658
659 /*
660 * ARCv1 -> call __dc_line_op
661 * ARCv2 && L1 D$ disabled -> nothing
662 * ARCv2 && L1 D$ enabled && IOC enabled -> nothing
663 * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op
664 */
665 if (!is_isa_arcv2() || !ioc_enabled())
666 __dc_line_op(start, end - start, OP_FLUSH);
667
668 if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass())
669 __slc_rgn_op(start, end - start, OP_FLUSH);
670 }
671
flush_cache(unsigned long start,unsigned long size)672 void flush_cache(unsigned long start, unsigned long size)
673 {
674 flush_dcache_range(start, start + size);
675 }
676
677 /*
678 * As invalidate_dcache_all() is not used in generic U-Boot code and as we
679 * don't need it in arch/arc code alone (invalidate without flush) we implement
680 * flush_n_invalidate_dcache_all (flush and invalidate in 1 operation) because
681 * it's much safer. See [ NOTE 1 ] for more details.
682 */
flush_n_invalidate_dcache_all(void)683 void flush_n_invalidate_dcache_all(void)
684 {
685 __dc_entire_op(OP_FLUSH_N_INV);
686
687 if (is_isa_arcv2() && !slc_data_bypass())
688 __slc_entire_op(OP_FLUSH_N_INV);
689 }
690
flush_dcache_all(void)691 void flush_dcache_all(void)
692 {
693 __dc_entire_op(OP_FLUSH);
694
695 if (is_isa_arcv2() && !slc_data_bypass())
696 __slc_entire_op(OP_FLUSH);
697 }
698
699 /*
700 * This is function to cleanup all caches (and therefore sync I/D caches) which
701 * can be used for cleanup before linux launch or to sync caches during
702 * relocation.
703 */
sync_n_cleanup_cache_all(void)704 void sync_n_cleanup_cache_all(void)
705 {
706 __dc_entire_op(OP_FLUSH_N_INV);
707
708 /*
709 * If SL$ is bypassed for data it is used only for instructions,
710 * and we shouldn't flush it. So invalidate it instead of flush_n_inv.
711 */
712 if (is_isa_arcv2()) {
713 if (slc_data_bypass())
714 __slc_entire_op(OP_INV);
715 else
716 __slc_entire_op(OP_FLUSH_N_INV);
717 }
718
719 __ic_entire_invalidate();
720 }
721