1 /*
2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <arch_helpers.h>
10 #include <bl31/interrupt_mgmt.h>
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <context.h>
14 #include <denver.h>
15 #include <lib/bakery_lock.h>
16 #include <lib/el3_runtime/context_mgmt.h>
17 #include <plat/common/platform.h>
18
19 #if ENABLE_WDT_LEGACY_FIQ_HANDLING
20 #include <flowctrl.h>
21 #endif
22 #include <tegra_def.h>
23 #include <tegra_private.h>
24
25 /* Legacy FIQ used by earlier Tegra platforms */
26 #define LEGACY_FIQ_PPI_WDT 28U
27
28 static DEFINE_BAKERY_LOCK(tegra_fiq_lock);
29
30 /*******************************************************************************
31 * Static variables
32 ******************************************************************************/
33 static uint64_t ns_fiq_handler_addr;
34 static uint32_t fiq_handler_active;
35 static pcpu_fiq_state_t fiq_state[PLATFORM_CORE_COUNT];
36
37 /*******************************************************************************
38 * Handler for FIQ interrupts
39 ******************************************************************************/
tegra_fiq_interrupt_handler(uint32_t id,uint32_t flags,void * handle,void * cookie)40 static uint64_t tegra_fiq_interrupt_handler(uint32_t id,
41 uint32_t flags,
42 void *handle,
43 void *cookie)
44 {
45 cpu_context_t *ctx = cm_get_context(NON_SECURE);
46 el3_state_t *el3state_ctx = get_el3state_ctx(ctx);
47 uint32_t cpu = plat_my_core_pos();
48 uint32_t irq;
49
50 (void)id;
51 (void)flags;
52 (void)handle;
53 (void)cookie;
54
55 /*
56 * Read the pending interrupt ID
57 */
58 irq = plat_ic_get_pending_interrupt_id();
59
60 bakery_lock_get(&tegra_fiq_lock);
61
62 /*
63 * Jump to NS world only if the NS world's FIQ handler has
64 * been registered
65 */
66 if (ns_fiq_handler_addr != 0U) {
67
68 /*
69 * The FIQ was generated when the execution was in the non-secure
70 * world. Save the context registers to start with.
71 */
72 cm_el1_sysregs_context_save(NON_SECURE);
73
74 /*
75 * Save elr_el3 and spsr_el3 from the saved context, and overwrite
76 * the context with the NS fiq_handler_addr and SPSR value.
77 */
78 fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3));
79 fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3));
80
81 /*
82 * Set the new ELR to continue execution in the NS world using the
83 * FIQ handler registered earlier.
84 */
85 cm_set_elr_el3(NON_SECURE, ns_fiq_handler_addr);
86 }
87
88 #if ENABLE_WDT_LEGACY_FIQ_HANDLING
89 /*
90 * Tegra platforms that use LEGACY_FIQ as the watchdog timer FIQ
91 * need to issue an IPI to other CPUs, to allow them to handle
92 * the "system hung" scenario. This interrupt is passed to the GICD
93 * via the Flow Controller. So, once we receive this interrupt,
94 * disable the routing so that we can mark it as "complete" in the
95 * GIC later.
96 */
97 if (irq == LEGACY_FIQ_PPI_WDT) {
98 tegra_fc_disable_fiq_to_ccplex_routing();
99 }
100 #endif
101
102 /*
103 * Mark this interrupt as complete to avoid a FIQ storm.
104 */
105 if (irq < 1022U) {
106 (void)plat_ic_acknowledge_interrupt();
107 plat_ic_end_of_interrupt(irq);
108 }
109
110 bakery_lock_release(&tegra_fiq_lock);
111
112 return 0;
113 }
114
115 /*******************************************************************************
116 * Setup handler for FIQ interrupts
117 ******************************************************************************/
tegra_fiq_handler_setup(void)118 void tegra_fiq_handler_setup(void)
119 {
120 uint32_t flags;
121 int32_t rc;
122
123 /* return if already registered */
124 if (fiq_handler_active == 0U) {
125 /*
126 * Register an interrupt handler for FIQ interrupts generated for
127 * NS interrupt sources
128 */
129 flags = 0U;
130 set_interrupt_rm_flag((flags), (NON_SECURE));
131 rc = register_interrupt_type_handler(INTR_TYPE_EL3,
132 tegra_fiq_interrupt_handler,
133 flags);
134 if (rc != 0) {
135 panic();
136 }
137
138 /* handler is now active */
139 fiq_handler_active = 1;
140 }
141 }
142
143 /*******************************************************************************
144 * Validate and store NS world's entrypoint for FIQ interrupts
145 ******************************************************************************/
tegra_fiq_set_ns_entrypoint(uint64_t entrypoint)146 void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint)
147 {
148 ns_fiq_handler_addr = entrypoint;
149 }
150
151 /*******************************************************************************
152 * Handler to return the NS EL1/EL0 CPU context
153 ******************************************************************************/
tegra_fiq_get_intr_context(void)154 int32_t tegra_fiq_get_intr_context(void)
155 {
156 cpu_context_t *ctx = cm_get_context(NON_SECURE);
157 gp_regs_t *gpregs_ctx = get_gpregs_ctx(ctx);
158 const el1_sys_regs_t *el1state_ctx = get_sysregs_ctx(ctx);
159 uint32_t cpu = plat_my_core_pos();
160 uint64_t val;
161
162 /*
163 * We store the ELR_EL3, SPSR_EL3, SP_EL0 and SP_EL1 registers so
164 * that el3_exit() sends these values back to the NS world.
165 */
166 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3));
167 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X1), (fiq_state[cpu].spsr_el3));
168
169 val = read_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_SP_EL0));
170 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X2), (val));
171
172 val = read_ctx_reg((el1state_ctx), (uint32_t)(CTX_SP_EL1));
173 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X3), (val));
174
175 return 0;
176 }
177