1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2017-2019 NXP
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
5 */
6
7 #include <common.h>
8 #include <cpu_func.h>
9 #include <env.h>
10 #include <fsl_ddr_sdram.h>
11 #include <vsprintf.h>
12 #include <asm/io.h>
13 #include <linux/errno.h>
14 #include <asm/system.h>
15 #include <fm_eth.h>
16 #include <asm/armv8/mmu.h>
17 #include <asm/io.h>
18 #include <asm/arch/fsl_serdes.h>
19 #include <asm/arch/soc.h>
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/speed.h>
22 #include <fsl_immap.h>
23 #include <asm/arch/mp.h>
24 #include <efi_loader.h>
25 #include <fsl-mc/fsl_mc.h>
26 #ifdef CONFIG_FSL_ESDHC
27 #include <fsl_esdhc.h>
28 #endif
29 #include <asm/armv8/sec_firmware.h>
30 #ifdef CONFIG_SYS_FSL_DDR
31 #include <fsl_ddr.h>
32 #endif
33 #include <asm/arch/clock.h>
34 #include <hwconfig.h>
35 #include <fsl_qbman.h>
36
37 #ifdef CONFIG_TFABOOT
38 #include <env_internal.h>
39 #ifdef CONFIG_CHAIN_OF_TRUST
40 #include <fsl_validate.h>
41 #endif
42 #endif
43 #include <linux/mii.h>
44
45 DECLARE_GLOBAL_DATA_PTR;
46
47 static struct cpu_type cpu_type_list[] = {
48 CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
49 CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
50 CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
51 CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
52 CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
53 CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
54 CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
55 CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
56 CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
57 CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
58 CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
59 CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
60 CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
61 CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
62 CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
63 CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
64 CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
65 CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
66 CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
67 CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
68 CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
69 CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
70 CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
71 CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
72 CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
73 CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
74 CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
75 CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
76 };
77
78 #define EARLY_PGTABLE_SIZE 0x5000
79 static struct mm_region early_map[] = {
80 #ifdef CONFIG_FSL_LSCH3
81 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
82 CONFIG_SYS_FSL_CCSR_SIZE,
83 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
84 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
85 },
86 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
87 SYS_FSL_OCRAM_SPACE_SIZE,
88 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
89 },
90 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
91 CONFIG_SYS_FSL_QSPI_SIZE1,
92 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
93 #ifdef CONFIG_FSL_IFC
94 /* For IFC Region #1, only the first 4MB is cache-enabled */
95 { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
96 CONFIG_SYS_FSL_IFC_SIZE1_1,
97 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
98 },
99 { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
100 CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
101 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
102 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
103 },
104 { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
105 CONFIG_SYS_FSL_IFC_SIZE1,
106 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
107 },
108 #endif
109 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
110 CONFIG_SYS_FSL_DRAM_SIZE1,
111 #if defined(CONFIG_TFABOOT) || \
112 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
113 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
114 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
115 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
116 #endif
117 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
118 },
119 #ifdef CONFIG_FSL_IFC
120 /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
121 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
122 CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
123 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
124 },
125 #endif
126 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
127 CONFIG_SYS_FSL_DCSR_SIZE,
128 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
129 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
130 },
131 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
132 CONFIG_SYS_FSL_DRAM_SIZE2,
133 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
134 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
135 },
136 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
137 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
138 CONFIG_SYS_FSL_DRAM_SIZE3,
139 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
140 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
141 },
142 #endif
143 #elif defined(CONFIG_FSL_LSCH2)
144 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
145 CONFIG_SYS_FSL_CCSR_SIZE,
146 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
147 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
148 },
149 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
150 SYS_FSL_OCRAM_SPACE_SIZE,
151 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
152 },
153 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
154 CONFIG_SYS_FSL_DCSR_SIZE,
155 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
156 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
157 },
158 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
159 CONFIG_SYS_FSL_QSPI_SIZE,
160 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
161 },
162 #ifdef CONFIG_FSL_IFC
163 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
164 CONFIG_SYS_FSL_IFC_SIZE,
165 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
166 },
167 #endif
168 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
169 CONFIG_SYS_FSL_DRAM_SIZE1,
170 #if defined(CONFIG_TFABOOT) || \
171 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
172 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
173 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
174 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
175 #endif
176 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
177 },
178 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
179 CONFIG_SYS_FSL_DRAM_SIZE2,
180 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
181 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
182 },
183 #endif
184 {}, /* list terminator */
185 };
186
187 static struct mm_region final_map[] = {
188 #ifdef CONFIG_FSL_LSCH3
189 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
190 CONFIG_SYS_FSL_CCSR_SIZE,
191 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
192 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
193 },
194 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
195 SYS_FSL_OCRAM_SPACE_SIZE,
196 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
197 },
198 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
199 CONFIG_SYS_FSL_DRAM_SIZE1,
200 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
201 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
202 },
203 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
204 CONFIG_SYS_FSL_QSPI_SIZE1,
205 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
206 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
207 },
208 { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
209 CONFIG_SYS_FSL_QSPI_SIZE2,
210 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
211 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
212 },
213 #ifdef CONFIG_FSL_IFC
214 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
215 CONFIG_SYS_FSL_IFC_SIZE2,
216 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
217 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
218 },
219 #endif
220 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
221 CONFIG_SYS_FSL_DCSR_SIZE,
222 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
223 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
224 },
225 { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
226 CONFIG_SYS_FSL_MC_SIZE,
227 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
228 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
229 },
230 { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
231 CONFIG_SYS_FSL_NI_SIZE,
232 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
233 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
234 },
235 /* For QBMAN portal, only the first 64MB is cache-enabled */
236 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
237 CONFIG_SYS_FSL_QBMAN_SIZE_1,
238 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
239 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
240 },
241 { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
242 CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
243 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
244 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
245 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
246 },
247 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
248 CONFIG_SYS_PCIE1_PHYS_SIZE,
249 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
250 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
251 },
252 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
253 CONFIG_SYS_PCIE2_PHYS_SIZE,
254 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
255 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
256 },
257 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
258 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
259 CONFIG_SYS_PCIE3_PHYS_SIZE,
260 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
261 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
262 },
263 #endif
264 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
265 { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
266 CONFIG_SYS_PCIE4_PHYS_SIZE,
267 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
268 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
269 },
270 #endif
271 #ifdef SYS_PCIE5_PHYS_ADDR
272 { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
273 SYS_PCIE5_PHYS_SIZE,
274 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
275 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
276 },
277 #endif
278 #ifdef SYS_PCIE6_PHYS_ADDR
279 { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
280 SYS_PCIE6_PHYS_SIZE,
281 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
282 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
283 },
284 #endif
285 { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
286 CONFIG_SYS_FSL_WRIOP1_SIZE,
287 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
288 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
289 },
290 { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
291 CONFIG_SYS_FSL_AIOP1_SIZE,
292 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
293 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
294 },
295 { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
296 CONFIG_SYS_FSL_PEBUF_SIZE,
297 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
298 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
299 },
300 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
301 CONFIG_SYS_FSL_DRAM_SIZE2,
302 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
303 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
304 },
305 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
306 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
307 CONFIG_SYS_FSL_DRAM_SIZE3,
308 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
309 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
310 },
311 #endif
312 #elif defined(CONFIG_FSL_LSCH2)
313 { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
314 CONFIG_SYS_FSL_BOOTROM_SIZE,
315 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
316 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
317 },
318 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
319 CONFIG_SYS_FSL_CCSR_SIZE,
320 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
321 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
322 },
323 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
324 SYS_FSL_OCRAM_SPACE_SIZE,
325 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
326 },
327 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
328 CONFIG_SYS_FSL_DCSR_SIZE,
329 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
330 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
331 },
332 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
333 CONFIG_SYS_FSL_QSPI_SIZE,
334 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
335 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
336 },
337 #ifdef CONFIG_FSL_IFC
338 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
339 CONFIG_SYS_FSL_IFC_SIZE,
340 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
341 },
342 #endif
343 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
344 CONFIG_SYS_FSL_DRAM_SIZE1,
345 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
346 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
347 },
348 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
349 CONFIG_SYS_FSL_QBMAN_SIZE,
350 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
351 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
352 },
353 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
354 CONFIG_SYS_FSL_DRAM_SIZE2,
355 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
356 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
357 },
358 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
359 CONFIG_SYS_PCIE1_PHYS_SIZE,
360 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
361 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
362 },
363 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
364 CONFIG_SYS_PCIE2_PHYS_SIZE,
365 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
366 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
367 },
368 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
369 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
370 CONFIG_SYS_PCIE3_PHYS_SIZE,
371 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
372 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
373 },
374 #endif
375 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
376 CONFIG_SYS_FSL_DRAM_SIZE3,
377 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
378 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
379 },
380 #endif
381 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
382 {}, /* space holder for secure mem */
383 #endif
384 {},
385 };
386
387 struct mm_region *mem_map = early_map;
388
cpu_name(char * name)389 void cpu_name(char *name)
390 {
391 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
392 unsigned int i, svr, ver;
393
394 svr = gur_in32(&gur->svr);
395 ver = SVR_SOC_VER(svr);
396
397 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
398 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
399 strcpy(name, cpu_type_list[i].name);
400 #ifdef CONFIG_ARCH_LX2160A
401 if (IS_C_PROCESSOR(svr))
402 strcat(name, "C");
403 #endif
404
405 if (IS_E_PROCESSOR(svr))
406 strcat(name, "E");
407
408 sprintf(name + strlen(name), " Rev%d.%d",
409 SVR_MAJ(svr), SVR_MIN(svr));
410 break;
411 }
412
413 if (i == ARRAY_SIZE(cpu_type_list))
414 strcpy(name, "unknown");
415 }
416
417 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
418 /*
419 * To start MMU before DDR is available, we create MMU table in SRAM.
420 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
421 * levels of translation tables here to cover 40-bit address space.
422 * We use 4KB granule size, with 40 bits physical address, T0SZ=24
423 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
424 * Note, the debug print in cache_v8.c is not usable for debugging
425 * these early MMU tables because UART is not yet available.
426 */
early_mmu_setup(void)427 static inline void early_mmu_setup(void)
428 {
429 unsigned int el = current_el();
430
431 /* global data is already setup, no allocation yet */
432 if (el == 3)
433 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
434 else
435 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
436 gd->arch.tlb_fillptr = gd->arch.tlb_addr;
437 gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
438
439 /* Create early page tables */
440 setup_pgtables();
441
442 /* point TTBR to the new table */
443 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
444 get_tcr(el, NULL, NULL) &
445 ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
446 MEMORY_ATTRIBUTES);
447
448 set_sctlr(get_sctlr() | CR_M);
449 }
450
fix_pcie_mmu_map(void)451 static void fix_pcie_mmu_map(void)
452 {
453 #ifdef CONFIG_ARCH_LS2080A
454 unsigned int i;
455 u32 svr, ver;
456 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
457
458 svr = gur_in32(&gur->svr);
459 ver = SVR_SOC_VER(svr);
460
461 /* Fix PCIE base and size for LS2088A */
462 if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
463 (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
464 (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
465 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
466 switch (final_map[i].phys) {
467 case CONFIG_SYS_PCIE1_PHYS_ADDR:
468 final_map[i].phys = 0x2000000000ULL;
469 final_map[i].virt = 0x2000000000ULL;
470 final_map[i].size = 0x800000000ULL;
471 break;
472 case CONFIG_SYS_PCIE2_PHYS_ADDR:
473 final_map[i].phys = 0x2800000000ULL;
474 final_map[i].virt = 0x2800000000ULL;
475 final_map[i].size = 0x800000000ULL;
476 break;
477 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
478 case CONFIG_SYS_PCIE3_PHYS_ADDR:
479 final_map[i].phys = 0x3000000000ULL;
480 final_map[i].virt = 0x3000000000ULL;
481 final_map[i].size = 0x800000000ULL;
482 break;
483 #endif
484 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
485 case CONFIG_SYS_PCIE4_PHYS_ADDR:
486 final_map[i].phys = 0x3800000000ULL;
487 final_map[i].virt = 0x3800000000ULL;
488 final_map[i].size = 0x800000000ULL;
489 break;
490 #endif
491 default:
492 break;
493 }
494 }
495 }
496 #endif
497 }
498
499 /*
500 * The final tables look similar to early tables, but different in detail.
501 * These tables are in DRAM. Sub tables are added to enable cache for
502 * QBMan and OCRAM.
503 *
504 * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
505 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
506 */
final_mmu_setup(void)507 static inline void final_mmu_setup(void)
508 {
509 u64 tlb_addr_save = gd->arch.tlb_addr;
510 unsigned int el = current_el();
511 int index;
512
513 /* fix the final_map before filling in the block entries */
514 fix_pcie_mmu_map();
515
516 mem_map = final_map;
517
518 /* Update mapping for DDR to actual size */
519 for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
520 /*
521 * Find the entry for DDR mapping and update the address and
522 * size. Zero-sized mapping will be skipped when creating MMU
523 * table.
524 */
525 switch (final_map[index].virt) {
526 case CONFIG_SYS_FSL_DRAM_BASE1:
527 final_map[index].virt = gd->bd->bi_dram[0].start;
528 final_map[index].phys = gd->bd->bi_dram[0].start;
529 final_map[index].size = gd->bd->bi_dram[0].size;
530 break;
531 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
532 case CONFIG_SYS_FSL_DRAM_BASE2:
533 #if (CONFIG_NR_DRAM_BANKS >= 2)
534 final_map[index].virt = gd->bd->bi_dram[1].start;
535 final_map[index].phys = gd->bd->bi_dram[1].start;
536 final_map[index].size = gd->bd->bi_dram[1].size;
537 #else
538 final_map[index].size = 0;
539 #endif
540 break;
541 #endif
542 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
543 case CONFIG_SYS_FSL_DRAM_BASE3:
544 #if (CONFIG_NR_DRAM_BANKS >= 3)
545 final_map[index].virt = gd->bd->bi_dram[2].start;
546 final_map[index].phys = gd->bd->bi_dram[2].start;
547 final_map[index].size = gd->bd->bi_dram[2].size;
548 #else
549 final_map[index].size = 0;
550 #endif
551 break;
552 #endif
553 default:
554 break;
555 }
556 }
557
558 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
559 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
560 if (el == 3) {
561 /*
562 * Only use gd->arch.secure_ram if the address is
563 * recalculated. Align to 4KB for MMU table.
564 */
565 /* put page tables in secure ram */
566 index = ARRAY_SIZE(final_map) - 2;
567 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
568 final_map[index].virt = gd->arch.secure_ram & ~0x3;
569 final_map[index].phys = final_map[index].virt;
570 final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
571 final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
572 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
573 tlb_addr_save = gd->arch.tlb_addr;
574 } else {
575 /* Use allocated (board_f.c) memory for TLB */
576 tlb_addr_save = gd->arch.tlb_allocated;
577 gd->arch.tlb_addr = tlb_addr_save;
578 }
579 }
580 #endif
581
582 /* Reset the fill ptr */
583 gd->arch.tlb_fillptr = tlb_addr_save;
584
585 /* Create normal system page tables */
586 setup_pgtables();
587
588 /* Create emergency page tables */
589 gd->arch.tlb_addr = gd->arch.tlb_fillptr;
590 gd->arch.tlb_emerg = gd->arch.tlb_addr;
591 setup_pgtables();
592 gd->arch.tlb_addr = tlb_addr_save;
593
594 /* Disable cache and MMU */
595 dcache_disable(); /* TLBs are invalidated */
596 invalidate_icache_all();
597
598 /* point TTBR to the new table */
599 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
600 MEMORY_ATTRIBUTES);
601
602 set_sctlr(get_sctlr() | CR_M);
603 }
604
get_page_table_size(void)605 u64 get_page_table_size(void)
606 {
607 return 0x10000;
608 }
609
arch_cpu_init(void)610 int arch_cpu_init(void)
611 {
612 /*
613 * This function is called before U-Boot relocates itself to speed up
614 * on system running. It is not necessary to run if performance is not
615 * critical. Skip if MMU is already enabled by SPL or other means.
616 */
617 if (get_sctlr() & CR_M)
618 return 0;
619
620 icache_enable();
621 __asm_invalidate_dcache_all();
622 __asm_invalidate_tlb_all();
623 early_mmu_setup();
624 set_sctlr(get_sctlr() | CR_C);
625 return 0;
626 }
627
mmu_setup(void)628 void mmu_setup(void)
629 {
630 final_mmu_setup();
631 }
632
633 /*
634 * This function is called from common/board_r.c.
635 * It recreates MMU table in main memory.
636 */
enable_caches(void)637 void enable_caches(void)
638 {
639 mmu_setup();
640 __asm_invalidate_tlb_all();
641 icache_enable();
642 dcache_enable();
643 }
644 #endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
645
646 #ifdef CONFIG_TFABOOT
__get_boot_src(u32 porsr1)647 enum boot_src __get_boot_src(u32 porsr1)
648 {
649 enum boot_src src = BOOT_SOURCE_RESERVED;
650 u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
651 #if !defined(CONFIG_NXP_LSCH3_2)
652 u32 val;
653 #endif
654 debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
655
656 #if defined(CONFIG_FSL_LSCH3)
657 #if defined(CONFIG_NXP_LSCH3_2)
658 switch (rcw_src) {
659 case RCW_SRC_SDHC1_VAL:
660 src = BOOT_SOURCE_SD_MMC;
661 break;
662 case RCW_SRC_SDHC2_VAL:
663 src = BOOT_SOURCE_SD_MMC2;
664 break;
665 case RCW_SRC_I2C1_VAL:
666 src = BOOT_SOURCE_I2C1_EXTENDED;
667 break;
668 case RCW_SRC_FLEXSPI_NAND2K_VAL:
669 src = BOOT_SOURCE_XSPI_NAND;
670 break;
671 case RCW_SRC_FLEXSPI_NAND4K_VAL:
672 src = BOOT_SOURCE_XSPI_NAND;
673 break;
674 case RCW_SRC_RESERVED_1_VAL:
675 src = BOOT_SOURCE_RESERVED;
676 break;
677 case RCW_SRC_FLEXSPI_NOR_24B:
678 src = BOOT_SOURCE_XSPI_NOR;
679 break;
680 default:
681 src = BOOT_SOURCE_RESERVED;
682 }
683 #else
684 val = rcw_src & RCW_SRC_TYPE_MASK;
685 if (val == RCW_SRC_NOR_VAL) {
686 val = rcw_src & NOR_TYPE_MASK;
687
688 switch (val) {
689 case NOR_16B_VAL:
690 case NOR_32B_VAL:
691 src = BOOT_SOURCE_IFC_NOR;
692 break;
693 default:
694 src = BOOT_SOURCE_RESERVED;
695 }
696 } else {
697 /* RCW SRC Serial Flash */
698 val = rcw_src & RCW_SRC_SERIAL_MASK;
699 switch (val) {
700 case RCW_SRC_QSPI_VAL:
701 /* RCW SRC Serial NOR (QSPI) */
702 src = BOOT_SOURCE_QSPI_NOR;
703 break;
704 case RCW_SRC_SD_CARD_VAL:
705 /* RCW SRC SD Card */
706 src = BOOT_SOURCE_SD_MMC;
707 break;
708 case RCW_SRC_EMMC_VAL:
709 /* RCW SRC EMMC */
710 src = BOOT_SOURCE_SD_MMC;
711 break;
712 case RCW_SRC_I2C1_VAL:
713 /* RCW SRC I2C1 Extended */
714 src = BOOT_SOURCE_I2C1_EXTENDED;
715 break;
716 default:
717 src = BOOT_SOURCE_RESERVED;
718 }
719 }
720 #endif
721 #elif defined(CONFIG_FSL_LSCH2)
722 /* RCW SRC NAND */
723 val = rcw_src & RCW_SRC_NAND_MASK;
724 if (val == RCW_SRC_NAND_VAL) {
725 val = rcw_src & NAND_RESERVED_MASK;
726 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
727 src = BOOT_SOURCE_IFC_NAND;
728
729 } else {
730 /* RCW SRC NOR */
731 val = rcw_src & RCW_SRC_NOR_MASK;
732 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
733 src = BOOT_SOURCE_IFC_NOR;
734 } else {
735 switch (rcw_src) {
736 case QSPI_VAL1:
737 case QSPI_VAL2:
738 src = BOOT_SOURCE_QSPI_NOR;
739 break;
740 case SD_VAL:
741 src = BOOT_SOURCE_SD_MMC;
742 break;
743 default:
744 src = BOOT_SOURCE_RESERVED;
745 }
746 }
747 }
748 #endif
749
750 if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
751 src = BOOT_SOURCE_QSPI_NOR;
752
753 debug("%s: src 0x%x\n", __func__, src);
754 return src;
755 }
756
get_boot_src(void)757 enum boot_src get_boot_src(void)
758 {
759 struct pt_regs regs;
760 u32 porsr1 = 0;
761
762 #if defined(CONFIG_FSL_LSCH3)
763 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
764 #elif defined(CONFIG_FSL_LSCH2)
765 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
766 #endif
767
768 if (current_el() == 2) {
769 regs.regs[0] = SIP_SVC_RCW;
770
771 smc_call(®s);
772 if (!regs.regs[0])
773 porsr1 = regs.regs[1];
774 }
775
776 if (current_el() == 3 || !porsr1) {
777 #ifdef CONFIG_FSL_LSCH3
778 porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
779 #elif defined(CONFIG_FSL_LSCH2)
780 porsr1 = in_be32(&gur->porsr1);
781 #endif
782 }
783
784 debug("%s: porsr1 0x%x\n", __func__, porsr1);
785
786 return __get_boot_src(porsr1);
787 }
788
789 #ifdef CONFIG_ENV_IS_IN_MMC
mmc_get_env_dev(void)790 int mmc_get_env_dev(void)
791 {
792 enum boot_src src = get_boot_src();
793 int dev = CONFIG_SYS_MMC_ENV_DEV;
794
795 switch (src) {
796 case BOOT_SOURCE_SD_MMC:
797 dev = 0;
798 break;
799 case BOOT_SOURCE_SD_MMC2:
800 dev = 1;
801 break;
802 default:
803 break;
804 }
805
806 return dev;
807 }
808 #endif
809
env_get_location(enum env_operation op,int prio)810 enum env_location env_get_location(enum env_operation op, int prio)
811 {
812 enum boot_src src = get_boot_src();
813 enum env_location env_loc = ENVL_NOWHERE;
814
815 if (prio)
816 return ENVL_UNKNOWN;
817
818 #ifdef CONFIG_ENV_IS_NOWHERE
819 return env_loc;
820 #endif
821
822 switch (src) {
823 case BOOT_SOURCE_IFC_NOR:
824 env_loc = ENVL_FLASH;
825 break;
826 case BOOT_SOURCE_QSPI_NOR:
827 /* FALLTHROUGH */
828 case BOOT_SOURCE_XSPI_NOR:
829 env_loc = ENVL_SPI_FLASH;
830 break;
831 case BOOT_SOURCE_IFC_NAND:
832 /* FALLTHROUGH */
833 case BOOT_SOURCE_QSPI_NAND:
834 /* FALLTHROUGH */
835 case BOOT_SOURCE_XSPI_NAND:
836 env_loc = ENVL_NAND;
837 break;
838 case BOOT_SOURCE_SD_MMC:
839 /* FALLTHROUGH */
840 case BOOT_SOURCE_SD_MMC2:
841 env_loc = ENVL_MMC;
842 break;
843 case BOOT_SOURCE_I2C1_EXTENDED:
844 /* FALLTHROUGH */
845 default:
846 break;
847 }
848
849 return env_loc;
850 }
851 #endif /* CONFIG_TFABOOT */
852
initiator_type(u32 cluster,int init_id)853 u32 initiator_type(u32 cluster, int init_id)
854 {
855 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
856 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
857 u32 type = 0;
858
859 type = gur_in32(&gur->tp_ityp[idx]);
860 if (type & TP_ITYP_AV)
861 return type;
862
863 return 0;
864 }
865
cpu_pos_mask(void)866 u32 cpu_pos_mask(void)
867 {
868 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
869 int i = 0;
870 u32 cluster, type, mask = 0;
871
872 do {
873 int j;
874
875 cluster = gur_in32(&gur->tp_cluster[i].lower);
876 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
877 type = initiator_type(cluster, j);
878 if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
879 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
880 }
881 i++;
882 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
883
884 return mask;
885 }
886
cpu_mask(void)887 u32 cpu_mask(void)
888 {
889 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
890 int i = 0, count = 0;
891 u32 cluster, type, mask = 0;
892
893 do {
894 int j;
895
896 cluster = gur_in32(&gur->tp_cluster[i].lower);
897 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
898 type = initiator_type(cluster, j);
899 if (type) {
900 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
901 mask |= 1 << count;
902 count++;
903 }
904 }
905 i++;
906 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
907
908 return mask;
909 }
910
911 /*
912 * Return the number of cores on this SOC.
913 */
cpu_numcores(void)914 int cpu_numcores(void)
915 {
916 return hweight32(cpu_mask());
917 }
918
fsl_qoriq_core_to_cluster(unsigned int core)919 int fsl_qoriq_core_to_cluster(unsigned int core)
920 {
921 struct ccsr_gur __iomem *gur =
922 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
923 int i = 0, count = 0;
924 u32 cluster;
925
926 do {
927 int j;
928
929 cluster = gur_in32(&gur->tp_cluster[i].lower);
930 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
931 if (initiator_type(cluster, j)) {
932 if (count == core)
933 return i;
934 count++;
935 }
936 }
937 i++;
938 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
939
940 return -1; /* cannot identify the cluster */
941 }
942
fsl_qoriq_core_to_type(unsigned int core)943 u32 fsl_qoriq_core_to_type(unsigned int core)
944 {
945 struct ccsr_gur __iomem *gur =
946 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
947 int i = 0, count = 0;
948 u32 cluster, type;
949
950 do {
951 int j;
952
953 cluster = gur_in32(&gur->tp_cluster[i].lower);
954 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
955 type = initiator_type(cluster, j);
956 if (type) {
957 if (count == core)
958 return type;
959 count++;
960 }
961 }
962 i++;
963 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
964
965 return -1; /* cannot identify the cluster */
966 }
967
968 #ifndef CONFIG_FSL_LSCH3
get_svr(void)969 uint get_svr(void)
970 {
971 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
972
973 return gur_in32(&gur->svr);
974 }
975 #endif
976
977 #ifdef CONFIG_DISPLAY_CPUINFO
print_cpuinfo(void)978 int print_cpuinfo(void)
979 {
980 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
981 struct sys_info sysinfo;
982 char buf[32];
983 unsigned int i, core;
984 u32 type, rcw, svr = gur_in32(&gur->svr);
985
986 puts("SoC: ");
987
988 cpu_name(buf);
989 printf(" %s (0x%x)\n", buf, svr);
990 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
991 get_sys_info(&sysinfo);
992 puts("Clock Configuration:");
993 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
994 if (!(i % 3))
995 puts("\n ");
996 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
997 printf("CPU%d(%s):%-4s MHz ", core,
998 type == TY_ITYP_VER_A7 ? "A7 " :
999 (type == TY_ITYP_VER_A53 ? "A53" :
1000 (type == TY_ITYP_VER_A57 ? "A57" :
1001 (type == TY_ITYP_VER_A72 ? "A72" : " "))),
1002 strmhz(buf, sysinfo.freq_processor[core]));
1003 }
1004 /* Display platform clock as Bus frequency. */
1005 printf("\n Bus: %-4s MHz ",
1006 strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
1007 printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
1008 #ifdef CONFIG_SYS_DPAA_FMAN
1009 printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
1010 #endif
1011 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
1012 if (soc_has_dp_ddr()) {
1013 printf(" DP-DDR: %-4s MT/s",
1014 strmhz(buf, sysinfo.freq_ddrbus2));
1015 }
1016 #endif
1017 puts("\n");
1018
1019 /*
1020 * Display the RCW, so that no one gets confused as to what RCW
1021 * we're actually using for this boot.
1022 */
1023 puts("Reset Configuration Word (RCW):");
1024 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
1025 rcw = gur_in32(&gur->rcwsr[i]);
1026 if ((i % 4) == 0)
1027 printf("\n %08x:", i * 4);
1028 printf(" %08x", rcw);
1029 }
1030 puts("\n");
1031
1032 return 0;
1033 }
1034 #endif
1035
1036 #ifdef CONFIG_FSL_ESDHC
cpu_mmc_init(bd_t * bis)1037 int cpu_mmc_init(bd_t *bis)
1038 {
1039 return fsl_esdhc_mmc_init(bis);
1040 }
1041 #endif
1042
cpu_eth_init(bd_t * bis)1043 int cpu_eth_init(bd_t *bis)
1044 {
1045 int error = 0;
1046
1047 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1048 error = fsl_mc_ldpaa_init(bis);
1049 #endif
1050 #ifdef CONFIG_FMAN_ENET
1051 fm_standard_init(bis);
1052 #endif
1053 return error;
1054 }
1055
check_psci(void)1056 static inline int check_psci(void)
1057 {
1058 unsigned int psci_ver;
1059
1060 psci_ver = sec_firmware_support_psci_version();
1061 if (psci_ver == PSCI_INVALID_VER)
1062 return 1;
1063
1064 return 0;
1065 }
1066
config_core_prefetch(void)1067 static void config_core_prefetch(void)
1068 {
1069 char *buf = NULL;
1070 char buffer[HWCONFIG_BUFFER_SIZE];
1071 const char *prefetch_arg = NULL;
1072 size_t arglen;
1073 unsigned int mask;
1074 struct pt_regs regs;
1075
1076 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
1077 buf = buffer;
1078 else
1079 return;
1080
1081 prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1082 &arglen, buf);
1083
1084 if (prefetch_arg) {
1085 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1086 if (mask & 0x1) {
1087 printf("Core0 prefetch can't be disabled\n");
1088 return;
1089 }
1090
1091 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
1092 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
1093 regs.regs[1] = mask;
1094 smc_call(®s);
1095
1096 if (regs.regs[0])
1097 printf("Prefetch disable config failed for mask ");
1098 else
1099 printf("Prefetch disable config passed for mask ");
1100 printf("0x%x\n", mask);
1101 }
1102 }
1103
arch_early_init_r(void)1104 int arch_early_init_r(void)
1105 {
1106 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
1107 u32 svr_dev_id;
1108 /*
1109 * erratum A009635 is valid only for LS2080A SoC and
1110 * its personalitiesi
1111 */
1112 svr_dev_id = get_svr();
1113 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1114 erratum_a009635();
1115 #endif
1116 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1117 erratum_a009942_check_cpo();
1118 #endif
1119 if (check_psci()) {
1120 debug("PSCI: PSCI does not exist.\n");
1121
1122 /* if PSCI does not exist, boot secondary cores here */
1123 if (fsl_layerscape_wake_seconday_cores())
1124 printf("Did not wake secondary cores\n");
1125 }
1126
1127 config_core_prefetch();
1128
1129 #ifdef CONFIG_SYS_HAS_SERDES
1130 fsl_serdes_init();
1131 #endif
1132 #ifdef CONFIG_SYS_FSL_HAS_RGMII
1133 /* some dpmacs in armv8a based freescale layerscape SOCs can be
1134 * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
1135 * EC*_PMUX(rgmii) bits in RCW.
1136 * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
1137 * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
1138 * Now if a dpmac is enabled by serdes bits then it takes precedence
1139 * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
1140 * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
1141 * then the dpmac is SGMII and not RGMII.
1142 *
1143 * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
1144 * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
1145 * or not? if it is (fsl_serdes_init has already enabled the dpmac),
1146 * then don't enable it.
1147 */
1148 fsl_rgmii_init();
1149 #endif
1150 #ifdef CONFIG_FMAN_ENET
1151 fman_enet_init();
1152 #endif
1153 #ifdef CONFIG_SYS_DPAA_QBMAN
1154 setup_qbman_portals();
1155 #endif
1156 return 0;
1157 }
1158
timer_init(void)1159 int timer_init(void)
1160 {
1161 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
1162 #ifdef CONFIG_FSL_LSCH3
1163 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
1164 #endif
1165 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1166 defined(CONFIG_ARCH_LS1028A)
1167 u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
1168 u32 svr_dev_id;
1169 #endif
1170 #ifdef COUNTER_FREQUENCY_REAL
1171 unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1172
1173 /* Update with accurate clock frequency */
1174 if (current_el() == 3)
1175 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
1176 #endif
1177
1178 #ifdef CONFIG_FSL_LSCH3
1179 /* Enable timebase for all clusters.
1180 * It is safe to do so even some clusters are not enabled.
1181 */
1182 out_le32(cltbenr, 0xf);
1183 #endif
1184
1185 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1186 defined(CONFIG_ARCH_LS1028A)
1187 /*
1188 * In certain Layerscape SoCs, the clock for each core's
1189 * has an enable bit in the PMU Physical Core Time Base Enable
1190 * Register (PCTBENR), which allows the watchdog to operate.
1191 */
1192 setbits_le32(pctbenr, 0xff);
1193 /*
1194 * For LS2080A SoC and its personalities, timer controller
1195 * offset is different
1196 */
1197 svr_dev_id = get_svr();
1198 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1199 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1200
1201 #endif
1202
1203 /* Enable clock for timer
1204 * This is a global setting.
1205 */
1206 out_le32(cntcr, 0x1);
1207
1208 return 0;
1209 }
1210
1211 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
1212
reset_cpu(ulong addr)1213 void __efi_runtime reset_cpu(ulong addr)
1214 {
1215 u32 val;
1216
1217 #ifdef CONFIG_ARCH_LX2160A
1218 val = in_le32(rstcr);
1219 val |= 0x01;
1220 out_le32(rstcr, val);
1221 #else
1222 /* Raise RESET_REQ_B */
1223 val = scfg_in32(rstcr);
1224 val |= 0x02;
1225 scfg_out32(rstcr, val);
1226 #endif
1227 }
1228
1229 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
1230
efi_reset_system(enum efi_reset_type reset_type,efi_status_t reset_status,unsigned long data_size,void * reset_data)1231 void __efi_runtime EFIAPI efi_reset_system(
1232 enum efi_reset_type reset_type,
1233 efi_status_t reset_status,
1234 unsigned long data_size, void *reset_data)
1235 {
1236 switch (reset_type) {
1237 case EFI_RESET_COLD:
1238 case EFI_RESET_WARM:
1239 case EFI_RESET_PLATFORM_SPECIFIC:
1240 reset_cpu(0);
1241 break;
1242 case EFI_RESET_SHUTDOWN:
1243 /* Nothing we can do */
1244 break;
1245 }
1246
1247 while (1) { }
1248 }
1249
efi_reset_system_init(void)1250 efi_status_t efi_reset_system_init(void)
1251 {
1252 return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
1253 }
1254
1255 #endif
1256
1257 /*
1258 * Calculate reserved memory with given memory bank
1259 * Return aligned memory size on success
1260 * Return (ram_size + needed size) for failure
1261 */
board_reserve_ram_top(phys_size_t ram_size)1262 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1263 {
1264 phys_size_t ram_top = ram_size;
1265
1266 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1267 ram_top = mc_get_dram_block_size();
1268 if (ram_top > ram_size)
1269 return ram_size + ram_top;
1270
1271 ram_top = ram_size - ram_top;
1272 /* The start address of MC reserved memory needs to be aligned. */
1273 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1274 #endif
1275
1276 return ram_size - ram_top;
1277 }
1278
get_effective_memsize(void)1279 phys_size_t get_effective_memsize(void)
1280 {
1281 phys_size_t ea_size, rem = 0;
1282
1283 /*
1284 * For ARMv8 SoCs, DDR memory is split into two or three regions. The
1285 * first region is 2GB space at 0x8000_0000. Secure memory needs to
1286 * allocated from first region. If the memory extends to the second
1287 * region (or the third region if applicable), Management Complex (MC)
1288 * memory should be put into the highest region, i.e. the end of DDR
1289 * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
1290 * U-Boot doesn't relocate itself into higher address. Should DDR be
1291 * configured to skip the first region, this function needs to be
1292 * adjusted.
1293 */
1294 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1295 ea_size = CONFIG_MAX_MEM_MAPPED;
1296 rem = gd->ram_size - ea_size;
1297 } else {
1298 ea_size = gd->ram_size;
1299 }
1300
1301 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1302 /* Check if we have enough space for secure memory */
1303 if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1304 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1305 else
1306 printf("Error: No enough space for secure memory.\n");
1307 #endif
1308 /* Check if we have enough memory for MC */
1309 if (rem < board_reserve_ram_top(rem)) {
1310 /* Not enough memory in high region to reserve */
1311 if (ea_size > board_reserve_ram_top(ea_size))
1312 ea_size -= board_reserve_ram_top(ea_size);
1313 else
1314 printf("Error: No enough space for reserved memory.\n");
1315 }
1316
1317 return ea_size;
1318 }
1319
1320 #ifdef CONFIG_TFABOOT
tfa_get_dram_size(void)1321 phys_size_t tfa_get_dram_size(void)
1322 {
1323 struct pt_regs regs;
1324 phys_size_t dram_size = 0;
1325
1326 regs.regs[0] = SMC_DRAM_BANK_INFO;
1327 regs.regs[1] = -1;
1328
1329 smc_call(®s);
1330 if (regs.regs[0])
1331 return 0;
1332
1333 dram_size = regs.regs[1];
1334 return dram_size;
1335 }
1336
tfa_dram_init_banksize(void)1337 static int tfa_dram_init_banksize(void)
1338 {
1339 int i = 0, ret = 0;
1340 struct pt_regs regs;
1341 phys_size_t dram_size = tfa_get_dram_size();
1342
1343 debug("dram_size %llx\n", dram_size);
1344
1345 if (!dram_size)
1346 return -EINVAL;
1347
1348 do {
1349 regs.regs[0] = SMC_DRAM_BANK_INFO;
1350 regs.regs[1] = i;
1351
1352 smc_call(®s);
1353 if (regs.regs[0]) {
1354 ret = -EINVAL;
1355 break;
1356 }
1357
1358 debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
1359 regs.regs[2]);
1360 gd->bd->bi_dram[i].start = regs.regs[1];
1361 gd->bd->bi_dram[i].size = regs.regs[2];
1362
1363 dram_size -= gd->bd->bi_dram[i].size;
1364
1365 i++;
1366 } while (dram_size);
1367
1368 if (i > 0)
1369 ret = 0;
1370
1371 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1372 /* Assign memory for MC */
1373 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1374 if (gd->bd->bi_dram[2].size >=
1375 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1376 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1377 gd->bd->bi_dram[2].size -
1378 board_reserve_ram_top(gd->bd->bi_dram[2].size);
1379 } else
1380 #endif
1381 {
1382 if (gd->bd->bi_dram[1].size >=
1383 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1384 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1385 gd->bd->bi_dram[1].size -
1386 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1387 } else if (gd->bd->bi_dram[0].size >
1388 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1389 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1390 gd->bd->bi_dram[0].size -
1391 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1392 }
1393 }
1394 #endif /* CONFIG_FSL_MC_ENET */
1395
1396 return ret;
1397 }
1398 #endif
1399
dram_init_banksize(void)1400 int dram_init_banksize(void)
1401 {
1402 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1403 phys_size_t dp_ddr_size;
1404 #endif
1405
1406 #ifdef CONFIG_TFABOOT
1407 if (!tfa_dram_init_banksize())
1408 return 0;
1409 #endif
1410 /*
1411 * gd->ram_size has the total size of DDR memory, less reserved secure
1412 * memory. The DDR extends from low region to high region(s) presuming
1413 * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1414 * the location of secure memory. gd->arch.resv_ram tracks the location
1415 * of reserved memory for Management Complex (MC). Because gd->ram_size
1416 * is reduced by this function if secure memory is reserved, checking
1417 * gd->arch.secure_ram should be done to avoid running it repeatedly.
1418 */
1419
1420 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1421 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1422 debug("No need to run again, skip %s\n", __func__);
1423
1424 return 0;
1425 }
1426 #endif
1427
1428 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1429 if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1430 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1431 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1432 gd->bd->bi_dram[1].size = gd->ram_size -
1433 CONFIG_SYS_DDR_BLOCK1_SIZE;
1434 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1435 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1436 gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1437 gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1438 CONFIG_SYS_DDR_BLOCK2_SIZE;
1439 gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1440 }
1441 #endif
1442 } else {
1443 gd->bd->bi_dram[0].size = gd->ram_size;
1444 }
1445 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1446 if (gd->bd->bi_dram[0].size >
1447 CONFIG_SYS_MEM_RESERVE_SECURE) {
1448 gd->bd->bi_dram[0].size -=
1449 CONFIG_SYS_MEM_RESERVE_SECURE;
1450 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1451 gd->bd->bi_dram[0].size;
1452 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1453 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1454 }
1455 #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
1456
1457 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1458 /* Assign memory for MC */
1459 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1460 if (gd->bd->bi_dram[2].size >=
1461 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1462 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1463 gd->bd->bi_dram[2].size -
1464 board_reserve_ram_top(gd->bd->bi_dram[2].size);
1465 } else
1466 #endif
1467 {
1468 if (gd->bd->bi_dram[1].size >=
1469 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1470 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1471 gd->bd->bi_dram[1].size -
1472 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1473 } else if (gd->bd->bi_dram[0].size >
1474 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1475 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1476 gd->bd->bi_dram[0].size -
1477 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1478 }
1479 }
1480 #endif /* CONFIG_FSL_MC_ENET */
1481
1482 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1483 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1484 #error "This SoC shouldn't have DP DDR"
1485 #endif
1486 if (soc_has_dp_ddr()) {
1487 /* initialize DP-DDR here */
1488 puts("DP-DDR: ");
1489 /*
1490 * DDR controller use 0 as the base address for binding.
1491 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1492 */
1493 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1494 CONFIG_DP_DDR_CTRL,
1495 CONFIG_DP_DDR_NUM_CTRLS,
1496 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1497 NULL, NULL, NULL);
1498 if (dp_ddr_size) {
1499 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1500 gd->bd->bi_dram[2].size = dp_ddr_size;
1501 } else {
1502 puts("Not detected");
1503 }
1504 }
1505 #endif
1506
1507 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1508 debug("%s is called. gd->ram_size is reduced to %lu\n",
1509 __func__, (ulong)gd->ram_size);
1510 #endif
1511
1512 return 0;
1513 }
1514
1515 #if CONFIG_IS_ENABLED(EFI_LOADER)
efi_add_known_memory(void)1516 void efi_add_known_memory(void)
1517 {
1518 int i;
1519 phys_addr_t ram_start, start;
1520 phys_size_t ram_size;
1521 u64 pages;
1522
1523 /* Add RAM */
1524 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1525 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1526 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1527 #error "This SoC shouldn't have DP DDR"
1528 #endif
1529 if (i == 2)
1530 continue; /* skip DP-DDR */
1531 #endif
1532 ram_start = gd->bd->bi_dram[i].start;
1533 ram_size = gd->bd->bi_dram[i].size;
1534 #ifdef CONFIG_RESV_RAM
1535 if (gd->arch.resv_ram >= ram_start &&
1536 gd->arch.resv_ram < ram_start + ram_size)
1537 ram_size = gd->arch.resv_ram - ram_start;
1538 #endif
1539 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
1540 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
1541
1542 efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
1543 false);
1544 }
1545 }
1546 #endif
1547
1548 /*
1549 * Before DDR size is known, early MMU table have DDR mapped as device memory
1550 * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1551 * needs to be set for these mappings.
1552 * If a special case configures DDR with holes in the mapping, the holes need
1553 * to be marked as invalid. This is not implemented in this function.
1554 */
update_early_mmu_table(void)1555 void update_early_mmu_table(void)
1556 {
1557 if (!gd->arch.tlb_addr)
1558 return;
1559
1560 if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1561 mmu_change_region_attr(
1562 CONFIG_SYS_SDRAM_BASE,
1563 gd->ram_size,
1564 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1565 PTE_BLOCK_OUTER_SHARE |
1566 PTE_BLOCK_NS |
1567 PTE_TYPE_VALID);
1568 } else {
1569 mmu_change_region_attr(
1570 CONFIG_SYS_SDRAM_BASE,
1571 CONFIG_SYS_DDR_BLOCK1_SIZE,
1572 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1573 PTE_BLOCK_OUTER_SHARE |
1574 PTE_BLOCK_NS |
1575 PTE_TYPE_VALID);
1576 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1577 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1578 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1579 #endif
1580 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1581 CONFIG_SYS_DDR_BLOCK2_SIZE) {
1582 mmu_change_region_attr(
1583 CONFIG_SYS_DDR_BLOCK2_BASE,
1584 CONFIG_SYS_DDR_BLOCK2_SIZE,
1585 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1586 PTE_BLOCK_OUTER_SHARE |
1587 PTE_BLOCK_NS |
1588 PTE_TYPE_VALID);
1589 mmu_change_region_attr(
1590 CONFIG_SYS_DDR_BLOCK3_BASE,
1591 gd->ram_size -
1592 CONFIG_SYS_DDR_BLOCK1_SIZE -
1593 CONFIG_SYS_DDR_BLOCK2_SIZE,
1594 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1595 PTE_BLOCK_OUTER_SHARE |
1596 PTE_BLOCK_NS |
1597 PTE_TYPE_VALID);
1598 } else
1599 #endif
1600 {
1601 mmu_change_region_attr(
1602 CONFIG_SYS_DDR_BLOCK2_BASE,
1603 gd->ram_size -
1604 CONFIG_SYS_DDR_BLOCK1_SIZE,
1605 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1606 PTE_BLOCK_OUTER_SHARE |
1607 PTE_BLOCK_NS |
1608 PTE_TYPE_VALID);
1609 }
1610 }
1611 }
1612
dram_init(void)1613 __weak int dram_init(void)
1614 {
1615 fsl_initdram();
1616 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1617 defined(CONFIG_SPL_BUILD)
1618 /* This will break-before-make MMU for DDR */
1619 update_early_mmu_table();
1620 #endif
1621
1622 return 0;
1623 }
1624