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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2019 DENX Software Engineering
4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5  *
6  * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
7  * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
8  */
9 #ifndef __LINUX_CLK_PROVIDER_H
10 #define __LINUX_CLK_PROVIDER_H
11 #include <clk-uclass.h>
12 
clk_dm(ulong id,struct clk * clk)13 static inline void clk_dm(ulong id, struct clk *clk)
14 {
15 	if (!IS_ERR(clk))
16 		clk->id = id;
17 }
18 
19 /*
20  * flags used across common struct clk.  these flags should only affect the
21  * top-level framework.  custom flags for dealing with hardware specifics
22  * belong in struct clk_foo
23  *
24  * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
25  */
26 #define CLK_SET_RATE_GATE	BIT(0) /* must be gated across rate change */
27 #define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
28 #define CLK_SET_RATE_PARENT	BIT(2) /* propagate rate change up one level */
29 #define CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */
30 				/* unused */
31 #define CLK_IS_BASIC		BIT(5) /* Basic clk, can't do a to_clk_foo() */
32 #define CLK_GET_RATE_NOCACHE	BIT(6) /* do not use the cached clk rate */
33 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
34 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
35 #define CLK_RECALC_NEW_RATES	BIT(9) /* recalc rates after notifications */
36 #define CLK_SET_RATE_UNGATE	BIT(10) /* clock needs to run to set rate */
37 #define CLK_IS_CRITICAL		BIT(11) /* do not gate, ever */
38 /* parents need enable during gate/ungate, set rate and re-parent */
39 #define CLK_OPS_PARENT_ENABLE	BIT(12)
40 /* duty cycle call may be forwarded to the parent clock */
41 #define CLK_DUTY_CYCLE_PARENT	BIT(13)
42 
43 #define CLK_MUX_INDEX_ONE		BIT(0)
44 #define CLK_MUX_INDEX_BIT		BIT(1)
45 #define CLK_MUX_HIWORD_MASK		BIT(2)
46 #define CLK_MUX_READ_ONLY		BIT(3) /* mux can't be changed */
47 #define CLK_MUX_ROUND_CLOSEST		BIT(4)
48 
49 struct clk_mux {
50 	struct clk	clk;
51 	void __iomem	*reg;
52 	u32		*table;
53 	u32		mask;
54 	u8		shift;
55 	u8		flags;
56 
57 	/*
58 	 * Fields from struct clk_init_data - this struct has been
59 	 * omitted to avoid too deep level of CCF for bootloader
60 	 */
61 	const char	* const *parent_names;
62 	u8		num_parents;
63 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
64 	u32             io_mux_val;
65 #endif
66 
67 };
68 
69 #define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
70 extern const struct clk_ops clk_mux_ops;
71 u8 clk_mux_get_parent(struct clk *clk);
72 
73 struct clk_gate {
74 	struct clk	clk;
75 	void __iomem	*reg;
76 	u8		bit_idx;
77 	u8		flags;
78 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
79 	u32		io_gate_val;
80 #endif
81 };
82 
83 #define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk)
84 
85 #define CLK_GATE_SET_TO_DISABLE		BIT(0)
86 #define CLK_GATE_HIWORD_MASK		BIT(1)
87 
88 extern const struct clk_ops clk_gate_ops;
89 struct clk *clk_register_gate(struct device *dev, const char *name,
90 			      const char *parent_name, unsigned long flags,
91 			      void __iomem *reg, u8 bit_idx,
92 			      u8 clk_gate_flags, spinlock_t *lock);
93 
94 struct clk_div_table {
95 	unsigned int	val;
96 	unsigned int	div;
97 };
98 
99 struct clk_divider {
100 	struct clk	clk;
101 	void __iomem	*reg;
102 	u8		shift;
103 	u8		width;
104 	u8		flags;
105 	const struct clk_div_table	*table;
106 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
107 	u32             io_divider_val;
108 #endif
109 };
110 
111 #define clk_div_mask(width)	((1 << (width)) - 1)
112 #define to_clk_divider(_clk) container_of(_clk, struct clk_divider, clk)
113 
114 #define CLK_DIVIDER_ONE_BASED		BIT(0)
115 #define CLK_DIVIDER_POWER_OF_TWO	BIT(1)
116 #define CLK_DIVIDER_ALLOW_ZERO		BIT(2)
117 #define CLK_DIVIDER_HIWORD_MASK		BIT(3)
118 #define CLK_DIVIDER_ROUND_CLOSEST	BIT(4)
119 #define CLK_DIVIDER_READ_ONLY		BIT(5)
120 #define CLK_DIVIDER_MAX_AT_ZERO		BIT(6)
121 extern const struct clk_ops clk_divider_ops;
122 unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
123 				  unsigned int val,
124 				  const struct clk_div_table *table,
125 				  unsigned long flags, unsigned long width);
126 
127 struct clk_fixed_factor {
128 	struct clk	clk;
129 	unsigned int	mult;
130 	unsigned int	div;
131 };
132 
133 #define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
134 					       clk)
135 
136 struct clk_fixed_rate {
137 	struct clk clk;
138 	unsigned long fixed_rate;
139 };
140 
141 #define to_clk_fixed_rate(dev)	((struct clk_fixed_rate *)dev_get_platdata(dev))
142 
143 struct clk_composite {
144 	struct clk	clk;
145 	struct clk_ops	ops;
146 
147 	struct clk	*mux;
148 	struct clk	*rate;
149 	struct clk	*gate;
150 
151 	const struct clk_ops	*mux_ops;
152 	const struct clk_ops	*rate_ops;
153 	const struct clk_ops	*gate_ops;
154 };
155 
156 #define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk)
157 
158 struct clk *clk_register_composite(struct device *dev, const char *name,
159 		const char * const *parent_names, int num_parents,
160 		struct clk *mux_clk, const struct clk_ops *mux_ops,
161 		struct clk *rate_clk, const struct clk_ops *rate_ops,
162 		struct clk *gate_clk, const struct clk_ops *gate_ops,
163 		unsigned long flags);
164 
165 int clk_register(struct clk *clk, const char *drv_name, const char *name,
166 		 const char *parent_name);
167 
168 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
169 		const char *parent_name, unsigned long flags,
170 		unsigned int mult, unsigned int div);
171 
172 struct clk *clk_register_divider(struct device *dev, const char *name,
173 		const char *parent_name, unsigned long flags,
174 		void __iomem *reg, u8 shift, u8 width,
175 		u8 clk_divider_flags);
176 
177 struct clk *clk_register_mux(struct device *dev, const char *name,
178 		const char * const *parent_names, u8 num_parents,
179 		unsigned long flags,
180 		void __iomem *reg, u8 shift, u8 width,
181 		u8 clk_mux_flags);
182 
183 const char *clk_hw_get_name(const struct clk *hw);
184 ulong clk_generic_get_rate(struct clk *clk);
185 
dev_get_clk_ptr(struct udevice * dev)186 static inline struct clk *dev_get_clk_ptr(struct udevice *dev)
187 {
188 	return (struct clk *)dev_get_uclass_priv(dev);
189 }
190 #endif /* __LINUX_CLK_PROVIDER_H */
191