| /external/elfutils/tests/ |
| D | run-show-die-info.sh | 28 Offset : 11
29 CU offset : 11
38 Offset : 104
39 CU offset : 104
45 Offset : 127
46 CU offset : 127
52 Offset : 146
53 CU offset : 11
62 Offset : 239
63 CU offset : 104
[all …]
|
| D | run-show-abbrev.sh | 25 abbrev[0]: attr[0]: code = 16, form = 6, offset = 0
26 abbrev[0]: attr[1]: code = 18, form = 1, offset = 2
27 abbrev[0]: attr[2]: code = 17, form = 1, offset = 4
28 abbrev[0]: attr[3]: code = 3, form = 8, offset = 6
29 abbrev[0]: attr[4]: code = 27, form = 8, offset = 8
30 abbrev[0]: attr[5]: code = 37, form = 8, offset = 10
31 abbrev[0]: attr[6]: code = 19, form = 11, offset = 12
33 abbrev[19]: attr[0]: code = 1, form = 19, offset = 19
34 abbrev[19]: attr[1]: code = 63, form = 12, offset = 21
35 abbrev[19]: attr[2]: code = 3, form = 8, offset = 23
[all …]
|
| /external/mesa3d/src/freedreno/registers/dsi/ |
| D | dsi.xml | 66 <reg32 offset="0x00000" name="6G_HW_VERSION">
72 <reg32 offset="0x00000" name="CTRL">
85 <reg32 offset="0x00004" name="STATUS0">
94 <reg32 offset="0x00008" name="FIFO_STATUS">
121 <reg32 offset="0x0000c" name="VID_CFG0">
132 <reg32 offset="0x0001c" name="VID_CFG1">
138 <reg32 offset="0x00020" name="ACTIVE_H">
142 <reg32 offset="0x00024" name="ACTIVE_V">
146 <reg32 offset="0x00028" name="TOTAL">
150 <reg32 offset="0x0002c" name="ACTIVE_HSYNC">
[all …]
|
| /external/mesa3d/src/freedreno/fdl/ |
| D | fd6_layout_test.c | 39 { .offset = 0, .pitch = 256 },
40 { .offset = 8192, .pitch = 256 },
41 { .offset = 12288, .pitch = 256 },
42 { .offset = 14336, .pitch = 256 },
43 { .offset = 15360, .pitch = 256 },
44 { .offset = 15872, .pitch = 256 },
59 { .offset = 0, .pitch = 4096 },
60 { .offset = 65536, .pitch = 2048 },
61 { .offset = 98304, .pitch = 1024 },
62 { .offset = 114688, .pitch = 512 },
[all …]
|
| /external/mesa3d/src/freedreno/registers/hdmi/ |
| D | hdmi.xml | 35 <reg32 offset="0x00000" name="CTRL">
40 <reg32 offset="0x00020" name="AUDIO_PKT_CTRL1">
43 <reg32 offset="0x00024" name="ACR_PKT_CTRL">
60 <reg32 offset="0x0028" name="VBI_PKT_CTRL">
80 <reg32 offset="0x0002c" name="INFOFRAME_CTRL0">
97 <reg32 offset="0x00030" name="INFOFRAME_CTRL1">
103 <reg32 offset="0x00034" name="GEN_PKT_CTRL">
133 <reg32 offset="0x00040" name="GC">
136 <reg32 offset="0x00044" name="AUDIO_PKT_CTRL2">
145 <reg32 offset="0x0006c" name="AVI_INFO" stride="4" length="4"/>
[all …]
|
| /external/u-boot/arch/x86/include/asm/arch-braswell/fsp/ |
| D | fsp_vpd.h | 11 u64 signature; /* Offset 0x0020 */
12 u8 revision; /* Offset 0x0028 */
13 u8 unused2[7]; /* Offset 0x0029 */
14 u16 mrc_init_tseg_size; /* Offset 0x0030 */
15 u16 mrc_init_mmio_size; /* Offset 0x0032 */
16 u8 mrc_init_spd_addr1; /* Offset 0x0034 */
17 u8 mrc_init_spd_addr2; /* Offset 0x0035 */
18 u8 mem_ch0_config; /* Offset 0x0036 */
19 u8 mem_ch1_config; /* Offset 0x0037 */
20 u32 memory_spd_ptr; /* Offset 0x0038 */
[all …]
|
| /external/mesa3d/src/freedreno/registers/adreno/ |
| D | a6xx_gmu.xml | 42 <reg32 offset="0x80" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/>
43 <reg32 offset="0x81" name="GMU_GX_SPTPRAC_POWER_CONTROL"/>
44 <reg32 offset="0xc00" name="GMU_CM3_ITCM_START"/>
45 <reg32 offset="0x1c00" name="GMU_CM3_DTCM_START"/>
46 <reg32 offset="0x23f0" name="GMU_NMI_CONTROL_STATUS"/>
47 <reg32 offset="0x23f8" name="GMU_BOOT_SLUMBER_OPTION"/>
48 <reg32 offset="0x23f9" name="GMU_GX_VOTE_IDX"/>
49 <reg32 offset="0x23fa" name="GMU_MX_VOTE_IDX"/>
50 <reg32 offset="0x23fc" name="GMU_DCVS_ACK_OPTION"/>
51 <reg32 offset="0x23fd" name="GMU_DCVS_PERF_SETTING"/>
[all …]
|
| D | a5xx.xml | 862 <reg32 offset="0x0800" name="CP_RB_BASE"/>
863 <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
864 <reg32 offset="0x0802" name="CP_RB_CNTL"/>
865 <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
866 <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
867 <reg32 offset="0x0806" name="CP_RB_RPTR"/>
868 <reg32 offset="0x0807" name="CP_RB_WPTR"/>
869 <reg32 offset="0x0808" name="CP_PFP_STAT_ADDR"/>
870 <reg32 offset="0x0809" name="CP_PFP_STAT_DATA"/>
871 <reg32 offset="0x080b" name="CP_DRAW_STATE_ADDR"/>
[all …]
|
| D | a6xx.xml | 967 <reg32 offset="0x0800" name="CP_RB_BASE"/>
968 <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
969 <reg32 offset="0x0802" name="CP_RB_CNTL"/>
970 <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR_LO"/>
971 <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
972 <reg32 offset="0x0806" name="CP_RB_RPTR"/>
973 <reg32 offset="0x0807" name="CP_RB_WPTR"/>
974 <reg32 offset="0x0808" name="CP_SQE_CNTL"/>
975 <reg32 offset="0x0812" name="CP_CP2GMU_STATUS">
978 <reg32 offset="0x0821" name="CP_HW_FAULT"/>
[all …]
|
| /external/u-boot/board/siemens/draco/ |
| D | mux.c | 22 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
23 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
28 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
29 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
34 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
36 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
42 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
43 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
44 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
45 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
[all …]
|
| /external/u-boot/board/siemens/rut/ |
| D | mux.c | 22 {OFFSET(uart0_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART0_RXD */
23 {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */
28 {OFFSET(ddr_resetn), (MODE(0))},
29 {OFFSET(ddr_csn0), (MODE(0) | PULLUP_EN)},
30 {OFFSET(ddr_ck), (MODE(0))},
31 {OFFSET(ddr_nck), (MODE(0))},
32 {OFFSET(ddr_casn), (MODE(0) | PULLUP_EN)},
33 {OFFSET(ddr_rasn), (MODE(0) | PULLUP_EN)},
34 {OFFSET(ddr_wen), (MODE(0) | PULLUP_EN)},
35 {OFFSET(ddr_ba0), (MODE(0) | PULLUP_EN)},
[all …]
|
| /external/u-boot/arch/arm/include/asm/arch-am33xx/ |
| D | cpu.h | 80 unsigned int wkclkstctrl; /* offset 0x00 */
81 unsigned int wkctrlclkctrl; /* offset 0x04 */
82 unsigned int wkgpio0clkctrl; /* offset 0x08 */
83 unsigned int wkl4wkclkctrl; /* offset 0x0c */
84 unsigned int timer0clkctrl; /* offset 0x10 */
86 unsigned int idlestdpllmpu; /* offset 0x20 */
89 unsigned int clkseldpllmpu; /* offset 0x2c */
91 unsigned int idlestdpllddr; /* offset 0x34 */
93 unsigned int clkseldpllddr; /* offset 0x40 */
95 unsigned int clkseldplldisp; /* offset 0x54 */
[all …]
|
| /external/u-boot/arch/arm/include/asm/arch-tegra/ |
| D | pmc.h | 12 uint pmc_cntrl; /* _CNTRL_0, offset 00 */
13 uint pmc_sec_disable; /* _SEC_DISABLE_0, offset 04 */
14 uint pmc_pmc_swrst; /* _PMC_SWRST_0, offset 08 */
15 uint pmc_wake_mask; /* _WAKE_MASK_0, offset 0C */
16 uint pmc_wake_lvl; /* _WAKE_LVL_0, offset 10 */
17 uint pmc_wake_status; /* _WAKE_STATUS_0, offset 14 */
18 uint pmc_sw_wake_status; /* _SW_WAKE_STATUS_0, offset 18 */
19 uint pmc_dpd_pads_oride; /* _DPD_PADS_ORIDE_0, offset 1C */
20 uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */
21 uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */
[all …]
|
| /external/u-boot/arch/arm/include/asm/arch-meson/ |
| D | clock-gx.h | 16 #define SCR 0x2C /* 0x0b offset in data sheet */
17 #define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */
19 #define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
20 #define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
21 #define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
22 #define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */
23 #define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
24 #define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */
26 #define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */
27 #define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */
[all …]
|
| /external/u-boot/arch/x86/include/asm/arch-baytrail/fsp/ |
| D | fsp_vpd.h | 31 uint64_t signature; /* Offset 0x0000 */
32 uint8_t reserved0[24]; /* Offset 0x0008 */
33 uint16_t mrc_init_tseg_size; /* Offset 0x0020 */
34 uint16_t mrc_init_mmio_size; /* Offset 0x0022 */
35 uint8_t mrc_init_spd_addr1; /* Offset 0x0024 */
36 uint8_t mrc_init_spd_addr2; /* Offset 0x0025 */
37 uint8_t emmc_boot_mode; /* Offset 0x0026 */
38 uint8_t enable_sdio; /* Offset 0x0027 */
39 uint8_t enable_sdcard; /* Offset 0x0028 */
40 uint8_t enable_hsuart0; /* Offset 0x0029 */
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/unittests/Support/ |
| D | DataExtractorTest.cpp | 28 uint32_t offset = 0; in TEST() local
30 EXPECT_EQ(0x80U, DE.getU8(&offset)); in TEST()
31 EXPECT_EQ(1U, offset); in TEST()
32 offset = 0; in TEST()
33 EXPECT_EQ(0x8090U, DE.getU16(&offset)); in TEST()
34 EXPECT_EQ(2U, offset); in TEST()
35 offset = 0; in TEST()
36 EXPECT_EQ(0x8090FFFFU, DE.getU32(&offset)); in TEST()
37 EXPECT_EQ(4U, offset); in TEST()
38 offset = 0; in TEST()
[all …]
|
| /external/llvm/unittests/Support/ |
| D | DataExtractorTest.cpp | 28 uint32_t offset = 0; in TEST() local
30 EXPECT_EQ(0x80U, DE.getU8(&offset)); in TEST()
31 EXPECT_EQ(1U, offset); in TEST()
32 offset = 0; in TEST()
33 EXPECT_EQ(0x8090U, DE.getU16(&offset)); in TEST()
34 EXPECT_EQ(2U, offset); in TEST()
35 offset = 0; in TEST()
36 EXPECT_EQ(0x8090FFFFU, DE.getU32(&offset)); in TEST()
37 EXPECT_EQ(4U, offset); in TEST()
38 offset = 0; in TEST()
[all …]
|
| /external/libnetfilter_conntrack/src/expect/ |
| D | snprintf_xml.c | 57 unsigned int size = 0, offset = 0; in snprintf_expect_meta_xml() local
60 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
63 ret = snprintf(buf+offset, len, in snprintf_expect_meta_xml()
66 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
69 ret = snprintf(buf+offset, len, "<timeout>%u</timeout>", in snprintf_expect_meta_xml()
71 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
74 ret = snprintf(buf+offset, len, "<class>%u</class>", in snprintf_expect_meta_xml()
76 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
79 ret = snprintf(buf+offset, len, "<zone>%u</zone>", exp->zone); in snprintf_expect_meta_xml()
80 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
[all …]
|
| /external/u-boot/board/bosch/shc/ |
| D | mux.c | 21 {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_RXD */
22 {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */
23 {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_CTS */
24 {OFFSET(uart0_rtsn), (MODE(0) | PULLUDDIS)}, /* UART0_RTS */
29 {OFFSET(uart1_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART1_RXD */
30 {OFFSET(uart1_txd), (MODE(0) | PULLUDDIS)}, /* UART1_TXD */
31 {OFFSET(uart1_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART1_CTS */
32 {OFFSET(uart1_rtsn), (MODE(0) | PULLUDDIS)}, /* UART1_RTS */
37 {OFFSET(spi0_sclk), (MODE(1) | PULLUDDIS | RXACTIVE)}, /* UART2_RXD */
38 {OFFSET(spi0_d0), (MODE(1) | PULLUDDIS)}, /* UART2_TXD */
[all …]
|
| /external/flatbuffers/tests/ |
| D | monster_test_generated.ts | 83 * @returns flatbuffers.Offset
85 static endInParentNamespace(builder:flatbuffers.Builder):flatbuffers.Offset {
86 var offset = builder.endObject();
87 return offset;
90 static createInParentNamespace(builder:flatbuffers.Builder):flatbuffers.Offset {
133 * @returns flatbuffers.Offset
135 static endMonster(builder:flatbuffers.Builder):flatbuffers.Offset {
136 var offset = builder.endObject();
137 return offset;
140 static createMonster(builder:flatbuffers.Builder):flatbuffers.Offset {
[all …]
|
| /external/u-boot/arch/arm/include/asm/arch-tegra124/ |
| D | mc.h | 13 u32 reserved0[4]; /* offset 0x00 - 0x0C */
14 u32 mc_smmu_config; /* offset 0x10 */
15 u32 mc_smmu_tlb_config; /* offset 0x14 */
16 u32 mc_smmu_ptc_config; /* offset 0x18 */
17 u32 mc_smmu_ptb_asid; /* offset 0x1C */
18 u32 mc_smmu_ptb_data; /* offset 0x20 */
19 u32 reserved1[3]; /* offset 0x24 - 0x2C */
20 u32 mc_smmu_tlb_flush; /* offset 0x30 */
21 u32 mc_smmu_ptc_flush; /* offset 0x34 */
22 u32 reserved2[6]; /* offset 0x38 - 0x4C */
[all …]
|
| /external/u-boot/arch/arm/include/asm/arch-tegra210/ |
| D | mc.h | 13 u32 reserved0[4]; /* offset 0x00 - 0x0C */
14 u32 mc_smmu_config; /* offset 0x10 */
15 u32 mc_smmu_tlb_config; /* offset 0x14 */
16 u32 mc_smmu_ptc_config; /* offset 0x18 */
17 u32 mc_smmu_ptb_asid; /* offset 0x1C */
18 u32 mc_smmu_ptb_data; /* offset 0x20 */
19 u32 reserved1[3]; /* offset 0x24 - 0x2C */
20 u32 mc_smmu_tlb_flush; /* offset 0x30 */
21 u32 mc_smmu_ptc_flush; /* offset 0x34 */
22 u32 reserved2[6]; /* offset 0x38 - 0x4C */
[all …]
|
| /external/u-boot/board/BuR/brppt1/ |
| D | mux.c | 20 {OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)},
22 {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
24 {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
31 {OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
33 {OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
35 {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
37 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
42 {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
43 {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-pdbdump/ |
| D | explain-dbi-stream.test | 2 ; RUN: -offset=0xF000 \
3 ; RUN: -offset=0xF004 \
4 ; RUN: -offset=0xF008 \
5 ; RUN: -offset=0xF00C \
6 ; RUN: -offset=0xF00E \
7 ; RUN: -offset=0xF010 \
8 ; RUN: -offset=0xF012 \
9 ; RUN: -offset=0xF014 \
10 ; RUN: -offset=0xF016 \
11 ; RUN: -offset=0xF018 \
[all …]
|
| /external/u-boot/board/siemens/pxm2/ |
| D | mux.c | 23 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
24 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
25 {OFFSET(nnmi), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_TXD */
31 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
32 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
33 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
34 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
35 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
36 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
37 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
[all …]
|