1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2019
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 *
6 * Common Clock Framework [CCF] driver for Sandbox
7 */
8
9 #include <common.h>
10 #include <dm.h>
11 #include <clk.h>
12 #include <asm/clk.h>
13 #include <clk-uclass.h>
14 #include <linux/clk-provider.h>
15 #include <sandbox-clk.h>
16
17 /*
18 * Sandbox implementation of CCF primitives necessary for clk-uclass testing
19 *
20 * --- Sandbox PLLv3 ---
21 */
22 struct clk_pllv3 {
23 struct clk clk;
24 u32 div_mask;
25 u32 div_shift;
26 };
27
sandbox_clk_enable_count(struct clk * clk)28 int sandbox_clk_enable_count(struct clk *clk)
29 {
30 struct clk *clkp = NULL;
31 int ret;
32
33 ret = clk_get_by_id(clk->id, &clkp);
34 if (ret)
35 return 0;
36
37 return clkp->enable_count;
38 }
39
clk_pllv3_get_rate(struct clk * clk)40 static ulong clk_pllv3_get_rate(struct clk *clk)
41 {
42 unsigned long parent_rate = clk_get_parent_rate(clk);
43
44 return parent_rate * 24;
45 }
46
47 static const struct clk_ops clk_pllv3_generic_ops = {
48 .get_rate = clk_pllv3_get_rate,
49 };
50
sandbox_clk_pllv3(enum sandbox_pllv3_type type,const char * name,const char * parent_name,void __iomem * base,u32 div_mask)51 struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
52 const char *parent_name, void __iomem *base,
53 u32 div_mask)
54 {
55 struct clk_pllv3 *pll;
56 struct clk *clk;
57 char *drv_name = "sandbox_clk_pllv3";
58 int ret;
59
60 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
61 if (!pll)
62 return ERR_PTR(-ENOMEM);
63
64 pll->div_mask = div_mask;
65 clk = &pll->clk;
66
67 ret = clk_register(clk, drv_name, name, parent_name);
68 if (ret) {
69 kfree(pll);
70 return ERR_PTR(ret);
71 }
72
73 return clk;
74 }
75
76 U_BOOT_DRIVER(sandbox_clk_pll_generic) = {
77 .name = "sandbox_clk_pllv3",
78 .id = UCLASS_CLK,
79 .ops = &clk_pllv3_generic_ops,
80 };
81
82 /* --- Sandbox PLLv3 --- */
83 /* --- Sandbox Gate --- */
84 struct clk_gate2 {
85 struct clk clk;
86 bool state;
87 };
88
89 #define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
90
clk_gate2_enable(struct clk * clk)91 static int clk_gate2_enable(struct clk *clk)
92 {
93 struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
94
95 gate->state = 1;
96 return 0;
97 }
98
clk_gate2_disable(struct clk * clk)99 static int clk_gate2_disable(struct clk *clk)
100 {
101 struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
102
103 gate->state = 0;
104 return 0;
105 }
106
107 static const struct clk_ops clk_gate2_ops = {
108 .enable = clk_gate2_enable,
109 .disable = clk_gate2_disable,
110 .get_rate = clk_generic_get_rate,
111 };
112
sandbox_clk_register_gate2(struct device * dev,const char * name,const char * parent_name,unsigned long flags,void __iomem * reg,u8 bit_idx,u8 cgr_val,u8 clk_gate2_flags)113 struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
114 const char *parent_name,
115 unsigned long flags, void __iomem *reg,
116 u8 bit_idx, u8 cgr_val,
117 u8 clk_gate2_flags)
118 {
119 struct clk_gate2 *gate;
120 struct clk *clk;
121 int ret;
122
123 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
124 if (!gate)
125 return ERR_PTR(-ENOMEM);
126
127 gate->state = 0;
128 clk = &gate->clk;
129
130 ret = clk_register(clk, "sandbox_clk_gate2", name, parent_name);
131 if (ret) {
132 kfree(gate);
133 return ERR_PTR(ret);
134 }
135
136 return clk;
137 }
138
139 U_BOOT_DRIVER(sandbox_clk_gate2) = {
140 .name = "sandbox_clk_gate2",
141 .id = UCLASS_CLK,
142 .ops = &clk_gate2_ops,
143 };
144
sandbox_clk_composite_divider_recalc_rate(struct clk * clk)145 static unsigned long sandbox_clk_composite_divider_recalc_rate(struct clk *clk)
146 {
147 struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
148 struct clk_composite *composite = (struct clk_composite *)clk->data;
149 ulong parent_rate = clk_get_parent_rate(&composite->clk);
150 unsigned int val;
151
152 val = divider->io_divider_val;
153 val >>= divider->shift;
154 val &= clk_div_mask(divider->width);
155
156 return divider_recalc_rate(clk, parent_rate, val, divider->table,
157 divider->flags, divider->width);
158 }
159
160 static const struct clk_ops sandbox_clk_composite_divider_ops = {
161 .get_rate = sandbox_clk_composite_divider_recalc_rate,
162 };
163
sandbox_clk_composite(const char * name,const char * const * parent_names,int num_parents,void __iomem * reg,unsigned long flags)164 struct clk *sandbox_clk_composite(const char *name,
165 const char * const *parent_names,
166 int num_parents, void __iomem *reg,
167 unsigned long flags)
168 {
169 struct clk *clk = ERR_PTR(-ENOMEM);
170 struct clk_divider *div = NULL;
171 struct clk_gate *gate = NULL;
172 struct clk_mux *mux = NULL;
173
174 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
175 if (!mux)
176 goto fail;
177
178 mux->reg = reg;
179 mux->shift = 24;
180 mux->mask = 0x7;
181 mux->num_parents = num_parents;
182 mux->flags = flags;
183 mux->parent_names = parent_names;
184
185 div = kzalloc(sizeof(*div), GFP_KERNEL);
186 if (!div)
187 goto fail;
188
189 div->reg = reg;
190 div->shift = 16;
191 div->width = 3;
192 div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
193
194 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
195 if (!gate)
196 goto fail;
197
198 gate->reg = reg;
199 gate->bit_idx = 28;
200 gate->flags = flags;
201
202 clk = clk_register_composite(NULL, name,
203 parent_names, num_parents,
204 &mux->clk, &clk_mux_ops, &div->clk,
205 &sandbox_clk_composite_divider_ops,
206 &gate->clk, &clk_gate_ops, flags);
207 if (IS_ERR(clk))
208 goto fail;
209
210 return clk;
211
212 fail:
213 kfree(gate);
214 kfree(div);
215 kfree(mux);
216 return ERR_CAST(clk);
217 }
218
219 /* --- Sandbox Gate --- */
220 /* The CCF core driver itself */
221 static const struct udevice_id sandbox_clk_ccf_test_ids[] = {
222 { .compatible = "sandbox,clk-ccf" },
223 { }
224 };
225
226 static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", };
227 static const char *const i2c_sels[] = { "pll3_60m", "pll3_80m", };
228
sandbox_clk_ccf_probe(struct udevice * dev)229 static int sandbox_clk_ccf_probe(struct udevice *dev)
230 {
231 void *base = NULL;
232 u32 reg;
233
234 clk_dm(SANDBOX_CLK_PLL3,
235 sandbox_clk_pllv3(SANDBOX_PLLV3_USB, "pll3_usb_otg", "osc",
236 base + 0x10, 0x3));
237
238 clk_dm(SANDBOX_CLK_PLL3_60M,
239 sandbox_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
240
241 clk_dm(SANDBOX_CLK_PLL3_80M,
242 sandbox_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
243
244 /* The HW adds +1 to the divider value (2+1) is the divider */
245 reg = (2 << 19);
246 clk_dm(SANDBOX_CLK_ECSPI_ROOT,
247 sandbox_clk_divider("ecspi_root", "pll3_60m", ®, 19, 6));
248
249 clk_dm(SANDBOX_CLK_ECSPI1,
250 sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
251
252 /* Select 'pll3_60m' */
253 reg = 0;
254 clk_dm(SANDBOX_CLK_USDHC1_SEL,
255 sandbox_clk_mux("usdhc1_sel", ®, 16, 1, usdhc_sels,
256 ARRAY_SIZE(usdhc_sels)));
257
258 /* Select 'pll3_80m' */
259 reg = BIT(17);
260 clk_dm(SANDBOX_CLK_USDHC2_SEL,
261 sandbox_clk_mux("usdhc2_sel", ®, 17, 1, usdhc_sels,
262 ARRAY_SIZE(usdhc_sels)));
263
264 reg = BIT(28) | BIT(24) | BIT(16);
265 clk_dm(SANDBOX_CLK_I2C,
266 sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels),
267 ®, 0));
268
269 clk_dm(SANDBOX_CLK_I2C_ROOT,
270 sandbox_clk_gate2("i2c_root", "i2c", base + 0x7c, 0));
271
272 return 0;
273 }
274
275 U_BOOT_DRIVER(sandbox_clk_ccf) = {
276 .name = "sandbox_clk_ccf",
277 .id = UCLASS_CLK,
278 .probe = sandbox_clk_ccf_probe,
279 .of_match = sandbox_clk_ccf_test_ids,
280 };
281