1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __XLAT_TABLES_AARCH64_H__ 8 #define __XLAT_TABLES_AARCH64_H__ 9 10 #include <arch.h> 11 #include <utils_def.h> 12 #include <xlat_tables_defs.h> 13 14 #if !defined(PAGE_SIZE) 15 #error "PAGE_SIZE is not defined." 16 #endif 17 18 /* 19 * In AArch64 state, the MMU may support 4 KB, 16 KB and 64 KB page 20 * granularity. For 4KB granularity, a level 0 table descriptor doesn't support 21 * block translation. For 16KB, the same thing happens to levels 0 and 1. For 22 * 64KB, same for level 1. See section D4.3.1 of the ARMv8-A Architecture 23 * Reference Manual (DDI 0487A.k) for more information. 24 * 25 * The define below specifies the first table level that allows block 26 * descriptors. 27 */ 28 #if PAGE_SIZE == (4 * 1024) 29 # define MIN_LVL_BLOCK_DESC U(1) 30 #elif PAGE_SIZE == (16 * 1024) || PAGE_SIZE == (64 * 1024) 31 # define MIN_LVL_BLOCK_DESC U(2) 32 #endif 33 34 #define XLAT_TABLE_LEVEL_MIN U(0) 35 36 /* 37 * Define the architectural limits of the virtual address space in AArch64 38 * state. 39 * 40 * TCR.TxSZ is calculated as 64 minus the width of said address space. 41 * The value of TCR.TxSZ must be in the range 16 to 39 [1], which means that 42 * the virtual address space width must be in the range 48 to 25 bits. 43 * 44 * [1] See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more 45 * information: 46 * Page 1730: 'Input address size', 'For all translation stages'. 47 */ 48 #define MIN_VIRT_ADDR_SPACE_SIZE (ULL(1) << (64 - TCR_TxSZ_MAX)) 49 #define MAX_VIRT_ADDR_SPACE_SIZE (ULL(1) << (64 - TCR_TxSZ_MIN)) 50 51 /* 52 * Here we calculate the initial lookup level from the value of the given 53 * virtual address space size. For a 4 KB page size, 54 * - level 0 supports virtual address spaces of widths 48 to 40 bits; 55 * - level 1 from 39 to 31; 56 * - level 2 from 30 to 25. 57 * 58 * Wider or narrower address spaces are not supported. As a result, level 3 59 * cannot be used as initial lookup level with 4 KB granularity. See section 60 * D4.2.5 in the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more 61 * information. 62 * 63 * For example, for a 35-bit address space (i.e. virt_addr_space_size == 64 * 1 << 35), TCR.TxSZ will be programmed to (64 - 35) = 29. According to Table 65 * D4-11 in the ARM ARM, the initial lookup level for an address space like that 66 * is 1. 67 * 68 * Note that this macro assumes that the given virtual address space size is 69 * valid. Therefore, the caller is expected to check it is the case using the 70 * CHECK_VIRT_ADDR_SPACE_SIZE() macro first. 71 */ 72 #define GET_XLAT_TABLE_LEVEL_BASE(virt_addr_space_size) \ 73 (((virt_addr_space_size) > (ULL(1) << L0_XLAT_ADDRESS_SHIFT)) \ 74 ? 0 \ 75 : (((virt_addr_space_size) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) \ 76 ? 1 : 2)) 77 78 #endif /* __XLAT_TABLES_AARCH64_H__ */ 79