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1 /*
2  * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 
9 #include <platform_def.h>
10 
11 #include <arch.h>
12 #include <bl1/bl1.h>
13 #include <common/bl_common.h>
14 #include <lib/utils.h>
15 #include <lib/xlat_tables/xlat_tables_compat.h>
16 #include <plat/arm/common/plat_arm.h>
17 #include <plat/common/platform.h>
18 
19 /* Weak definitions may be overridden in specific ARM standard platform */
20 #pragma weak bl1_early_platform_setup
21 #pragma weak bl1_plat_arch_setup
22 #pragma weak bl1_plat_sec_mem_layout
23 #pragma weak bl1_plat_prepare_exit
24 #pragma weak bl1_plat_get_next_image_id
25 #pragma weak plat_arm_bl1_fwu_needed
26 
27 #define MAP_BL1_TOTAL		MAP_REGION_FLAT(			\
28 					bl1_tzram_layout.total_base,	\
29 					bl1_tzram_layout.total_size,	\
30 					MT_MEMORY | MT_RW | MT_SECURE)
31 /*
32  * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
33  * otherwise one region is defined containing both
34  */
35 #if SEPARATE_CODE_AND_RODATA
36 #define MAP_BL1_RO		MAP_REGION_FLAT(			\
37 					BL_CODE_BASE,			\
38 					BL1_CODE_END - BL_CODE_BASE,	\
39 					MT_CODE | MT_SECURE),		\
40 				MAP_REGION_FLAT(			\
41 					BL1_RO_DATA_BASE,		\
42 					BL1_RO_DATA_END			\
43 						- BL_RO_DATA_BASE,	\
44 					MT_RO_DATA | MT_SECURE)
45 #else
46 #define MAP_BL1_RO		MAP_REGION_FLAT(			\
47 					BL_CODE_BASE,			\
48 					BL1_CODE_END - BL_CODE_BASE,	\
49 					MT_CODE | MT_SECURE)
50 #endif
51 
52 /* Data structure which holds the extents of the trusted SRAM for BL1*/
53 static meminfo_t bl1_tzram_layout;
54 
bl1_plat_sec_mem_layout(void)55 struct meminfo *bl1_plat_sec_mem_layout(void)
56 {
57 	return &bl1_tzram_layout;
58 }
59 
60 /*******************************************************************************
61  * BL1 specific platform actions shared between ARM standard platforms.
62  ******************************************************************************/
arm_bl1_early_platform_setup(void)63 void arm_bl1_early_platform_setup(void)
64 {
65 
66 #if !ARM_DISABLE_TRUSTED_WDOG
67 	/* Enable watchdog */
68 	plat_arm_secure_wdt_start();
69 #endif
70 
71 	/* Initialize the console to provide early debug support */
72 	arm_console_boot_init();
73 
74 	/* Allow BL1 to see the whole Trusted RAM */
75 	bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
76 	bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
77 }
78 
bl1_early_platform_setup(void)79 void bl1_early_platform_setup(void)
80 {
81 	arm_bl1_early_platform_setup();
82 
83 	/*
84 	 * Initialize Interconnect for this cluster during cold boot.
85 	 * No need for locks as no other CPU is active.
86 	 */
87 	plat_arm_interconnect_init();
88 	/*
89 	 * Enable Interconnect coherency for the primary CPU's cluster.
90 	 */
91 	plat_arm_interconnect_enter_coherency();
92 }
93 
94 /******************************************************************************
95  * Perform the very early platform specific architecture setup shared between
96  * ARM standard platforms. This only does basic initialization. Later
97  * architectural setup (bl1_arch_setup()) does not do anything platform
98  * specific.
99  *****************************************************************************/
arm_bl1_plat_arch_setup(void)100 void arm_bl1_plat_arch_setup(void)
101 {
102 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
103 	/*
104 	 * Ensure ARM platforms don't use coherent memory in BL1 unless
105 	 * cryptocell integration is enabled.
106 	 */
107 	assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
108 #endif
109 
110 	const mmap_region_t bl_regions[] = {
111 		MAP_BL1_TOTAL,
112 		MAP_BL1_RO,
113 #if USE_ROMLIB
114 		ARM_MAP_ROMLIB_CODE,
115 		ARM_MAP_ROMLIB_DATA,
116 #endif
117 #if ARM_CRYPTOCELL_INTEG
118 		ARM_MAP_BL_COHERENT_RAM,
119 #endif
120 		{0}
121 	};
122 
123 	setup_page_tables(bl_regions, plat_arm_get_mmap());
124 #ifdef __aarch64__
125 	enable_mmu_el3(0);
126 #else
127 	enable_mmu_svc_mon(0);
128 #endif /* __aarch64__ */
129 
130 	arm_setup_romlib();
131 }
132 
bl1_plat_arch_setup(void)133 void bl1_plat_arch_setup(void)
134 {
135 	arm_bl1_plat_arch_setup();
136 }
137 
138 /*
139  * Perform the platform specific architecture setup shared between
140  * ARM standard platforms.
141  */
arm_bl1_platform_setup(void)142 void arm_bl1_platform_setup(void)
143 {
144 	/* Initialise the IO layer and register platform IO devices */
145 	plat_arm_io_setup();
146 	arm_load_tb_fw_config();
147 #if TRUSTED_BOARD_BOOT
148 	/* Share the Mbed TLS heap info with other images */
149 	arm_bl1_set_mbedtls_heap();
150 #endif /* TRUSTED_BOARD_BOOT */
151 
152 	/*
153 	 * Allow access to the System counter timer module and program
154 	 * counter frequency for non secure images during FWU
155 	 */
156 #ifdef ARM_SYS_TIMCTL_BASE
157 	arm_configure_sys_timer();
158 #endif
159 #if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
160 	write_cntfrq_el0(plat_get_syscnt_freq2());
161 #endif
162 }
163 
bl1_plat_prepare_exit(entry_point_info_t * ep_info)164 void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
165 {
166 #if !ARM_DISABLE_TRUSTED_WDOG
167 	/* Disable watchdog before leaving BL1 */
168 	plat_arm_secure_wdt_stop();
169 #endif
170 
171 #ifdef EL3_PAYLOAD_BASE
172 	/*
173 	 * Program the EL3 payload's entry point address into the CPUs mailbox
174 	 * in order to release secondary CPUs from their holding pen and make
175 	 * them jump there.
176 	 */
177 	plat_arm_program_trusted_mailbox(ep_info->pc);
178 	dsbsy();
179 	sev();
180 #endif
181 }
182 
183 /*
184  * On Arm platforms, the FWU process is triggered when the FIP image has
185  * been tampered with.
186  */
plat_arm_bl1_fwu_needed(void)187 int plat_arm_bl1_fwu_needed(void)
188 {
189 	return (arm_io_is_toc_valid() != 1);
190 }
191 
192 /*******************************************************************************
193  * The following function checks if Firmware update is needed,
194  * by checking if TOC in FIP image is valid or not.
195  ******************************************************************************/
bl1_plat_get_next_image_id(void)196 unsigned int bl1_plat_get_next_image_id(void)
197 {
198 	if (plat_arm_bl1_fwu_needed() != 0)
199 		return NS_BL1U_IMAGE_ID;
200 
201 	return BL2_IMAGE_ID;
202 }
203