1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 5 */ 6 7 #ifndef _SYS_PROTO_H_ 8 #define _SYS_PROTO_H_ 9 10 #include <asm/io.h> 11 #include <asm/mach-imx/regs-common.h> 12 #include <common.h> 13 #include "../arch-imx/cpu.h" 14 15 #define soc_rev() (get_cpu_rev() & 0xFF) 16 #define is_soc_rev(rev) (soc_rev() == rev) 17 18 /* returns MXC_CPU_ value */ 19 #define cpu_type(rev) (((rev) >> 12) & 0xff) 20 #define soc_type(rev) (((rev) >> 12) & 0xf0) 21 /* both macros return/take MXC_CPU_ constants */ 22 #define get_cpu_type() (cpu_type(get_cpu_rev())) 23 #define get_soc_type() (soc_type(get_cpu_rev())) 24 #define is_cpu_type(cpu) (get_cpu_type() == cpu) 25 #define is_soc_type(soc) (get_soc_type() == soc) 26 27 #define is_mx6() (is_soc_type(MXC_SOC_MX6)) 28 #define is_mx7() (is_soc_type(MXC_SOC_MX7)) 29 #define is_imx8m() (is_soc_type(MXC_SOC_IMX8M)) 30 #define is_imx8() (is_soc_type(MXC_SOC_IMX8)) 31 32 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) 33 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) 34 #define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL)) 35 #define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL)) 36 #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX)) 37 #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL)) 38 #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO)) 39 #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL)) 40 #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL)) 41 #define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ)) 42 #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL)) 43 44 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) 45 46 #define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ)) 47 #define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM)) 48 #define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\ 49 is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \ 50 is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL)) 51 #define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML)) 52 #define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD)) 53 #define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL)) 54 #define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS)) 55 #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL)) 56 #define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN)) 57 58 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) 59 60 #ifdef CONFIG_MX6 61 #define IMX6_SRC_GPR10_BMODE BIT(28) 62 63 #define IMX6_BMODE_MASK GENMASK(7, 0) 64 #define IMX6_BMODE_SHIFT 4 65 #define IMX6_BMODE_EMI_MASK BIT(3) 66 #define IMX6_BMODE_EMI_SHIFT 3 67 #define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24) 68 #define IMX6_BMODE_SERIAL_ROM_SHIFT 24 69 70 enum imx6_bmode_serial_rom { 71 IMX6_BMODE_ECSPI1, 72 IMX6_BMODE_ECSPI2, 73 IMX6_BMODE_ECSPI3, 74 IMX6_BMODE_ECSPI4, 75 IMX6_BMODE_ECSPI5, 76 IMX6_BMODE_I2C1, 77 IMX6_BMODE_I2C2, 78 IMX6_BMODE_I2C3, 79 }; 80 81 enum imx6_bmode_emi { 82 IMX6_BMODE_NOR, 83 IMX6_BMODE_ONENAND, 84 }; 85 86 enum imx6_bmode { 87 IMX6_BMODE_EMI, 88 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) 89 IMX6_BMODE_QSPI, 90 IMX6_BMODE_RESERVED, 91 #else 92 IMX6_BMODE_RESERVED, 93 IMX6_BMODE_SATA, 94 #endif 95 IMX6_BMODE_SERIAL_ROM, 96 IMX6_BMODE_SD, 97 IMX6_BMODE_ESD, 98 IMX6_BMODE_MMC, 99 IMX6_BMODE_EMMC, 100 IMX6_BMODE_NAND_MIN, 101 IMX6_BMODE_NAND_MAX = 0xf, 102 }; 103 104 u32 imx6_src_get_boot_mode(void); 105 void gpr_init(void); 106 107 #endif /* CONFIG_MX6 */ 108 109 #ifdef CONFIG_IMX8M 110 struct rom_api { 111 u16 ver; 112 u16 tag; 113 u32 reserved1; 114 u32 (*download_image)(u8 *dest, u32 offset, u32 size, u32 xor); 115 u32 (*query_boot_infor)(u32 info_type, u32 *info, u32 xor); 116 }; 117 118 enum boot_dev_type_e { 119 BT_DEV_TYPE_SD = 1, 120 BT_DEV_TYPE_MMC = 2, 121 BT_DEV_TYPE_NAND = 3, 122 BT_DEV_TYPE_FLEXSPINOR = 4, 123 124 BT_DEV_TYPE_USB = 0xE, 125 BT_DEV_TYPE_MEM_DEV = 0xF, 126 127 BT_DEV_TYPE_INVALID = 0xFF 128 }; 129 130 #define QUERY_ROM_VER 1 131 #define QUERY_BT_DEV 2 132 #define QUERY_PAGE_SZ 3 133 #define QUERY_IVT_OFF 4 134 #define QUERY_BT_STAGE 5 135 #define QUERY_IMG_OFF 6 136 137 #define ROM_API_OKAY 0xF0 138 139 extern struct rom_api *g_rom_api; 140 #endif 141 142 u32 get_nr_cpus(void); 143 u32 get_cpu_rev(void); 144 u32 get_cpu_speed_grade_hz(void); 145 u32 get_cpu_temp_grade(int *minc, int *maxc); 146 const char *get_imx_type(u32 imxtype); 147 u32 imx_ddr_size(void); 148 void sdelay(unsigned long); 149 void set_chipselect_size(int const); 150 151 void init_aips(void); 152 void init_src(void); 153 void init_snvs(void); 154 void imx_wdog_disable_powerdown(void); 155 156 int arch_auxiliary_core_check_up(u32 core_id); 157 158 int board_mmc_get_env_dev(int devno); 159 160 int nxp_board_rev(void); 161 char nxp_board_rev_string(void); 162 163 /* 164 * Initializes on-chip ethernet controllers. 165 * to override, implement board_eth_init() 166 */ 167 int fecmxc_initialize(bd_t *bis); 168 u32 get_ahb_clk(void); 169 u32 get_periph_clk(void); 170 171 void lcdif_power_down(void); 172 173 int mxs_reset_block(struct mxs_register_32 *reg); 174 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout); 175 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout); 176 177 unsigned long call_imx_sip(unsigned long id, unsigned long reg0, 178 unsigned long reg1, unsigned long reg2, 179 unsigned long reg3); 180 unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0, 181 unsigned long *reg1, unsigned long reg2, 182 unsigned long reg3); 183 #endif 184