1/* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <arch.h> 10#include <asm_macros.S> 11#include <bl31/ea_handle.h> 12#include <bl31/interrupt_mgmt.h> 13#include <common/runtime_svc.h> 14#include <context.h> 15#include <lib/el3_runtime/cpu_data.h> 16#include <lib/smccc.h> 17 18 .globl runtime_exceptions 19 20 .globl sync_exception_sp_el0 21 .globl irq_sp_el0 22 .globl fiq_sp_el0 23 .globl serror_sp_el0 24 25 .globl sync_exception_sp_elx 26 .globl irq_sp_elx 27 .globl fiq_sp_elx 28 .globl serror_sp_elx 29 30 .globl sync_exception_aarch64 31 .globl irq_aarch64 32 .globl fiq_aarch64 33 .globl serror_aarch64 34 35 .globl sync_exception_aarch32 36 .globl irq_aarch32 37 .globl fiq_aarch32 38 .globl serror_aarch32 39 40 /* 41 * Macro that prepares entry to EL3 upon taking an exception. 42 * 43 * With RAS_EXTENSION, this macro synchronizes pending errors with an ESB 44 * instruction. When an error is thus synchronized, the handling is 45 * delegated to platform EA handler. 46 * 47 * Without RAS_EXTENSION, this macro just saves x30, and unmasks 48 * Asynchronous External Aborts. 49 */ 50 .macro check_and_unmask_ea 51#if RAS_EXTENSION 52 /* Synchronize pending External Aborts */ 53 esb 54 55 /* Unmask the SError interrupt */ 56 msr daifclr, #DAIF_ABT_BIT 57 58 /* 59 * Explicitly save x30 so as to free up a register and to enable 60 * branching 61 */ 62 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 63 64 /* Check for SErrors synchronized by the ESB instruction */ 65 mrs x30, DISR_EL1 66 tbz x30, #DISR_A_BIT, 1f 67 68 /* 69 * Save general purpose and ARMv8.3-PAuth registers (if enabled). 70 * If Secure Cycle Counter is not disabled in MDCR_EL3 when 71 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. 72 */ 73 bl save_gp_pmcr_pauth_regs 74 75 bl handle_lower_el_ea_esb 76 77 /* Restore general purpose, PMCR_EL0 and ARMv8.3-PAuth registers */ 78 bl restore_gp_pmcr_pauth_regs 791: 80#else 81 /* Unmask the SError interrupt */ 82 msr daifclr, #DAIF_ABT_BIT 83 84 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 85#endif 86 .endm 87 88 /* --------------------------------------------------------------------- 89 * This macro handles Synchronous exceptions. 90 * Only SMC exceptions are supported. 91 * --------------------------------------------------------------------- 92 */ 93 .macro handle_sync_exception 94#if ENABLE_RUNTIME_INSTRUMENTATION 95 /* 96 * Read the timestamp value and store it in per-cpu data. The value 97 * will be extracted from per-cpu data by the C level SMC handler and 98 * saved to the PMF timestamp region. 99 */ 100 mrs x30, cntpct_el0 101 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 102 mrs x29, tpidr_el3 103 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET] 104 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 105#endif 106 107 mrs x30, esr_el3 108 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 109 110 /* Handle SMC exceptions separately from other synchronous exceptions */ 111 cmp x30, #EC_AARCH32_SMC 112 b.eq smc_handler32 113 114 cmp x30, #EC_AARCH64_SMC 115 b.eq smc_handler64 116 117 /* Synchronous exceptions other than the above are assumed to be EA */ 118 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 119 b enter_lower_el_sync_ea 120 .endm 121 122 123 /* --------------------------------------------------------------------- 124 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS 125 * interrupts. 126 * --------------------------------------------------------------------- 127 */ 128 .macro handle_interrupt_exception label 129 130 /* 131 * Save general purpose and ARMv8.3-PAuth registers (if enabled). 132 * If Secure Cycle Counter is not disabled in MDCR_EL3 when 133 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. 134 */ 135 bl save_gp_pmcr_pauth_regs 136 137#if ENABLE_PAUTH 138 /* Load and program APIAKey firmware key */ 139 bl pauth_load_bl31_apiakey 140#endif 141 142 /* Save the EL3 system registers needed to return from this exception */ 143 mrs x0, spsr_el3 144 mrs x1, elr_el3 145 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 146 147 /* Switch to the runtime stack i.e. SP_EL0 */ 148 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 149 mov x20, sp 150 msr spsel, #MODE_SP_EL0 151 mov sp, x2 152 153 /* 154 * Find out whether this is a valid interrupt type. 155 * If the interrupt controller reports a spurious interrupt then return 156 * to where we came from. 157 */ 158 bl plat_ic_get_pending_interrupt_type 159 cmp x0, #INTR_TYPE_INVAL 160 b.eq interrupt_exit_\label 161 162 /* 163 * Get the registered handler for this interrupt type. 164 * A NULL return value could be 'cause of the following conditions: 165 * 166 * a. An interrupt of a type was routed correctly but a handler for its 167 * type was not registered. 168 * 169 * b. An interrupt of a type was not routed correctly so a handler for 170 * its type was not registered. 171 * 172 * c. An interrupt of a type was routed correctly to EL3, but was 173 * deasserted before its pending state could be read. Another 174 * interrupt of a different type pended at the same time and its 175 * type was reported as pending instead. However, a handler for this 176 * type was not registered. 177 * 178 * a. and b. can only happen due to a programming error. The 179 * occurrence of c. could be beyond the control of Trusted Firmware. 180 * It makes sense to return from this exception instead of reporting an 181 * error. 182 */ 183 bl get_interrupt_type_handler 184 cbz x0, interrupt_exit_\label 185 mov x21, x0 186 187 mov x0, #INTR_ID_UNAVAILABLE 188 189 /* Set the current security state in the 'flags' parameter */ 190 mrs x2, scr_el3 191 ubfx x1, x2, #0, #1 192 193 /* Restore the reference to the 'handle' i.e. SP_EL3 */ 194 mov x2, x20 195 196 /* x3 will point to a cookie (not used now) */ 197 mov x3, xzr 198 199 /* Call the interrupt type handler */ 200 blr x21 201 202interrupt_exit_\label: 203 /* Return from exception, possibly in a different security state */ 204 b el3_exit 205 206 .endm 207 208 209vector_base runtime_exceptions 210 211 /* --------------------------------------------------------------------- 212 * Current EL with SP_EL0 : 0x0 - 0x200 213 * --------------------------------------------------------------------- 214 */ 215vector_entry sync_exception_sp_el0 216#ifdef MONITOR_TRAPS 217 stp x29, x30, [sp, #-16]! 218 219 mrs x30, esr_el3 220 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 221 222 /* Check for BRK */ 223 cmp x30, #EC_BRK 224 b.eq brk_handler 225 226 ldp x29, x30, [sp], #16 227#endif /* MONITOR_TRAPS */ 228 229 /* We don't expect any synchronous exceptions from EL3 */ 230 b report_unhandled_exception 231end_vector_entry sync_exception_sp_el0 232 233vector_entry irq_sp_el0 234 /* 235 * EL3 code is non-reentrant. Any asynchronous exception is a serious 236 * error. Loop infinitely. 237 */ 238 b report_unhandled_interrupt 239end_vector_entry irq_sp_el0 240 241 242vector_entry fiq_sp_el0 243 b report_unhandled_interrupt 244end_vector_entry fiq_sp_el0 245 246 247vector_entry serror_sp_el0 248 no_ret plat_handle_el3_ea 249end_vector_entry serror_sp_el0 250 251 /* --------------------------------------------------------------------- 252 * Current EL with SP_ELx: 0x200 - 0x400 253 * --------------------------------------------------------------------- 254 */ 255vector_entry sync_exception_sp_elx 256 /* 257 * This exception will trigger if anything went wrong during a previous 258 * exception entry or exit or while handling an earlier unexpected 259 * synchronous exception. There is a high probability that SP_EL3 is 260 * corrupted. 261 */ 262 b report_unhandled_exception 263end_vector_entry sync_exception_sp_elx 264 265vector_entry irq_sp_elx 266 b report_unhandled_interrupt 267end_vector_entry irq_sp_elx 268 269vector_entry fiq_sp_elx 270 b report_unhandled_interrupt 271end_vector_entry fiq_sp_elx 272 273vector_entry serror_sp_elx 274 no_ret plat_handle_el3_ea 275end_vector_entry serror_sp_elx 276 277 /* --------------------------------------------------------------------- 278 * Lower EL using AArch64 : 0x400 - 0x600 279 * --------------------------------------------------------------------- 280 */ 281vector_entry sync_exception_aarch64 282 /* 283 * This exception vector will be the entry point for SMCs and traps 284 * that are unhandled at lower ELs most commonly. SP_EL3 should point 285 * to a valid cpu context where the general purpose and system register 286 * state can be saved. 287 */ 288 check_and_unmask_ea 289 handle_sync_exception 290end_vector_entry sync_exception_aarch64 291 292vector_entry irq_aarch64 293 check_and_unmask_ea 294 handle_interrupt_exception irq_aarch64 295end_vector_entry irq_aarch64 296 297vector_entry fiq_aarch64 298 check_and_unmask_ea 299 handle_interrupt_exception fiq_aarch64 300end_vector_entry fiq_aarch64 301 302vector_entry serror_aarch64 303 msr daifclr, #DAIF_ABT_BIT 304 b enter_lower_el_async_ea 305end_vector_entry serror_aarch64 306 307 /* --------------------------------------------------------------------- 308 * Lower EL using AArch32 : 0x600 - 0x800 309 * --------------------------------------------------------------------- 310 */ 311vector_entry sync_exception_aarch32 312 /* 313 * This exception vector will be the entry point for SMCs and traps 314 * that are unhandled at lower ELs most commonly. SP_EL3 should point 315 * to a valid cpu context where the general purpose and system register 316 * state can be saved. 317 */ 318 check_and_unmask_ea 319 handle_sync_exception 320end_vector_entry sync_exception_aarch32 321 322vector_entry irq_aarch32 323 check_and_unmask_ea 324 handle_interrupt_exception irq_aarch32 325end_vector_entry irq_aarch32 326 327vector_entry fiq_aarch32 328 check_and_unmask_ea 329 handle_interrupt_exception fiq_aarch32 330end_vector_entry fiq_aarch32 331 332vector_entry serror_aarch32 333 msr daifclr, #DAIF_ABT_BIT 334 b enter_lower_el_async_ea 335end_vector_entry serror_aarch32 336 337#ifdef MONITOR_TRAPS 338 .section .rodata.brk_string, "aS" 339brk_location: 340 .asciz "Error at instruction 0x" 341brk_message: 342 .asciz "Unexpected BRK instruction with value 0x" 343#endif /* MONITOR_TRAPS */ 344 345 /* --------------------------------------------------------------------- 346 * The following code handles secure monitor calls. 347 * Depending upon the execution state from where the SMC has been 348 * invoked, it frees some general purpose registers to perform the 349 * remaining tasks. They involve finding the runtime service handler 350 * that is the target of the SMC & switching to runtime stacks (SP_EL0) 351 * before calling the handler. 352 * 353 * Note that x30 has been explicitly saved and can be used here 354 * --------------------------------------------------------------------- 355 */ 356func smc_handler 357smc_handler32: 358 /* Check whether aarch32 issued an SMC64 */ 359 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited 360 361smc_handler64: 362 /* NOTE: The code below must preserve x0-x4 */ 363 364 /* 365 * Save general purpose and ARMv8.3-PAuth registers (if enabled). 366 * If Secure Cycle Counter is not disabled in MDCR_EL3 when 367 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter. 368 */ 369 bl save_gp_pmcr_pauth_regs 370 371#if ENABLE_PAUTH 372 /* Load and program APIAKey firmware key */ 373 bl pauth_load_bl31_apiakey 374#endif 375 376 /* 377 * Populate the parameters for the SMC handler. 378 * We already have x0-x4 in place. x5 will point to a cookie (not used 379 * now). x6 will point to the context structure (SP_EL3) and x7 will 380 * contain flags we need to pass to the handler. 381 */ 382 mov x5, xzr 383 mov x6, sp 384 385 /* 386 * Restore the saved C runtime stack value which will become the new 387 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' 388 * structure prior to the last ERET from EL3. 389 */ 390 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 391 392 /* Switch to SP_EL0 */ 393 msr spsel, #MODE_SP_EL0 394 395 /* 396 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world 397 * switch during SMC handling. 398 * TODO: Revisit if all system registers can be saved later. 399 */ 400 mrs x16, spsr_el3 401 mrs x17, elr_el3 402 mrs x18, scr_el3 403 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 404 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 405 406 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 407 bfi x7, x18, #0, #1 408 409 mov sp, x12 410 411 /* Get the unique owning entity number */ 412 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH 413 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH 414 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH 415 416 /* Load descriptor index from array of indices */ 417 adr x14, rt_svc_descs_indices 418 ldrb w15, [x14, x16] 419 420 /* Any index greater than 127 is invalid. Check bit 7. */ 421 tbnz w15, 7, smc_unknown 422 423 /* 424 * Get the descriptor using the index 425 * x11 = (base + off), w15 = index 426 * 427 * handler = (base + off) + (index << log2(size)) 428 */ 429 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) 430 lsl w10, w15, #RT_SVC_SIZE_LOG2 431 ldr x15, [x11, w10, uxtw] 432 433 /* 434 * Call the Secure Monitor Call handler and then drop directly into 435 * el3_exit() which will program any remaining architectural state 436 * prior to issuing the ERET to the desired lower EL. 437 */ 438#if DEBUG 439 cbz x15, rt_svc_fw_critical_error 440#endif 441 blr x15 442 443 b el3_exit 444 445smc_unknown: 446 /* 447 * Unknown SMC call. Populate return value with SMC_UNK and call 448 * el3_exit() which will restore the remaining architectural state 449 * i.e., SYS, GP and PAuth registers(if any) prior to issuing the ERET 450 * to the desired lower EL. 451 */ 452 mov x0, #SMC_UNK 453 str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 454 b el3_exit 455 456smc_prohibited: 457 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 458 mov x0, #SMC_UNK 459 exception_return 460 461#if DEBUG 462rt_svc_fw_critical_error: 463 /* Switch to SP_ELx */ 464 msr spsel, #MODE_SP_ELX 465 no_ret report_unhandled_exception 466#endif 467endfunc smc_handler 468 469 /* --------------------------------------------------------------------- 470 * The following code handles exceptions caused by BRK instructions. 471 * Following a BRK instruction, the only real valid cause of action is 472 * to print some information and panic, as the code that caused it is 473 * likely in an inconsistent internal state. 474 * 475 * This is initially intended to be used in conjunction with 476 * __builtin_trap. 477 * --------------------------------------------------------------------- 478 */ 479#ifdef MONITOR_TRAPS 480func brk_handler 481 /* Extract the ISS */ 482 mrs x10, esr_el3 483 ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH 484 485 /* Ensure the console is initialized */ 486 bl plat_crash_console_init 487 488 adr x4, brk_location 489 bl asm_print_str 490 mrs x4, elr_el3 491 bl asm_print_hex 492 bl asm_print_newline 493 494 adr x4, brk_message 495 bl asm_print_str 496 mov x4, x10 497 mov x5, #28 498 bl asm_print_hex_bits 499 bl asm_print_newline 500 501 no_ret plat_panic_handler 502endfunc brk_handler 503#endif /* MONITOR_TRAPS */ 504