1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * (C) Copyright 2002-2006
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * (C) Copyright 2002
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Marius Groeger <mgroeger@sysgo.de>
10 */
11
12 #include <common.h>
13 #include <bloblist.h>
14 #include <console.h>
15 #include <cpu.h>
16 #include <cpu_func.h>
17 #include <dm.h>
18 #include <env.h>
19 #include <env_internal.h>
20 #include <fdtdec.h>
21 #include <fs.h>
22 #include <i2c.h>
23 #include <init.h>
24 #include <initcall.h>
25 #include <lcd.h>
26 #include <malloc.h>
27 #include <mapmem.h>
28 #include <os.h>
29 #include <post.h>
30 #include <relocate.h>
31 #include <serial.h>
32 #ifdef CONFIG_SPL
33 #include <spl.h>
34 #endif
35 #include <status_led.h>
36 #include <sysreset.h>
37 #include <timer.h>
38 #include <trace.h>
39 #include <video.h>
40 #include <watchdog.h>
41 #ifdef CONFIG_MACH_TYPE
42 #include <asm/mach-types.h>
43 #endif
44 #if defined(CONFIG_MP) && defined(CONFIG_PPC)
45 #include <asm/mp.h>
46 #endif
47 #include <asm/io.h>
48 #include <asm/sections.h>
49 #include <dm/root.h>
50 #include <linux/errno.h>
51
52 /*
53 * Pointer to initial global data area
54 *
55 * Here we initialize it if needed.
56 */
57 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
58 #undef XTRN_DECLARE_GLOBAL_DATA_PTR
59 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
60 DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
61 #else
62 DECLARE_GLOBAL_DATA_PTR;
63 #endif
64
65 /*
66 * TODO(sjg@chromium.org): IMO this code should be
67 * refactored to a single function, something like:
68 *
69 * void led_set_state(enum led_colour_t colour, int on);
70 */
71 /************************************************************************
72 * Coloured LED functionality
73 ************************************************************************
74 * May be supplied by boards if desired
75 */
coloured_LED_init(void)76 __weak void coloured_LED_init(void) {}
red_led_on(void)77 __weak void red_led_on(void) {}
red_led_off(void)78 __weak void red_led_off(void) {}
green_led_on(void)79 __weak void green_led_on(void) {}
green_led_off(void)80 __weak void green_led_off(void) {}
yellow_led_on(void)81 __weak void yellow_led_on(void) {}
yellow_led_off(void)82 __weak void yellow_led_off(void) {}
blue_led_on(void)83 __weak void blue_led_on(void) {}
blue_led_off(void)84 __weak void blue_led_off(void) {}
85
86 /*
87 * Why is gd allocated a register? Prior to reloc it might be better to
88 * just pass it around to each function in this file?
89 *
90 * After reloc one could argue that it is hardly used and doesn't need
91 * to be in a register. Or if it is it should perhaps hold pointers to all
92 * global data for all modules, so that post-reloc we can avoid the massive
93 * literal pool we get on ARM. Or perhaps just encourage each module to use
94 * a structure...
95 */
96
97 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
init_func_watchdog_init(void)98 static int init_func_watchdog_init(void)
99 {
100 # if defined(CONFIG_HW_WATCHDOG) && \
101 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
102 defined(CONFIG_SH) || \
103 defined(CONFIG_DESIGNWARE_WATCHDOG) || \
104 defined(CONFIG_IMX_WATCHDOG))
105 hw_watchdog_init();
106 puts(" Watchdog enabled\n");
107 # endif
108 WATCHDOG_RESET();
109
110 return 0;
111 }
112
init_func_watchdog_reset(void)113 int init_func_watchdog_reset(void)
114 {
115 WATCHDOG_RESET();
116
117 return 0;
118 }
119 #endif /* CONFIG_WATCHDOG */
120
board_add_ram_info(int use_default)121 __weak void board_add_ram_info(int use_default)
122 {
123 /* please define platform specific board_add_ram_info() */
124 }
125
init_baud_rate(void)126 static int init_baud_rate(void)
127 {
128 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
129 return 0;
130 }
131
display_text_info(void)132 static int display_text_info(void)
133 {
134 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
135 ulong bss_start, bss_end, text_base;
136
137 bss_start = (ulong)&__bss_start;
138 bss_end = (ulong)&__bss_end;
139
140 #ifdef CONFIG_SYS_TEXT_BASE
141 text_base = CONFIG_SYS_TEXT_BASE;
142 #else
143 text_base = CONFIG_SYS_MONITOR_BASE;
144 #endif
145
146 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
147 text_base, bss_start, bss_end);
148 #endif
149
150 return 0;
151 }
152
153 #ifdef CONFIG_SYSRESET
print_resetinfo(void)154 static int print_resetinfo(void)
155 {
156 struct udevice *dev;
157 char status[256];
158 int ret;
159
160 ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
161 if (ret) {
162 debug("%s: No sysreset device found (error: %d)\n",
163 __func__, ret);
164 /* Not all boards have sysreset drivers available during early
165 * boot, so don't fail if one can't be found.
166 */
167 return 0;
168 }
169
170 if (!sysreset_get_status(dev, status, sizeof(status)))
171 printf("%s", status);
172
173 return 0;
174 }
175 #endif
176
177 #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
print_cpuinfo(void)178 static int print_cpuinfo(void)
179 {
180 struct udevice *dev;
181 char desc[512];
182 int ret;
183
184 ret = uclass_first_device_err(UCLASS_CPU, &dev);
185 if (ret) {
186 debug("%s: Could not get CPU device (err = %d)\n",
187 __func__, ret);
188 return ret;
189 }
190
191 ret = cpu_get_desc(dev, desc, sizeof(desc));
192 if (ret) {
193 debug("%s: Could not get CPU description (err = %d)\n",
194 dev->name, ret);
195 return ret;
196 }
197
198 printf("CPU: %s\n", desc);
199
200 return 0;
201 }
202 #endif
203
announce_dram_init(void)204 static int announce_dram_init(void)
205 {
206 puts("DRAM: ");
207 return 0;
208 }
209
show_dram_config(void)210 static int show_dram_config(void)
211 {
212 unsigned long long size;
213
214 #ifdef CONFIG_NR_DRAM_BANKS
215 int i;
216
217 debug("\nRAM Configuration:\n");
218 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
219 size += gd->bd->bi_dram[i].size;
220 debug("Bank #%d: %llx ", i,
221 (unsigned long long)(gd->bd->bi_dram[i].start));
222 #ifdef DEBUG
223 print_size(gd->bd->bi_dram[i].size, "\n");
224 #endif
225 }
226 debug("\nDRAM: ");
227 #else
228 size = gd->ram_size;
229 #endif
230
231 print_size(size, "");
232 board_add_ram_info(0);
233 putc('\n');
234
235 return 0;
236 }
237
dram_init_banksize(void)238 __weak int dram_init_banksize(void)
239 {
240 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
241 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
242 gd->bd->bi_dram[0].size = get_effective_memsize();
243 #endif
244
245 return 0;
246 }
247
248 #if defined(CONFIG_SYS_I2C)
init_func_i2c(void)249 static int init_func_i2c(void)
250 {
251 puts("I2C: ");
252 #ifdef CONFIG_SYS_I2C
253 i2c_init_all();
254 #else
255 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
256 #endif
257 puts("ready\n");
258 return 0;
259 }
260 #endif
261
262 #if defined(CONFIG_VID)
init_func_vid(void)263 __weak int init_func_vid(void)
264 {
265 return 0;
266 }
267 #endif
268
setup_mon_len(void)269 static int setup_mon_len(void)
270 {
271 #if defined(__ARM__) || defined(__MICROBLAZE__)
272 gd->mon_len = (ulong)&__bss_end - (ulong)_start;
273 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
274 gd->mon_len = (ulong)&_end - (ulong)_init;
275 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
276 gd->mon_len = CONFIG_SYS_MONITOR_LEN;
277 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
278 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
279 #elif defined(CONFIG_SYS_MONITOR_BASE)
280 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
281 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
282 #endif
283 return 0;
284 }
285
setup_spl_handoff(void)286 static int setup_spl_handoff(void)
287 {
288 #if CONFIG_IS_ENABLED(HANDOFF)
289 gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF,
290 sizeof(struct spl_handoff));
291 debug("Found SPL hand-off info %p\n", gd->spl_handoff);
292 #endif
293
294 return 0;
295 }
296
arch_cpu_init(void)297 __weak int arch_cpu_init(void)
298 {
299 return 0;
300 }
301
mach_cpu_init(void)302 __weak int mach_cpu_init(void)
303 {
304 return 0;
305 }
306
307 /* Get the top of usable RAM */
board_get_usable_ram_top(ulong total_size)308 __weak ulong board_get_usable_ram_top(ulong total_size)
309 {
310 #ifdef CONFIG_SYS_SDRAM_BASE
311 /*
312 * Detect whether we have so much RAM that it goes past the end of our
313 * 32-bit address space. If so, clip the usable RAM so it doesn't.
314 */
315 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
316 /*
317 * Will wrap back to top of 32-bit space when reservations
318 * are made.
319 */
320 return 0;
321 #endif
322 return gd->ram_top;
323 }
324
setup_dest_addr(void)325 static int setup_dest_addr(void)
326 {
327 debug("Monitor len: %08lX\n", gd->mon_len);
328 /*
329 * Ram is setup, size stored in gd !!
330 */
331 debug("Ram size: %08lX\n", (ulong)gd->ram_size);
332 #if defined(CONFIG_SYS_MEM_TOP_HIDE)
333 /*
334 * Subtract specified amount of memory to hide so that it won't
335 * get "touched" at all by U-Boot. By fixing up gd->ram_size
336 * the Linux kernel should now get passed the now "corrected"
337 * memory size and won't touch it either. This should work
338 * for arch/ppc and arch/powerpc. Only Linux board ports in
339 * arch/powerpc with bootwrapper support, that recalculate the
340 * memory size from the SDRAM controller setup will have to
341 * get fixed.
342 */
343 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
344 #endif
345 #ifdef CONFIG_SYS_SDRAM_BASE
346 gd->ram_base = CONFIG_SYS_SDRAM_BASE;
347 #endif
348 gd->ram_top = gd->ram_base + get_effective_memsize();
349 gd->ram_top = board_get_usable_ram_top(gd->mon_len);
350 gd->relocaddr = gd->ram_top;
351 debug("Ram top: %08lX\n", (ulong)gd->ram_top);
352 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
353 /*
354 * We need to make sure the location we intend to put secondary core
355 * boot code is reserved and not used by any part of u-boot
356 */
357 if (gd->relocaddr > determine_mp_bootpg(NULL)) {
358 gd->relocaddr = determine_mp_bootpg(NULL);
359 debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
360 }
361 #endif
362 return 0;
363 }
364
365 #ifdef CONFIG_PRAM
366 /* reserve protected RAM */
reserve_pram(void)367 static int reserve_pram(void)
368 {
369 ulong reg;
370
371 reg = env_get_ulong("pram", 10, CONFIG_PRAM);
372 gd->relocaddr -= (reg << 10); /* size is in kB */
373 debug("Reserving %ldk for protected RAM at %08lx\n", reg,
374 gd->relocaddr);
375 return 0;
376 }
377 #endif /* CONFIG_PRAM */
378
379 /* Round memory pointer down to next 4 kB limit */
reserve_round_4k(void)380 static int reserve_round_4k(void)
381 {
382 gd->relocaddr &= ~(4096 - 1);
383 return 0;
384 }
385
386 #ifdef CONFIG_ARM
reserve_mmu(void)387 __weak int reserve_mmu(void)
388 {
389 #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
390 /* reserve TLB table */
391 gd->arch.tlb_size = PGTABLE_SIZE;
392 gd->relocaddr -= gd->arch.tlb_size;
393
394 /* round down to next 64 kB limit */
395 gd->relocaddr &= ~(0x10000 - 1);
396
397 gd->arch.tlb_addr = gd->relocaddr;
398 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
399 gd->arch.tlb_addr + gd->arch.tlb_size);
400
401 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
402 /*
403 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
404 * with location within secure ram.
405 */
406 gd->arch.tlb_allocated = gd->arch.tlb_addr;
407 #endif
408 #endif
409
410 return 0;
411 }
412 #endif
413
reserve_video(void)414 static int reserve_video(void)
415 {
416 #ifdef CONFIG_DM_VIDEO
417 ulong addr;
418 int ret;
419
420 addr = gd->relocaddr;
421 ret = video_reserve(&addr);
422 if (ret)
423 return ret;
424 gd->relocaddr = addr;
425 #elif defined(CONFIG_LCD)
426 # ifdef CONFIG_FB_ADDR
427 gd->fb_base = CONFIG_FB_ADDR;
428 # else
429 /* reserve memory for LCD display (always full pages) */
430 gd->relocaddr = lcd_setmem(gd->relocaddr);
431 gd->fb_base = gd->relocaddr;
432 # endif /* CONFIG_FB_ADDR */
433 #endif
434
435 return 0;
436 }
437
reserve_trace(void)438 static int reserve_trace(void)
439 {
440 #ifdef CONFIG_TRACE
441 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
442 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
443 debug("Reserving %luk for trace data at: %08lx\n",
444 (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
445 #endif
446
447 return 0;
448 }
449
reserve_uboot(void)450 static int reserve_uboot(void)
451 {
452 if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
453 /*
454 * reserve memory for U-Boot code, data & bss
455 * round down to next 4 kB limit
456 */
457 gd->relocaddr -= gd->mon_len;
458 gd->relocaddr &= ~(4096 - 1);
459 #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
460 /* round down to next 64 kB limit so that IVPR stays aligned */
461 gd->relocaddr &= ~(65536 - 1);
462 #endif
463
464 debug("Reserving %ldk for U-Boot at: %08lx\n",
465 gd->mon_len >> 10, gd->relocaddr);
466 }
467
468 gd->start_addr_sp = gd->relocaddr;
469
470 return 0;
471 }
472
473 #ifdef CONFIG_SYS_NONCACHED_MEMORY
reserve_noncached(void)474 static int reserve_noncached(void)
475 {
476 /*
477 * The value of gd->start_addr_sp must match the value of malloc_start
478 * calculated in boatrd_f.c:initr_malloc(), which is passed to
479 * board_r.c:mem_malloc_init() and then used by
480 * cache.c:noncached_init()
481 *
482 * These calculations must match the code in cache.c:noncached_init()
483 */
484 gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) -
485 MMU_SECTION_SIZE;
486 gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY,
487 MMU_SECTION_SIZE);
488 debug("Reserving %dM for noncached_alloc() at: %08lx\n",
489 CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp);
490
491 return 0;
492 }
493 #endif
494
495 /* reserve memory for malloc() area */
reserve_malloc(void)496 static int reserve_malloc(void)
497 {
498 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
499 debug("Reserving %dk for malloc() at: %08lx\n",
500 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
501 #ifdef CONFIG_SYS_NONCACHED_MEMORY
502 reserve_noncached();
503 #endif
504
505 return 0;
506 }
507
508 /* (permanently) allocate a Board Info struct */
reserve_board(void)509 static int reserve_board(void)
510 {
511 if (!gd->bd) {
512 gd->start_addr_sp -= sizeof(bd_t);
513 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
514 memset(gd->bd, '\0', sizeof(bd_t));
515 debug("Reserving %zu Bytes for Board Info at: %08lx\n",
516 sizeof(bd_t), gd->start_addr_sp);
517 }
518 return 0;
519 }
520
setup_machine(void)521 static int setup_machine(void)
522 {
523 #ifdef CONFIG_MACH_TYPE
524 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
525 #endif
526 return 0;
527 }
528
reserve_global_data(void)529 static int reserve_global_data(void)
530 {
531 gd->start_addr_sp -= sizeof(gd_t);
532 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
533 debug("Reserving %zu Bytes for Global Data at: %08lx\n",
534 sizeof(gd_t), gd->start_addr_sp);
535 return 0;
536 }
537
reserve_fdt(void)538 static int reserve_fdt(void)
539 {
540 #ifndef CONFIG_OF_EMBED
541 /*
542 * If the device tree is sitting immediately above our image then we
543 * must relocate it. If it is embedded in the data section, then it
544 * will be relocated with other data.
545 */
546 if (gd->fdt_blob) {
547 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
548
549 gd->start_addr_sp -= gd->fdt_size;
550 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
551 debug("Reserving %lu Bytes for FDT at: %08lx\n",
552 gd->fdt_size, gd->start_addr_sp);
553 }
554 #endif
555
556 return 0;
557 }
558
reserve_bootstage(void)559 static int reserve_bootstage(void)
560 {
561 #ifdef CONFIG_BOOTSTAGE
562 int size = bootstage_get_size();
563
564 gd->start_addr_sp -= size;
565 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
566 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
567 gd->start_addr_sp);
568 #endif
569
570 return 0;
571 }
572
arch_reserve_stacks(void)573 __weak int arch_reserve_stacks(void)
574 {
575 return 0;
576 }
577
reserve_stacks(void)578 static int reserve_stacks(void)
579 {
580 /* make stack pointer 16-byte aligned */
581 gd->start_addr_sp -= 16;
582 gd->start_addr_sp &= ~0xf;
583
584 /*
585 * let the architecture-specific code tailor gd->start_addr_sp and
586 * gd->irq_sp
587 */
588 return arch_reserve_stacks();
589 }
590
reserve_bloblist(void)591 static int reserve_bloblist(void)
592 {
593 #ifdef CONFIG_BLOBLIST
594 gd->start_addr_sp &= ~0xf;
595 gd->start_addr_sp -= CONFIG_BLOBLIST_SIZE;
596 gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE);
597 #endif
598
599 return 0;
600 }
601
display_new_sp(void)602 static int display_new_sp(void)
603 {
604 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
605
606 return 0;
607 }
608
609 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
610 defined(CONFIG_SH)
setup_board_part1(void)611 static int setup_board_part1(void)
612 {
613 bd_t *bd = gd->bd;
614
615 /*
616 * Save local variables to board info struct
617 */
618 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
619 bd->bi_memsize = gd->ram_size; /* size in bytes */
620
621 #ifdef CONFIG_SYS_SRAM_BASE
622 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
623 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
624 #endif
625
626 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
627 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
628 #endif
629 #if defined(CONFIG_M68K)
630 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
631 #endif
632 #if defined(CONFIG_MPC83xx)
633 bd->bi_immrbar = CONFIG_SYS_IMMR;
634 #endif
635
636 return 0;
637 }
638 #endif
639
640 #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
setup_board_part2(void)641 static int setup_board_part2(void)
642 {
643 bd_t *bd = gd->bd;
644
645 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
646 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
647 #if defined(CONFIG_CPM2)
648 bd->bi_cpmfreq = gd->arch.cpm_clk;
649 bd->bi_brgfreq = gd->arch.brg_clk;
650 bd->bi_sccfreq = gd->arch.scc_clk;
651 bd->bi_vco = gd->arch.vco_out;
652 #endif /* CONFIG_CPM2 */
653 #if defined(CONFIG_M68K) && defined(CONFIG_PCI)
654 bd->bi_pcifreq = gd->pci_clk;
655 #endif
656 #if defined(CONFIG_EXTRA_CLOCK)
657 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
658 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
659 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
660 #endif
661
662 return 0;
663 }
664 #endif
665
666 #ifdef CONFIG_POST
init_post(void)667 static int init_post(void)
668 {
669 post_bootmode_init();
670 post_run(NULL, POST_ROM | post_bootmode_get(0));
671
672 return 0;
673 }
674 #endif
675
reloc_fdt(void)676 static int reloc_fdt(void)
677 {
678 #ifndef CONFIG_OF_EMBED
679 if (gd->flags & GD_FLG_SKIP_RELOC)
680 return 0;
681 if (gd->new_fdt) {
682 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
683 gd->fdt_blob = gd->new_fdt;
684 }
685 #endif
686
687 return 0;
688 }
689
reloc_bootstage(void)690 static int reloc_bootstage(void)
691 {
692 #ifdef CONFIG_BOOTSTAGE
693 if (gd->flags & GD_FLG_SKIP_RELOC)
694 return 0;
695 if (gd->new_bootstage) {
696 int size = bootstage_get_size();
697
698 debug("Copying bootstage from %p to %p, size %x\n",
699 gd->bootstage, gd->new_bootstage, size);
700 memcpy(gd->new_bootstage, gd->bootstage, size);
701 gd->bootstage = gd->new_bootstage;
702 bootstage_relocate();
703 }
704 #endif
705
706 return 0;
707 }
708
reloc_bloblist(void)709 static int reloc_bloblist(void)
710 {
711 #ifdef CONFIG_BLOBLIST
712 if (gd->flags & GD_FLG_SKIP_RELOC)
713 return 0;
714 if (gd->new_bloblist) {
715 int size = CONFIG_BLOBLIST_SIZE;
716
717 debug("Copying bloblist from %p to %p, size %x\n",
718 gd->bloblist, gd->new_bloblist, size);
719 memcpy(gd->new_bloblist, gd->bloblist, size);
720 gd->bloblist = gd->new_bloblist;
721 }
722 #endif
723
724 return 0;
725 }
726
setup_reloc(void)727 static int setup_reloc(void)
728 {
729 if (gd->flags & GD_FLG_SKIP_RELOC) {
730 debug("Skipping relocation due to flag\n");
731 return 0;
732 }
733
734 #ifdef CONFIG_SYS_TEXT_BASE
735 #ifdef ARM
736 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
737 #elif defined(CONFIG_M68K)
738 /*
739 * On all ColdFire arch cpu, monitor code starts always
740 * just after the default vector table location, so at 0x400
741 */
742 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
743 #elif !defined(CONFIG_SANDBOX)
744 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
745 #endif
746 #endif
747 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
748
749 debug("Relocation Offset is: %08lx\n", gd->reloc_off);
750 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
751 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
752 gd->start_addr_sp);
753
754 return 0;
755 }
756
757 #ifdef CONFIG_OF_BOARD_FIXUP
fix_fdt(void)758 static int fix_fdt(void)
759 {
760 return board_fix_fdt((void *)gd->fdt_blob);
761 }
762 #endif
763
764 /* ARM calls relocate_code from its crt0.S */
765 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
766 !CONFIG_IS_ENABLED(X86_64)
767
jump_to_copy(void)768 static int jump_to_copy(void)
769 {
770 if (gd->flags & GD_FLG_SKIP_RELOC)
771 return 0;
772 /*
773 * x86 is special, but in a nice way. It uses a trampoline which
774 * enables the dcache if possible.
775 *
776 * For now, other archs use relocate_code(), which is implemented
777 * similarly for all archs. When we do generic relocation, hopefully
778 * we can make all archs enable the dcache prior to relocation.
779 */
780 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
781 /*
782 * SDRAM and console are now initialised. The final stack can now
783 * be setup in SDRAM. Code execution will continue in Flash, but
784 * with the stack in SDRAM and Global Data in temporary memory
785 * (CPU cache)
786 */
787 arch_setup_gd(gd->new_gd);
788 board_init_f_r_trampoline(gd->start_addr_sp);
789 #else
790 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
791 #endif
792
793 return 0;
794 }
795 #endif
796
797 /* Record the board_init_f() bootstage (after arch_cpu_init()) */
initf_bootstage(void)798 static int initf_bootstage(void)
799 {
800 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
801 IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
802 int ret;
803
804 ret = bootstage_init(!from_spl);
805 if (ret)
806 return ret;
807 if (from_spl) {
808 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
809 CONFIG_BOOTSTAGE_STASH_SIZE);
810
811 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
812 if (ret && ret != -ENOENT) {
813 debug("Failed to unstash bootstage: err=%d\n", ret);
814 return ret;
815 }
816 }
817
818 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
819
820 return 0;
821 }
822
initf_console_record(void)823 static int initf_console_record(void)
824 {
825 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
826 return console_record_init();
827 #else
828 return 0;
829 #endif
830 }
831
initf_dm(void)832 static int initf_dm(void)
833 {
834 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
835 int ret;
836
837 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
838 ret = dm_init_and_scan(true);
839 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F);
840 if (ret)
841 return ret;
842 #endif
843 #ifdef CONFIG_TIMER_EARLY
844 ret = dm_timer_init();
845 if (ret)
846 return ret;
847 #endif
848
849 return 0;
850 }
851
852 /* Architecture-specific memory reservation */
reserve_arch(void)853 __weak int reserve_arch(void)
854 {
855 return 0;
856 }
857
arch_cpu_init_dm(void)858 __weak int arch_cpu_init_dm(void)
859 {
860 return 0;
861 }
862
863 static const init_fnc_t init_sequence_f[] = {
864 setup_mon_len,
865 #ifdef CONFIG_OF_CONTROL
866 fdtdec_setup,
867 #endif
868 #ifdef CONFIG_TRACE_EARLY
869 trace_early_init,
870 #endif
871 initf_malloc,
872 log_init,
873 initf_bootstage, /* uses its own timer, so does not need DM */
874 #ifdef CONFIG_BLOBLIST
875 bloblist_init,
876 #endif
877 setup_spl_handoff,
878 initf_console_record,
879 #if defined(CONFIG_HAVE_FSP)
880 arch_fsp_init,
881 #endif
882 arch_cpu_init, /* basic arch cpu dependent setup */
883 mach_cpu_init, /* SoC/machine dependent CPU setup */
884 initf_dm,
885 arch_cpu_init_dm,
886 #if defined(CONFIG_BOARD_EARLY_INIT_F)
887 board_early_init_f,
888 #endif
889 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
890 /* get CPU and bus clocks according to the environment variable */
891 get_clocks, /* get CPU and bus clocks (etc.) */
892 #endif
893 #if !defined(CONFIG_M68K)
894 timer_init, /* initialize timer */
895 #endif
896 #if defined(CONFIG_BOARD_POSTCLK_INIT)
897 board_postclk_init,
898 #endif
899 env_init, /* initialize environment */
900 init_baud_rate, /* initialze baudrate settings */
901 serial_init, /* serial communications setup */
902 console_init_f, /* stage 1 init of console */
903 display_options, /* say that we are here */
904 display_text_info, /* show debugging info if required */
905 #if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86)
906 checkcpu,
907 #endif
908 #if defined(CONFIG_SYSRESET)
909 print_resetinfo,
910 #endif
911 #if defined(CONFIG_DISPLAY_CPUINFO)
912 print_cpuinfo, /* display cpu info (and speed) */
913 #endif
914 #if defined(CONFIG_DTB_RESELECT)
915 embedded_dtb_select,
916 #endif
917 #if defined(CONFIG_DISPLAY_BOARDINFO)
918 show_board_info,
919 #endif
920 INIT_FUNC_WATCHDOG_INIT
921 #if defined(CONFIG_MISC_INIT_F)
922 misc_init_f,
923 #endif
924 INIT_FUNC_WATCHDOG_RESET
925 #if defined(CONFIG_SYS_I2C)
926 init_func_i2c,
927 #endif
928 #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
929 init_func_vid,
930 #endif
931 announce_dram_init,
932 dram_init, /* configure available RAM banks */
933 #ifdef CONFIG_POST
934 post_init_f,
935 #endif
936 INIT_FUNC_WATCHDOG_RESET
937 #if defined(CONFIG_SYS_DRAM_TEST)
938 testdram,
939 #endif /* CONFIG_SYS_DRAM_TEST */
940 INIT_FUNC_WATCHDOG_RESET
941
942 #ifdef CONFIG_POST
943 init_post,
944 #endif
945 INIT_FUNC_WATCHDOG_RESET
946 /*
947 * Now that we have DRAM mapped and working, we can
948 * relocate the code and continue running from DRAM.
949 *
950 * Reserve memory at end of RAM for (top down in that order):
951 * - area that won't get touched by U-Boot and Linux (optional)
952 * - kernel log buffer
953 * - protected RAM
954 * - LCD framebuffer
955 * - monitor code
956 * - board info struct
957 */
958 setup_dest_addr,
959 #ifdef CONFIG_PRAM
960 reserve_pram,
961 #endif
962 reserve_round_4k,
963 #ifdef CONFIG_ARM
964 reserve_mmu,
965 #endif
966 reserve_video,
967 reserve_trace,
968 reserve_uboot,
969 reserve_malloc,
970 reserve_board,
971 setup_machine,
972 reserve_global_data,
973 reserve_fdt,
974 reserve_bootstage,
975 reserve_bloblist,
976 reserve_arch,
977 reserve_stacks,
978 dram_init_banksize,
979 show_dram_config,
980 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
981 defined(CONFIG_SH)
982 setup_board_part1,
983 #endif
984 #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
985 INIT_FUNC_WATCHDOG_RESET
986 setup_board_part2,
987 #endif
988 display_new_sp,
989 #ifdef CONFIG_OF_BOARD_FIXUP
990 fix_fdt,
991 #endif
992 INIT_FUNC_WATCHDOG_RESET
993 reloc_fdt,
994 reloc_bootstage,
995 reloc_bloblist,
996 setup_reloc,
997 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
998 copy_uboot_to_ram,
999 do_elf_reloc_fixups,
1000 clear_bss,
1001 #endif
1002 #if defined(CONFIG_XTENSA)
1003 clear_bss,
1004 #endif
1005 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
1006 !CONFIG_IS_ENABLED(X86_64)
1007 jump_to_copy,
1008 #endif
1009 NULL,
1010 };
1011
board_init_f(ulong boot_flags)1012 void board_init_f(ulong boot_flags)
1013 {
1014 gd->flags = boot_flags;
1015 gd->have_console = 0;
1016
1017 if (initcall_run_list(init_sequence_f))
1018 hang();
1019
1020 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
1021 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
1022 !defined(CONFIG_ARC)
1023 /* NOTREACHED - jump_to_copy() does not return */
1024 hang();
1025 #endif
1026 }
1027
1028 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
1029 /*
1030 * For now this code is only used on x86.
1031 *
1032 * init_sequence_f_r is the list of init functions which are run when
1033 * U-Boot is executing from Flash with a semi-limited 'C' environment.
1034 * The following limitations must be considered when implementing an
1035 * '_f_r' function:
1036 * - 'static' variables are read-only
1037 * - Global Data (gd->xxx) is read/write
1038 *
1039 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
1040 * supported). It _should_, if possible, copy global data to RAM and
1041 * initialise the CPU caches (to speed up the relocation process)
1042 *
1043 * NOTE: At present only x86 uses this route, but it is intended that
1044 * all archs will move to this when generic relocation is implemented.
1045 */
1046 static const init_fnc_t init_sequence_f_r[] = {
1047 #if !CONFIG_IS_ENABLED(X86_64)
1048 init_cache_f_r,
1049 #endif
1050
1051 NULL,
1052 };
1053
board_init_f_r(void)1054 void board_init_f_r(void)
1055 {
1056 if (initcall_run_list(init_sequence_f_r))
1057 hang();
1058
1059 /*
1060 * The pre-relocation drivers may be using memory that has now gone
1061 * away. Mark serial as unavailable - this will fall back to the debug
1062 * UART if available.
1063 *
1064 * Do the same with log drivers since the memory may not be available.
1065 */
1066 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
1067 #ifdef CONFIG_TIMER
1068 gd->timer = NULL;
1069 #endif
1070
1071 /*
1072 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
1073 * Transfer execution from Flash to RAM by calculating the address
1074 * of the in-RAM copy of board_init_r() and calling it
1075 */
1076 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
1077
1078 /* NOTREACHED - board_init_r() does not return */
1079 hang();
1080 }
1081 #endif /* CONFIG_X86 */
1082