1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * boot-common.c
4 *
5 * Common bootmode functions for omap based boards
6 *
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 */
9
10 #include <common.h>
11 #include <ahci.h>
12 #include <spl.h>
13 #include <asm/omap_common.h>
14 #include <asm/arch/omap.h>
15 #include <asm/arch/mmc_host_def.h>
16 #include <asm/arch/sys_proto.h>
17 #include <watchdog.h>
18 #include <scsi.h>
19 #include <i2c.h>
20
21 DECLARE_GLOBAL_DATA_PTR;
22
omap_sys_boot_device(void)23 __weak u32 omap_sys_boot_device(void)
24 {
25 return BOOT_DEVICE_NONE;
26 }
27
save_omap_boot_params(void)28 void save_omap_boot_params(void)
29 {
30 u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
31 struct omap_boot_parameters *omap_boot_params;
32 int sys_boot_device = 0;
33 u32 boot_device;
34 u32 boot_mode;
35
36 if ((boot_params < NON_SECURE_SRAM_START) ||
37 (boot_params > NON_SECURE_SRAM_END))
38 return;
39
40 omap_boot_params = (struct omap_boot_parameters *)boot_params;
41
42 boot_device = omap_boot_params->boot_device;
43 boot_mode = MMCSD_MODE_UNDEFINED;
44
45 /* Boot device */
46
47 #ifdef BOOT_DEVICE_NAND_I2C
48 /*
49 * Re-map NAND&I2C boot-device to the "normal" NAND boot-device.
50 * Otherwise the SPL boot IF can't handle this device correctly.
51 * Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens
52 * Draco leads to this boot-device passed to SPL from the BootROM.
53 */
54 if (boot_device == BOOT_DEVICE_NAND_I2C)
55 boot_device = BOOT_DEVICE_NAND;
56 #endif
57 #ifdef BOOT_DEVICE_QSPI_4
58 /*
59 * We get different values for QSPI_1 and QSPI_4 being used, but
60 * don't actually care about this difference. Rather than
61 * mangle the later code, if we're coming in as QSPI_4 just
62 * change to the QSPI_1 value.
63 */
64 if (boot_device == BOOT_DEVICE_QSPI_4)
65 boot_device = BOOT_DEVICE_SPI;
66 #endif
67 #ifdef CONFIG_TI816X
68 /*
69 * On PG2.0 and later TI816x the values we get when booting are not the
70 * same as on PG1.0, which is what the defines are based on. Update
71 * them as needed.
72 */
73 if (get_cpu_rev() != 1) {
74 if (boot_device == 0x05) {
75 omap_boot_params->boot_device = BOOT_DEVICE_NAND;
76 boot_device = BOOT_DEVICE_NAND;
77 }
78 if (boot_device == 0x08) {
79 omap_boot_params->boot_device = BOOT_DEVICE_MMC1;
80 boot_device = BOOT_DEVICE_MMC1;
81 }
82 }
83 #endif
84 /*
85 * When booting from peripheral booting, the boot device is not usable
86 * as-is (unless there is support for it), so the boot device is instead
87 * figured out using the SYS_BOOT pins.
88 */
89 switch (boot_device) {
90 #if defined(BOOT_DEVICE_UART) && !defined(CONFIG_SPL_YMODEM_SUPPORT)
91 case BOOT_DEVICE_UART:
92 sys_boot_device = 1;
93 break;
94 #endif
95 #if defined(BOOT_DEVICE_USB) && !defined(CONFIG_SPL_USB_STORAGE)
96 case BOOT_DEVICE_USB:
97 sys_boot_device = 1;
98 break;
99 #endif
100 #if defined(BOOT_DEVICE_USBETH) && !defined(CONFIG_SPL_USB_ETHER)
101 case BOOT_DEVICE_USBETH:
102 sys_boot_device = 1;
103 break;
104 #endif
105 #if defined(BOOT_DEVICE_CPGMAC) && !defined(CONFIG_SPL_ETH_SUPPORT)
106 case BOOT_DEVICE_CPGMAC:
107 sys_boot_device = 1;
108 break;
109 #endif
110 #if defined(BOOT_DEVICE_DFU) && !defined(CONFIG_SPL_DFU)
111 case BOOT_DEVICE_DFU:
112 sys_boot_device = 1;
113 break;
114 #endif
115 }
116
117 if (sys_boot_device) {
118 boot_device = omap_sys_boot_device();
119
120 /* MMC raw mode will fallback to FS mode. */
121 if ((boot_device >= MMC_BOOT_DEVICES_START) &&
122 (boot_device <= MMC_BOOT_DEVICES_END))
123 boot_mode = MMCSD_MODE_RAW;
124 }
125
126 gd->arch.omap_boot_device = boot_device;
127
128 /* Boot mode */
129
130 #ifdef CONFIG_OMAP34XX
131 if ((boot_device >= MMC_BOOT_DEVICES_START) &&
132 (boot_device <= MMC_BOOT_DEVICES_END)) {
133 switch (boot_device) {
134 case BOOT_DEVICE_MMC1:
135 boot_mode = MMCSD_MODE_FS;
136 break;
137 case BOOT_DEVICE_MMC2:
138 boot_mode = MMCSD_MODE_RAW;
139 break;
140 }
141 }
142 #else
143 /*
144 * If the boot device was dynamically changed and doesn't match what
145 * the bootrom initially booted, we cannot use the boot device
146 * descriptor to figure out the boot mode.
147 */
148 if ((boot_device == omap_boot_params->boot_device) &&
149 (boot_device >= MMC_BOOT_DEVICES_START) &&
150 (boot_device <= MMC_BOOT_DEVICES_END)) {
151 boot_params = omap_boot_params->boot_device_descriptor;
152 if ((boot_params < NON_SECURE_SRAM_START) ||
153 (boot_params > NON_SECURE_SRAM_END))
154 return;
155
156 boot_params = *((u32 *)(boot_params + DEVICE_DATA_OFFSET));
157 if ((boot_params < NON_SECURE_SRAM_START) ||
158 (boot_params > NON_SECURE_SRAM_END))
159 return;
160
161 boot_mode = *((u32 *)(boot_params + BOOT_MODE_OFFSET));
162
163 if (boot_mode != MMCSD_MODE_FS &&
164 boot_mode != MMCSD_MODE_RAW)
165 #ifdef CONFIG_SUPPORT_EMMC_BOOT
166 boot_mode = MMCSD_MODE_EMMCBOOT;
167 #else
168 boot_mode = MMCSD_MODE_UNDEFINED;
169 #endif
170 }
171 #endif
172
173 gd->arch.omap_boot_mode = boot_mode;
174
175 #if !defined(CONFIG_TI814X) && !defined(CONFIG_TI816X) && \
176 !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX)
177
178 /* CH flags */
179
180 gd->arch.omap_ch_flags = omap_boot_params->ch_flags;
181 #endif
182 }
183
184 #ifdef CONFIG_SPL_BUILD
spl_boot_device(void)185 u32 spl_boot_device(void)
186 {
187 return gd->arch.omap_boot_device;
188 }
189
spl_boot_mode(const u32 boot_device)190 u32 spl_boot_mode(const u32 boot_device)
191 {
192 return gd->arch.omap_boot_mode;
193 }
194
spl_board_init(void)195 void spl_board_init(void)
196 {
197 #ifdef CONFIG_SPL_SERIAL_SUPPORT
198 /* Prepare console output */
199 preloader_console_init();
200 #endif
201 #if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
202 gpmc_init();
203 #endif
204 #if defined(CONFIG_SPL_I2C_SUPPORT) && !defined(CONFIG_DM_I2C)
205 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
206 #endif
207 #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
208 arch_misc_init();
209 #endif
210 #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
211 hw_watchdog_init();
212 #endif
213 #ifdef CONFIG_AM33XX
214 am33xx_spl_board_init();
215 #endif
216 }
217
jump_to_image_no_args(struct spl_image_info * spl_image)218 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
219 {
220 typedef void __noreturn (*image_entry_noargs_t)(u32 *);
221 image_entry_noargs_t image_entry =
222 (image_entry_noargs_t) spl_image->entry_point;
223
224 u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
225
226 debug("image entry point: 0x%lX\n", spl_image->entry_point);
227 /* Pass the saved boot_params from rom code */
228 image_entry((u32 *)boot_params);
229 }
230 #endif
231
232 #ifdef CONFIG_SCSI_AHCI_PLAT
arch_preboot_os(void)233 void arch_preboot_os(void)
234 {
235 ahci_reset((void __iomem *)DWC_AHSATA_BASE);
236 }
237 #endif
238