1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 * Chao Fu (B44548@freescale.com)
9 * Haikun Wang (B53464@freescale.com)
10 */
11
12 #include <common.h>
13 #include <dm.h>
14 #include <errno.h>
15 #include <common.h>
16 #include <spi.h>
17 #include <malloc.h>
18 #include <asm/io.h>
19 #include <fdtdec.h>
20 #ifndef CONFIG_M68K
21 #include <asm/arch/clock.h>
22 #endif
23 #include <fsl_dspi.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 /* fsl_dspi_platdata flags */
28 #define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
29
30 /* idle data value */
31 #define DSPI_IDLE_VAL 0x0
32
33 /* max chipselect signals number */
34 #define FSL_DSPI_MAX_CHIPSELECT 6
35
36 /* default SCK frequency, unit: HZ */
37 #define FSL_DSPI_DEFAULT_SCK_FREQ 10000000
38
39 /* tx/rx data wait timeout value, unit: us */
40 #define DSPI_TXRX_WAIT_TIMEOUT 1000000
41
42 /* CTAR register pre-configure value */
43 #define DSPI_CTAR_DEFAULT_VALUE (DSPI_CTAR_TRSZ(7) | \
44 DSPI_CTAR_PCSSCK_1CLK | \
45 DSPI_CTAR_PASC(0) | \
46 DSPI_CTAR_PDT(0) | \
47 DSPI_CTAR_CSSCK(0) | \
48 DSPI_CTAR_ASC(0) | \
49 DSPI_CTAR_DT(0))
50
51 /* CTAR register pre-configure mask */
52 #define DSPI_CTAR_SET_MODE_MASK (DSPI_CTAR_TRSZ(15) | \
53 DSPI_CTAR_PCSSCK(3) | \
54 DSPI_CTAR_PASC(3) | \
55 DSPI_CTAR_PDT(3) | \
56 DSPI_CTAR_CSSCK(15) | \
57 DSPI_CTAR_ASC(15) | \
58 DSPI_CTAR_DT(15))
59
60 /**
61 * struct fsl_dspi_platdata - platform data for Freescale DSPI
62 *
63 * @flags: Flags for DSPI DSPI_FLAG_...
64 * @speed_hz: Default SCK frequency
65 * @num_chipselect: Number of DSPI chipselect signals
66 * @regs_addr: Base address of DSPI registers
67 */
68 struct fsl_dspi_platdata {
69 uint flags;
70 uint speed_hz;
71 uint num_chipselect;
72 fdt_addr_t regs_addr;
73 };
74
75 /**
76 * struct fsl_dspi_priv - private data for Freescale DSPI
77 *
78 * @flags: Flags for DSPI DSPI_FLAG_...
79 * @mode: SPI mode to use for slave device (see SPI mode flags)
80 * @mcr_val: MCR register configure value
81 * @bus_clk: DSPI input clk frequency
82 * @speed_hz: Default SCK frequency
83 * @charbit: How many bits in every transfer
84 * @num_chipselect: Number of DSPI chipselect signals
85 * @ctar_val: CTAR register configure value of per chipselect slave device
86 * @regs: Point to DSPI register structure for I/O access
87 */
88 struct fsl_dspi_priv {
89 uint flags;
90 uint mode;
91 uint mcr_val;
92 uint bus_clk;
93 uint speed_hz;
94 uint charbit;
95 uint num_chipselect;
96 uint ctar_val[FSL_DSPI_MAX_CHIPSELECT];
97 struct dspi *regs;
98 };
99
100 #ifndef CONFIG_DM_SPI
101 struct fsl_dspi {
102 struct spi_slave slave;
103 struct fsl_dspi_priv priv;
104 };
105 #endif
106
cpu_dspi_port_conf(void)107 __weak void cpu_dspi_port_conf(void)
108 {
109 }
110
cpu_dspi_claim_bus(uint bus,uint cs)111 __weak int cpu_dspi_claim_bus(uint bus, uint cs)
112 {
113 return 0;
114 }
115
cpu_dspi_release_bus(uint bus,uint cs)116 __weak void cpu_dspi_release_bus(uint bus, uint cs)
117 {
118 }
119
dspi_read32(uint flags,uint * addr)120 static uint dspi_read32(uint flags, uint *addr)
121 {
122 return flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
123 in_be32(addr) : in_le32(addr);
124 }
125
dspi_write32(uint flags,uint * addr,uint val)126 static void dspi_write32(uint flags, uint *addr, uint val)
127 {
128 flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
129 out_be32(addr, val) : out_le32(addr, val);
130 }
131
dspi_halt(struct fsl_dspi_priv * priv,u8 halt)132 static void dspi_halt(struct fsl_dspi_priv *priv, u8 halt)
133 {
134 uint mcr_val;
135
136 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
137
138 if (halt)
139 mcr_val |= DSPI_MCR_HALT;
140 else
141 mcr_val &= ~DSPI_MCR_HALT;
142
143 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
144 }
145
fsl_dspi_init_mcr(struct fsl_dspi_priv * priv,uint cfg_val)146 static void fsl_dspi_init_mcr(struct fsl_dspi_priv *priv, uint cfg_val)
147 {
148 /* halt DSPI module */
149 dspi_halt(priv, 1);
150
151 dspi_write32(priv->flags, &priv->regs->mcr, cfg_val);
152
153 /* resume module */
154 dspi_halt(priv, 0);
155
156 priv->mcr_val = cfg_val;
157 }
158
fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv * priv,uint cs,uint state)159 static void fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv *priv,
160 uint cs, uint state)
161 {
162 uint mcr_val;
163
164 dspi_halt(priv, 1);
165
166 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
167 if (state & SPI_CS_HIGH)
168 /* CSx inactive state is low */
169 mcr_val &= ~DSPI_MCR_PCSIS(cs);
170 else
171 /* CSx inactive state is high */
172 mcr_val |= DSPI_MCR_PCSIS(cs);
173 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
174
175 dspi_halt(priv, 0);
176 }
177
fsl_dspi_cfg_ctar_mode(struct fsl_dspi_priv * priv,uint cs,uint mode)178 static int fsl_dspi_cfg_ctar_mode(struct fsl_dspi_priv *priv,
179 uint cs, uint mode)
180 {
181 uint bus_setup;
182
183 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
184
185 bus_setup &= ~DSPI_CTAR_SET_MODE_MASK;
186 bus_setup |= priv->ctar_val[cs];
187 bus_setup &= ~(DSPI_CTAR_CPOL | DSPI_CTAR_CPHA | DSPI_CTAR_LSBFE);
188
189 if (mode & SPI_CPOL)
190 bus_setup |= DSPI_CTAR_CPOL;
191 if (mode & SPI_CPHA)
192 bus_setup |= DSPI_CTAR_CPHA;
193 if (mode & SPI_LSB_FIRST)
194 bus_setup |= DSPI_CTAR_LSBFE;
195
196 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
197
198 priv->charbit =
199 ((dspi_read32(priv->flags, &priv->regs->ctar[0]) &
200 DSPI_CTAR_TRSZ(15)) == DSPI_CTAR_TRSZ(15)) ? 16 : 8;
201
202 return 0;
203 }
204
fsl_dspi_clr_fifo(struct fsl_dspi_priv * priv)205 static void fsl_dspi_clr_fifo(struct fsl_dspi_priv *priv)
206 {
207 uint mcr_val;
208
209 dspi_halt(priv, 1);
210 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
211 /* flush RX and TX FIFO */
212 mcr_val |= (DSPI_MCR_CTXF | DSPI_MCR_CRXF);
213 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
214 dspi_halt(priv, 0);
215 }
216
dspi_tx(struct fsl_dspi_priv * priv,u32 ctrl,u16 data)217 static void dspi_tx(struct fsl_dspi_priv *priv, u32 ctrl, u16 data)
218 {
219 int timeout = DSPI_TXRX_WAIT_TIMEOUT;
220
221 /* wait for empty entries in TXFIFO or timeout */
222 while (DSPI_SR_TXCTR(dspi_read32(priv->flags, &priv->regs->sr)) >= 4 &&
223 timeout--)
224 udelay(1);
225
226 if (timeout >= 0)
227 dspi_write32(priv->flags, &priv->regs->tfr, (ctrl | data));
228 else
229 debug("dspi_tx: waiting timeout!\n");
230 }
231
dspi_rx(struct fsl_dspi_priv * priv)232 static u16 dspi_rx(struct fsl_dspi_priv *priv)
233 {
234 int timeout = DSPI_TXRX_WAIT_TIMEOUT;
235
236 /* wait for valid entries in RXFIFO or timeout */
237 while (DSPI_SR_RXCTR(dspi_read32(priv->flags, &priv->regs->sr)) == 0 &&
238 timeout--)
239 udelay(1);
240
241 if (timeout >= 0)
242 return (u16)DSPI_RFR_RXDATA(
243 dspi_read32(priv->flags, &priv->regs->rfr));
244 else {
245 debug("dspi_rx: waiting timeout!\n");
246 return (u16)(~0);
247 }
248 }
249
dspi_xfer(struct fsl_dspi_priv * priv,uint cs,unsigned int bitlen,const void * dout,void * din,unsigned long flags)250 static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen,
251 const void *dout, void *din, unsigned long flags)
252 {
253 u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
254 u8 *spi_rd = NULL, *spi_wr = NULL;
255 static u32 ctrl;
256 uint len = bitlen >> 3;
257
258 if (priv->charbit == 16) {
259 bitlen >>= 1;
260 spi_wr16 = (u16 *)dout;
261 spi_rd16 = (u16 *)din;
262 } else {
263 spi_wr = (u8 *)dout;
264 spi_rd = (u8 *)din;
265 }
266
267 if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
268 ctrl |= DSPI_TFR_CONT;
269
270 ctrl = ctrl & DSPI_TFR_CONT;
271 ctrl = ctrl | DSPI_TFR_CTAS(0) | DSPI_TFR_PCS(cs);
272
273 if (len > 1) {
274 int tmp_len = len - 1;
275 while (tmp_len--) {
276 if ((dout != NULL) && (din != NULL)) {
277 if (priv->charbit == 16) {
278 dspi_tx(priv, ctrl, *spi_wr16++);
279 *spi_rd16++ = dspi_rx(priv);
280 }
281 else {
282 dspi_tx(priv, ctrl, *spi_wr++);
283 *spi_rd++ = dspi_rx(priv);
284 }
285 }
286
287 else if (dout != NULL) {
288 if (priv->charbit == 16)
289 dspi_tx(priv, ctrl, *spi_wr16++);
290 else
291 dspi_tx(priv, ctrl, *spi_wr++);
292 dspi_rx(priv);
293 }
294
295 else if (din != NULL) {
296 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
297 if (priv->charbit == 16)
298 *spi_rd16++ = dspi_rx(priv);
299 else
300 *spi_rd++ = dspi_rx(priv);
301 }
302 }
303
304 len = 1; /* remaining byte */
305 }
306
307 if ((flags & SPI_XFER_END) == SPI_XFER_END)
308 ctrl &= ~DSPI_TFR_CONT;
309
310 if (len) {
311 if ((dout != NULL) && (din != NULL)) {
312 if (priv->charbit == 16) {
313 dspi_tx(priv, ctrl, *spi_wr16++);
314 *spi_rd16++ = dspi_rx(priv);
315 }
316 else {
317 dspi_tx(priv, ctrl, *spi_wr++);
318 *spi_rd++ = dspi_rx(priv);
319 }
320 }
321
322 else if (dout != NULL) {
323 if (priv->charbit == 16)
324 dspi_tx(priv, ctrl, *spi_wr16);
325 else
326 dspi_tx(priv, ctrl, *spi_wr);
327 dspi_rx(priv);
328 }
329
330 else if (din != NULL) {
331 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
332 if (priv->charbit == 16)
333 *spi_rd16 = dspi_rx(priv);
334 else
335 *spi_rd = dspi_rx(priv);
336 }
337 } else {
338 /* dummy read */
339 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
340 dspi_rx(priv);
341 }
342
343 return 0;
344 }
345
346 /**
347 * Calculate the divide value between input clk frequency and expected SCK frequency
348 * Formula: SCK = (clkrate/pbr) x ((1+dbr)/br)
349 * Dbr: use default value 0
350 *
351 * @pbr: return Baud Rate Prescaler value
352 * @br: return Baud Rate Scaler value
353 * @speed_hz: expected SCK frequency
354 * @clkrate: input clk frequency
355 */
fsl_dspi_hz_to_spi_baud(int * pbr,int * br,int speed_hz,uint clkrate)356 static int fsl_dspi_hz_to_spi_baud(int *pbr, int *br,
357 int speed_hz, uint clkrate)
358 {
359 /* Valid baud rate pre-scaler values */
360 int pbr_tbl[4] = {2, 3, 5, 7};
361 int brs[16] = {2, 4, 6, 8,
362 16, 32, 64, 128,
363 256, 512, 1024, 2048,
364 4096, 8192, 16384, 32768};
365 int temp, i = 0, j = 0;
366
367 temp = clkrate / speed_hz;
368
369 for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
370 for (j = 0; j < ARRAY_SIZE(brs); j++) {
371 if (pbr_tbl[i] * brs[j] >= temp) {
372 *pbr = i;
373 *br = j;
374 return 0;
375 }
376 }
377
378 debug("Can not find valid baud rate,speed_hz is %d, ", speed_hz);
379 debug("clkrate is %d, we use the max prescaler value.\n", clkrate);
380
381 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
382 *br = ARRAY_SIZE(brs) - 1;
383 return -EINVAL;
384 }
385
fsl_dspi_cfg_speed(struct fsl_dspi_priv * priv,uint speed)386 static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed)
387 {
388 int ret;
389 uint bus_setup;
390 int best_i, best_j, bus_clk;
391
392 bus_clk = priv->bus_clk;
393
394 debug("DSPI set_speed: expected SCK speed %u, bus_clk %u.\n",
395 speed, bus_clk);
396
397 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
398 bus_setup &= ~(DSPI_CTAR_DBR | DSPI_CTAR_PBR(0x3) | DSPI_CTAR_BR(0xf));
399
400 ret = fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
401 if (ret) {
402 speed = priv->speed_hz;
403 debug("DSPI set_speed use default SCK rate %u.\n", speed);
404 fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
405 }
406
407 bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
408 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
409
410 priv->speed_hz = speed;
411
412 return 0;
413 }
414 #ifndef CONFIG_DM_SPI
spi_cs_is_valid(unsigned int bus,unsigned int cs)415 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
416 {
417 if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
418 return 1;
419 else
420 return 0;
421 }
422
spi_setup_slave(unsigned int bus,unsigned int cs,unsigned int max_hz,unsigned int mode)423 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
424 unsigned int max_hz, unsigned int mode)
425 {
426 struct fsl_dspi *dspi;
427 uint mcr_cfg_val;
428
429 dspi = spi_alloc_slave(struct fsl_dspi, bus, cs);
430 if (!dspi)
431 return NULL;
432
433 cpu_dspi_port_conf();
434
435 #ifdef CONFIG_SYS_FSL_DSPI_BE
436 dspi->priv.flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
437 #endif
438
439 dspi->priv.regs = (struct dspi *)MMAP_DSPI;
440
441 #ifdef CONFIG_M68K
442 dspi->priv.bus_clk = gd->bus_clk;
443 #else
444 dspi->priv.bus_clk = mxc_get_clock(MXC_DSPI_CLK);
445 #endif
446 dspi->priv.speed_hz = FSL_DSPI_DEFAULT_SCK_FREQ;
447
448 /* default: all CS signals inactive state is high */
449 mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
450 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
451 fsl_dspi_init_mcr(&dspi->priv, mcr_cfg_val);
452
453 for (i = 0; i < FSL_DSPI_MAX_CHIPSELECT; i++)
454 dspi->priv.ctar_val[i] = DSPI_CTAR_DEFAULT_VALUE;
455
456 #ifdef CONFIG_SYS_DSPI_CTAR0
457 if (FSL_DSPI_MAX_CHIPSELECT > 0)
458 dspi->priv.ctar_val[0] = CONFIG_SYS_DSPI_CTAR0;
459 #endif
460 #ifdef CONFIG_SYS_DSPI_CTAR1
461 if (FSL_DSPI_MAX_CHIPSELECT > 1)
462 dspi->priv.ctar_val[1] = CONFIG_SYS_DSPI_CTAR1;
463 #endif
464 #ifdef CONFIG_SYS_DSPI_CTAR2
465 if (FSL_DSPI_MAX_CHIPSELECT > 2)
466 dspi->priv.ctar_val[2] = CONFIG_SYS_DSPI_CTAR2;
467 #endif
468 #ifdef CONFIG_SYS_DSPI_CTAR3
469 if (FSL_DSPI_MAX_CHIPSELECT > 3)
470 dspi->priv.ctar_val[3] = CONFIG_SYS_DSPI_CTAR3;
471 #endif
472 #ifdef CONFIG_SYS_DSPI_CTAR4
473 if (FSL_DSPI_MAX_CHIPSELECT > 4)
474 dspi->priv.ctar_val[4] = CONFIG_SYS_DSPI_CTAR4;
475 #endif
476 #ifdef CONFIG_SYS_DSPI_CTAR5
477 if (FSL_DSPI_MAX_CHIPSELECT > 5)
478 dspi->priv.ctar_val[5] = CONFIG_SYS_DSPI_CTAR5;
479 #endif
480 #ifdef CONFIG_SYS_DSPI_CTAR6
481 if (FSL_DSPI_MAX_CHIPSELECT > 6)
482 dspi->priv.ctar_val[6] = CONFIG_SYS_DSPI_CTAR6;
483 #endif
484 #ifdef CONFIG_SYS_DSPI_CTAR7
485 if (FSL_DSPI_MAX_CHIPSELECT > 7)
486 dspi->priv.ctar_val[7] = CONFIG_SYS_DSPI_CTAR7;
487 #endif
488
489 fsl_dspi_cfg_speed(&dspi->priv, max_hz);
490
491 /* configure transfer mode */
492 fsl_dspi_cfg_ctar_mode(&dspi->priv, cs, mode);
493
494 /* configure active state of CSX */
495 fsl_dspi_cfg_cs_active_state(&dspi->priv, cs, mode);
496
497 return &dspi->slave;
498 }
499
spi_free_slave(struct spi_slave * slave)500 void spi_free_slave(struct spi_slave *slave)
501 {
502 free(slave);
503 }
504
spi_claim_bus(struct spi_slave * slave)505 int spi_claim_bus(struct spi_slave *slave)
506 {
507 uint sr_val;
508 struct fsl_dspi *dspi = (struct fsl_dspi *)slave;
509
510 cpu_dspi_claim_bus(slave->bus, slave->cs);
511
512 fsl_dspi_clr_fifo(&dspi->priv);
513
514 /* check module TX and RX status */
515 sr_val = dspi_read32(dspi->priv.flags, &dspi->priv.regs->sr);
516 if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
517 debug("DSPI RX/TX not ready!\n");
518 return -EIO;
519 }
520
521 return 0;
522 }
523
spi_release_bus(struct spi_slave * slave)524 void spi_release_bus(struct spi_slave *slave)
525 {
526 struct fsl_dspi *dspi = (struct fsl_dspi *)slave;
527
528 dspi_halt(&dspi->priv, 1);
529 cpu_dspi_release_bus(slave->bus.slave->cs);
530 }
531
spi_xfer(struct spi_slave * slave,unsigned int bitlen,const void * dout,void * din,unsigned long flags)532 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
533 void *din, unsigned long flags)
534 {
535 struct fsl_dspi *dspi = (struct fsl_dspi *)slave;
536 return dspi_xfer(&dspi->priv, slave->cs, bitlen, dout, din, flags);
537 }
538 #else
fsl_dspi_child_pre_probe(struct udevice * dev)539 static int fsl_dspi_child_pre_probe(struct udevice *dev)
540 {
541 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
542 struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
543
544 if (slave_plat->cs >= priv->num_chipselect) {
545 debug("DSPI invalid chipselect number %d(max %d)!\n",
546 slave_plat->cs, priv->num_chipselect - 1);
547 return -EINVAL;
548 }
549
550 priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE;
551
552 debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n",
553 slave_plat->cs, slave_plat->max_hz, slave_plat->mode);
554
555 return 0;
556 }
557
fsl_dspi_probe(struct udevice * bus)558 static int fsl_dspi_probe(struct udevice *bus)
559 {
560 struct fsl_dspi_platdata *plat = dev_get_platdata(bus);
561 struct fsl_dspi_priv *priv = dev_get_priv(bus);
562 struct dm_spi_bus *dm_spi_bus;
563 uint mcr_cfg_val;
564
565 dm_spi_bus = bus->uclass_priv;
566
567 /* cpu speical pin muxing configure */
568 cpu_dspi_port_conf();
569
570 /* get input clk frequency */
571 priv->regs = (struct dspi *)plat->regs_addr;
572 priv->flags = plat->flags;
573 #ifdef CONFIG_M68K
574 priv->bus_clk = gd->bus_clk;
575 #else
576 priv->bus_clk = mxc_get_clock(MXC_DSPI_CLK);
577 #endif
578 priv->num_chipselect = plat->num_chipselect;
579 priv->speed_hz = plat->speed_hz;
580 /* frame data length in bits, default 8bits */
581 priv->charbit = 8;
582
583 dm_spi_bus->max_hz = plat->speed_hz;
584
585 /* default: all CS signals inactive state is high */
586 mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
587 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
588 fsl_dspi_init_mcr(priv, mcr_cfg_val);
589
590 debug("%s probe done, bus-num %d.\n", bus->name, bus->seq);
591
592 return 0;
593 }
594
fsl_dspi_claim_bus(struct udevice * dev)595 static int fsl_dspi_claim_bus(struct udevice *dev)
596 {
597 uint sr_val;
598 struct fsl_dspi_priv *priv;
599 struct udevice *bus = dev->parent;
600 struct dm_spi_slave_platdata *slave_plat =
601 dev_get_parent_platdata(dev);
602
603 priv = dev_get_priv(bus);
604
605 /* processor special preparation work */
606 cpu_dspi_claim_bus(bus->seq, slave_plat->cs);
607
608 /* configure transfer mode */
609 fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs, priv->mode);
610
611 /* configure active state of CSX */
612 fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs,
613 priv->mode);
614
615 fsl_dspi_clr_fifo(priv);
616
617 /* check module TX and RX status */
618 sr_val = dspi_read32(priv->flags, &priv->regs->sr);
619 if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
620 debug("DSPI RX/TX not ready!\n");
621 return -EIO;
622 }
623
624 return 0;
625 }
626
fsl_dspi_release_bus(struct udevice * dev)627 static int fsl_dspi_release_bus(struct udevice *dev)
628 {
629 struct udevice *bus = dev->parent;
630 struct fsl_dspi_priv *priv = dev_get_priv(bus);
631 struct dm_spi_slave_platdata *slave_plat =
632 dev_get_parent_platdata(dev);
633
634 /* halt module */
635 dspi_halt(priv, 1);
636
637 /* processor special release work */
638 cpu_dspi_release_bus(bus->seq, slave_plat->cs);
639
640 return 0;
641 }
642
643 /**
644 * This function doesn't do anything except help with debugging
645 */
fsl_dspi_bind(struct udevice * bus)646 static int fsl_dspi_bind(struct udevice *bus)
647 {
648 debug("%s assigned req_seq %d.\n", bus->name, bus->req_seq);
649 return 0;
650 }
651
fsl_dspi_ofdata_to_platdata(struct udevice * bus)652 static int fsl_dspi_ofdata_to_platdata(struct udevice *bus)
653 {
654 fdt_addr_t addr;
655 struct fsl_dspi_platdata *plat = bus->platdata;
656 const void *blob = gd->fdt_blob;
657 int node = dev_of_offset(bus);
658
659 if (fdtdec_get_bool(blob, node, "big-endian"))
660 plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
661
662 plat->num_chipselect =
663 fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
664
665 addr = devfdt_get_addr(bus);
666 if (addr == FDT_ADDR_T_NONE) {
667 debug("DSPI: Can't get base address or size\n");
668 return -ENOMEM;
669 }
670 plat->regs_addr = addr;
671
672 plat->speed_hz = fdtdec_get_int(blob,
673 node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
674
675 debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n",
676 &plat->regs_addr, plat->speed_hz,
677 plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
678 plat->num_chipselect);
679
680 return 0;
681 }
682
fsl_dspi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)683 static int fsl_dspi_xfer(struct udevice *dev, unsigned int bitlen,
684 const void *dout, void *din, unsigned long flags)
685 {
686 struct fsl_dspi_priv *priv;
687 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
688 struct udevice *bus;
689
690 bus = dev->parent;
691 priv = dev_get_priv(bus);
692
693 return dspi_xfer(priv, slave_plat->cs, bitlen, dout, din, flags);
694 }
695
fsl_dspi_set_speed(struct udevice * bus,uint speed)696 static int fsl_dspi_set_speed(struct udevice *bus, uint speed)
697 {
698 struct fsl_dspi_priv *priv = dev_get_priv(bus);
699
700 return fsl_dspi_cfg_speed(priv, speed);
701 }
702
fsl_dspi_set_mode(struct udevice * bus,uint mode)703 static int fsl_dspi_set_mode(struct udevice *bus, uint mode)
704 {
705 struct fsl_dspi_priv *priv = dev_get_priv(bus);
706
707 debug("DSPI set_mode: mode 0x%x.\n", mode);
708
709 /*
710 * We store some chipselect special configure value in priv->ctar_val,
711 * and we can't get the correct chipselect number here,
712 * so just store mode value.
713 * Do really configuration when claim_bus.
714 */
715 priv->mode = mode;
716
717 return 0;
718 }
719
720 static const struct dm_spi_ops fsl_dspi_ops = {
721 .claim_bus = fsl_dspi_claim_bus,
722 .release_bus = fsl_dspi_release_bus,
723 .xfer = fsl_dspi_xfer,
724 .set_speed = fsl_dspi_set_speed,
725 .set_mode = fsl_dspi_set_mode,
726 };
727
728 static const struct udevice_id fsl_dspi_ids[] = {
729 { .compatible = "fsl,vf610-dspi" },
730 { }
731 };
732
733 U_BOOT_DRIVER(fsl_dspi) = {
734 .name = "fsl_dspi",
735 .id = UCLASS_SPI,
736 .of_match = fsl_dspi_ids,
737 .ops = &fsl_dspi_ops,
738 .ofdata_to_platdata = fsl_dspi_ofdata_to_platdata,
739 .platdata_auto_alloc_size = sizeof(struct fsl_dspi_platdata),
740 .priv_auto_alloc_size = sizeof(struct fsl_dspi_priv),
741 .probe = fsl_dspi_probe,
742 .child_pre_probe = fsl_dspi_child_pre_probe,
743 .bind = fsl_dspi_bind,
744 };
745 #endif
746