1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
4 * With help from the common/soft_spi and arch/powerpc/cpu/mpc8260 drivers
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <malloc.h>
11 #include <spi.h>
12 #include <asm/mpc8xxx_spi.h>
13 #include <asm-generic/gpio.h>
14
15 enum {
16 SPI_EV_NE = BIT(31 - 22), /* Receiver Not Empty */
17 SPI_EV_NF = BIT(31 - 23), /* Transmitter Not Full */
18 };
19
20 enum {
21 SPI_MODE_LOOP = BIT(31 - 1), /* Loopback mode */
22 SPI_MODE_CI = BIT(31 - 2), /* Clock invert */
23 SPI_MODE_CP = BIT(31 - 3), /* Clock phase */
24 SPI_MODE_DIV16 = BIT(31 - 4), /* Divide clock source by 16 */
25 SPI_MODE_REV = BIT(31 - 5), /* Reverse mode - MSB first */
26 SPI_MODE_MS = BIT(31 - 6), /* Always master */
27 SPI_MODE_EN = BIT(31 - 7), /* Enable interface */
28
29 SPI_MODE_LEN_MASK = 0xf00000,
30 SPI_MODE_PM_MASK = 0xf0000,
31
32 SPI_COM_LST = BIT(31 - 9),
33 };
34
35 struct mpc8xxx_priv {
36 spi8xxx_t *spi;
37 struct gpio_desc gpios[16];
38 int max_cs;
39 };
40
to_prescale_mod(u32 val)41 static inline u32 to_prescale_mod(u32 val)
42 {
43 return (min(val, (u32)15) << 16);
44 }
45
set_char_len(spi8xxx_t * spi,u32 val)46 static void set_char_len(spi8xxx_t *spi, u32 val)
47 {
48 clrsetbits_be32(&spi->mode, SPI_MODE_LEN_MASK, (val << 20));
49 }
50
51 #define SPI_TIMEOUT 1000
52
__spi_set_speed(spi8xxx_t * spi,uint speed)53 static int __spi_set_speed(spi8xxx_t *spi, uint speed)
54 {
55 /* TODO(mario.six@gdsys.cc): This only ever sets one fixed speed */
56
57 /* Use SYSCLK / 8 (16.67MHz typ.) */
58 clrsetbits_be32(&spi->mode, SPI_MODE_PM_MASK, to_prescale_mod(1));
59
60 return 0;
61 }
62
mpc8xxx_spi_ofdata_to_platdata(struct udevice * dev)63 static int mpc8xxx_spi_ofdata_to_platdata(struct udevice *dev)
64 {
65 struct mpc8xxx_priv *priv = dev_get_priv(dev);
66 int ret;
67
68 priv->spi = (spi8xxx_t *)dev_read_addr(dev);
69
70 /* TODO(mario.six@gdsys.cc): Read clock and save the value */
71
72 ret = gpio_request_list_by_name(dev, "gpios", priv->gpios,
73 ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
74 if (ret < 0)
75 return -EINVAL;
76
77 priv->max_cs = ret;
78
79 return 0;
80 }
81
mpc8xxx_spi_probe(struct udevice * dev)82 static int mpc8xxx_spi_probe(struct udevice *dev)
83 {
84 struct mpc8xxx_priv *priv = dev_get_priv(dev);
85
86 /*
87 * SPI pins on the MPC83xx are not muxed, so all we do is initialize
88 * some registers
89 */
90 out_be32(&priv->spi->mode, SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN);
91
92 __spi_set_speed(priv->spi, 16666667);
93
94 /* Clear all SPI events */
95 setbits_be32(&priv->spi->event, 0xffffffff);
96 /* Mask all SPI interrupts */
97 clrbits_be32(&priv->spi->mask, 0xffffffff);
98 /* LST bit doesn't do anything, so disregard */
99 out_be32(&priv->spi->com, 0);
100
101 return 0;
102 }
103
mpc8xxx_spi_cs_activate(struct udevice * dev)104 static void mpc8xxx_spi_cs_activate(struct udevice *dev)
105 {
106 struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
107 struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
108
109 dm_gpio_set_dir_flags(&priv->gpios[platdata->cs], GPIOD_IS_OUT);
110 dm_gpio_set_value(&priv->gpios[platdata->cs], 0);
111 }
112
mpc8xxx_spi_cs_deactivate(struct udevice * dev)113 static void mpc8xxx_spi_cs_deactivate(struct udevice *dev)
114 {
115 struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
116 struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
117
118 dm_gpio_set_dir_flags(&priv->gpios[platdata->cs], GPIOD_IS_OUT);
119 dm_gpio_set_value(&priv->gpios[platdata->cs], 1);
120 }
121
mpc8xxx_spi_xfer(struct udevice * dev,uint bitlen,const void * dout,void * din,ulong flags)122 static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen,
123 const void *dout, void *din, ulong flags)
124 {
125 struct udevice *bus = dev->parent;
126 struct mpc8xxx_priv *priv = dev_get_priv(bus);
127 spi8xxx_t *spi = priv->spi;
128 struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
129 u32 tmpdin = 0;
130 int num_blks = DIV_ROUND_UP(bitlen, 32);
131
132 debug("%s: slave %s:%u dout %08X din %08X bitlen %u\n", __func__,
133 bus->name, platdata->cs, *(uint *)dout, *(uint *)din, bitlen);
134
135 if (flags & SPI_XFER_BEGIN)
136 mpc8xxx_spi_cs_activate(dev);
137
138 /* Clear all SPI events */
139 setbits_be32(&spi->event, 0xffffffff);
140
141 /* Handle data in 32-bit chunks */
142 while (num_blks--) {
143 u32 tmpdout = 0;
144 uchar xfer_bitlen = (bitlen >= 32 ? 32 : bitlen);
145 ulong start;
146
147 clrbits_be32(&spi->mode, SPI_MODE_EN);
148
149 /* Set up length for this transfer */
150
151 if (bitlen <= 4) /* 4 bits or less */
152 set_char_len(spi, 3);
153 else if (bitlen <= 16) /* at most 16 bits */
154 set_char_len(spi, bitlen - 1);
155 else /* more than 16 bits -> full 32 bit transfer */
156 set_char_len(spi, 0);
157
158 setbits_be32(&spi->mode, SPI_MODE_EN);
159
160 /* Shift data so it's msb-justified */
161 tmpdout = *(u32 *)dout >> (32 - xfer_bitlen);
162
163 if (bitlen > 32) {
164 /* Set up the next iteration if sending > 32 bits */
165 bitlen -= 32;
166 dout += 4;
167 }
168
169 /* Write the data out */
170 out_be32(&spi->tx, tmpdout);
171
172 debug("*** %s: ... %08x written\n", __func__, tmpdout);
173
174 /*
175 * Wait for SPI transmit to get out
176 * or time out (1 second = 1000 ms)
177 * The NE event must be read and cleared first
178 */
179 start = get_timer(0);
180 do {
181 u32 event = in_be32(&spi->event);
182 bool have_ne = event & SPI_EV_NE;
183 bool have_nf = event & SPI_EV_NF;
184
185 if (!have_ne)
186 continue;
187
188 tmpdin = in_be32(&spi->rx);
189 setbits_be32(&spi->event, SPI_EV_NE);
190
191 *(u32 *)din = (tmpdin << (32 - xfer_bitlen));
192 if (xfer_bitlen == 32) {
193 /* Advance output buffer by 32 bits */
194 din += 4;
195 }
196
197 /*
198 * Only bail when we've had both NE and NF events.
199 * This will cause timeouts on RO devices, so maybe
200 * in the future put an arbitrary delay after writing
201 * the device. Arbitrary delays suck, though...
202 */
203 if (have_nf)
204 break;
205
206 mdelay(1);
207 } while (get_timer(start) < SPI_TIMEOUT);
208
209 if (get_timer(start) >= SPI_TIMEOUT) {
210 debug("*** %s: Time out during SPI transfer\n",
211 __func__);
212 return -ETIMEDOUT;
213 }
214
215 debug("*** %s: transfer ended. Value=%08x\n", __func__, tmpdin);
216 }
217
218 if (flags & SPI_XFER_END)
219 mpc8xxx_spi_cs_deactivate(dev);
220
221 return 0;
222 }
223
mpc8xxx_spi_set_speed(struct udevice * dev,uint speed)224 static int mpc8xxx_spi_set_speed(struct udevice *dev, uint speed)
225 {
226 struct mpc8xxx_priv *priv = dev_get_priv(dev);
227
228 return __spi_set_speed(priv->spi, speed);
229 }
230
mpc8xxx_spi_set_mode(struct udevice * dev,uint mode)231 static int mpc8xxx_spi_set_mode(struct udevice *dev, uint mode)
232 {
233 /* TODO(mario.six@gdsys.cc): Using SPI_CPHA (for clock phase) and
234 * SPI_CPOL (for clock polarity) should work
235 */
236 return 0;
237 }
238
239 static const struct dm_spi_ops mpc8xxx_spi_ops = {
240 .xfer = mpc8xxx_spi_xfer,
241 .set_speed = mpc8xxx_spi_set_speed,
242 .set_mode = mpc8xxx_spi_set_mode,
243 /*
244 * cs_info is not needed, since we require all chip selects to be
245 * in the device tree explicitly
246 */
247 };
248
249 static const struct udevice_id mpc8xxx_spi_ids[] = {
250 { .compatible = "fsl,spi" },
251 { }
252 };
253
254 U_BOOT_DRIVER(mpc8xxx_spi) = {
255 .name = "mpc8xxx_spi",
256 .id = UCLASS_SPI,
257 .of_match = mpc8xxx_spi_ids,
258 .ops = &mpc8xxx_spi_ops,
259 .ofdata_to_platdata = mpc8xxx_spi_ofdata_to_platdata,
260 .probe = mpc8xxx_spi_probe,
261 .priv_auto_alloc_size = sizeof(struct mpc8xxx_priv),
262 };
263