1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Freescale i.MX28 SPI driver
4 *
5 * Copyright (C) 2019 DENX Software Engineering
6 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
7 *
8 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
9 * on behalf of DENX Software Engineering GmbH
10 *
11 * NOTE: This driver only supports the SPI-controller chipselects,
12 * GPIO driven chipselects are not supported.
13 */
14
15 #include <common.h>
16 #include <cpu_func.h>
17 #include <malloc.h>
18 #include <memalign.h>
19 #include <spi.h>
20 #include <linux/errno.h>
21 #include <asm/io.h>
22 #include <asm/arch/clock.h>
23 #include <asm/arch/imx-regs.h>
24 #include <asm/arch/sys_proto.h>
25 #include <asm/mach-imx/dma.h>
26
27 #define MXS_SPI_MAX_TIMEOUT 1000000
28 #define MXS_SPI_PORT_OFFSET 0x2000
29 #define MXS_SSP_CHIPSELECT_MASK 0x00300000
30 #define MXS_SSP_CHIPSELECT_SHIFT 20
31
32 #define MXSSSP_SMALL_TRANSFER 512
33
mxs_spi_start_xfer(struct mxs_ssp_regs * ssp_regs)34 static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
35 {
36 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
37 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
38 }
39
mxs_spi_end_xfer(struct mxs_ssp_regs * ssp_regs)40 static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
41 {
42 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
43 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
44 }
45
46 #if !CONFIG_IS_ENABLED(DM_SPI)
47 struct mxs_spi_slave {
48 struct spi_slave slave;
49 uint32_t max_khz;
50 uint32_t mode;
51 struct mxs_ssp_regs *regs;
52 };
53
to_mxs_slave(struct spi_slave * slave)54 static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
55 {
56 return container_of(slave, struct mxs_spi_slave, slave);
57 }
58 #else
59 #include <dm.h>
60 #include <errno.h>
61 #include <dt-structs.h>
62
63 #ifdef CONFIG_MX28
64 #define dtd_fsl_imx_spi dtd_fsl_imx28_spi
65 #else /* CONFIG_MX23 */
66 #define dtd_fsl_imx_spi dtd_fsl_imx23_spi
67 #endif
68
69 struct mxs_spi_platdata {
70 #if CONFIG_IS_ENABLED(OF_PLATDATA)
71 struct dtd_fsl_imx_spi dtplat;
72 #endif
73 s32 frequency; /* Default clock frequency, -1 for none */
74 fdt_addr_t base; /* SPI IP block base address */
75 int num_cs; /* Number of CSes supported */
76 int dma_id; /* ID of the DMA channel */
77 int clk_id; /* ID of the SSP clock */
78 };
79
80 struct mxs_spi_priv {
81 struct mxs_ssp_regs *regs;
82 unsigned int dma_channel;
83 unsigned int max_freq;
84 unsigned int clk_id;
85 unsigned int mode;
86 };
87 #endif
88
89 #if !CONFIG_IS_ENABLED(DM_SPI)
mxs_spi_xfer_pio(struct mxs_spi_slave * slave,char * data,int length,int write,unsigned long flags)90 static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
91 char *data, int length, int write, unsigned long flags)
92 {
93 struct mxs_ssp_regs *ssp_regs = slave->regs;
94 #else
95 static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv,
96 char *data, int length, int write,
97 unsigned long flags)
98 {
99 struct mxs_ssp_regs *ssp_regs = priv->regs;
100 #endif
101
102 if (flags & SPI_XFER_BEGIN)
103 mxs_spi_start_xfer(ssp_regs);
104
105 while (length--) {
106 /* We transfer 1 byte */
107 #if defined(CONFIG_MX23)
108 writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
109 writel(1, &ssp_regs->hw_ssp_ctrl0_set);
110 #elif defined(CONFIG_MX28)
111 writel(1, &ssp_regs->hw_ssp_xfer_size);
112 #endif
113
114 if ((flags & SPI_XFER_END) && !length)
115 mxs_spi_end_xfer(ssp_regs);
116
117 if (write)
118 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
119 else
120 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
121
122 writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
123
124 if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
125 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
126 printf("MXS SPI: Timeout waiting for start\n");
127 return -ETIMEDOUT;
128 }
129
130 if (write)
131 writel(*data++, &ssp_regs->hw_ssp_data);
132
133 writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
134
135 if (!write) {
136 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
137 SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
138 printf("MXS SPI: Timeout waiting for data\n");
139 return -ETIMEDOUT;
140 }
141
142 *data = readl(&ssp_regs->hw_ssp_data);
143 data++;
144 }
145
146 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
147 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
148 printf("MXS SPI: Timeout waiting for finish\n");
149 return -ETIMEDOUT;
150 }
151 }
152
153 return 0;
154 }
155
156 #if !CONFIG_IS_ENABLED(DM_SPI)
157 static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
158 char *data, int length, int write, unsigned long flags)
159 {
160 struct mxs_ssp_regs *ssp_regs = slave->regs;
161 #else
162 static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv,
163 char *data, int length, int write,
164 unsigned long flags)
165 { struct mxs_ssp_regs *ssp_regs = priv->regs;
166 #endif
167 const int xfer_max_sz = 0xff00;
168 const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
169 struct mxs_dma_desc *dp;
170 uint32_t ctrl0;
171 uint32_t cache_data_count;
172 const uint32_t dstart = (uint32_t)data;
173 int dmach;
174 int tl;
175 int ret = 0;
176
177 #if defined(CONFIG_MX23)
178 const int mxs_spi_pio_words = 1;
179 #elif defined(CONFIG_MX28)
180 const int mxs_spi_pio_words = 4;
181 #endif
182
183 ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
184
185 memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
186
187 ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
188 ctrl0 |= SSP_CTRL0_DATA_XFER;
189
190 if (flags & SPI_XFER_BEGIN)
191 ctrl0 |= SSP_CTRL0_LOCK_CS;
192 if (!write)
193 ctrl0 |= SSP_CTRL0_READ;
194
195 if (length % ARCH_DMA_MINALIGN)
196 cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
197 else
198 cache_data_count = length;
199
200 /* Flush data to DRAM so DMA can pick them up */
201 if (write)
202 flush_dcache_range(dstart, dstart + cache_data_count);
203
204 /* Invalidate the area, so no writeback into the RAM races with DMA */
205 invalidate_dcache_range(dstart, dstart + cache_data_count);
206
207 #if !CONFIG_IS_ENABLED(DM_SPI)
208 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
209 #else
210 dmach = priv->dma_channel;
211 #endif
212
213 dp = desc;
214 while (length) {
215 dp->address = (dma_addr_t)dp;
216 dp->cmd.address = (dma_addr_t)data;
217
218 /*
219 * This is correct, even though it does indeed look insane.
220 * I hereby have to, wholeheartedly, thank Freescale Inc.,
221 * for always inventing insane hardware and keeping me busy
222 * and employed ;-)
223 */
224 if (write)
225 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
226 else
227 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
228
229 /*
230 * The DMA controller can transfer large chunks (64kB) at
231 * time by setting the transfer length to 0. Setting tl to
232 * 0x10000 will overflow below and make .data contain 0.
233 * Otherwise, 0xff00 is the transfer maximum.
234 */
235 if (length >= 0x10000)
236 tl = 0x10000;
237 else
238 tl = min(length, xfer_max_sz);
239
240 dp->cmd.data |=
241 ((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
242 (mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
243 MXS_DMA_DESC_HALT_ON_TERMINATE |
244 MXS_DMA_DESC_TERMINATE_FLUSH;
245
246 data += tl;
247 length -= tl;
248
249 if (!length) {
250 dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
251
252 if (flags & SPI_XFER_END) {
253 ctrl0 &= ~SSP_CTRL0_LOCK_CS;
254 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
255 }
256 }
257
258 /*
259 * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
260 * case of MX28, write only CTRL0 in case of MX23 due
261 * to the difference in register layout. It is utterly
262 * essential that the XFER_SIZE register is written on
263 * a per-descriptor basis with the same size as is the
264 * descriptor!
265 */
266 dp->cmd.pio_words[0] = ctrl0;
267 #ifdef CONFIG_MX28
268 dp->cmd.pio_words[1] = 0;
269 dp->cmd.pio_words[2] = 0;
270 dp->cmd.pio_words[3] = tl;
271 #endif
272
273 mxs_dma_desc_append(dmach, dp);
274
275 dp++;
276 }
277
278 if (mxs_dma_go(dmach))
279 ret = -EINVAL;
280
281 /* The data arrived into DRAM, invalidate cache over them */
282 if (!write)
283 invalidate_dcache_range(dstart, dstart + cache_data_count);
284
285 return ret;
286 }
287
288 #if !CONFIG_IS_ENABLED(DM_SPI)
289 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
290 const void *dout, void *din, unsigned long flags)
291 {
292 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
293 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
294 #else
295 int mxs_spi_xfer(struct udevice *dev, unsigned int bitlen,
296 const void *dout, void *din, unsigned long flags)
297 {
298 struct udevice *bus = dev_get_parent(dev);
299 struct mxs_spi_priv *priv = dev_get_priv(bus);
300 struct mxs_ssp_regs *ssp_regs = priv->regs;
301 #endif
302 int len = bitlen / 8;
303 char dummy;
304 int write = 0;
305 char *data = NULL;
306 int dma = 1;
307
308 if (bitlen == 0) {
309 if (flags & SPI_XFER_END) {
310 din = (void *)&dummy;
311 len = 1;
312 } else
313 return 0;
314 }
315
316 /* Half-duplex only */
317 if (din && dout)
318 return -EINVAL;
319 /* No data */
320 if (!din && !dout)
321 return 0;
322
323 if (dout) {
324 data = (char *)dout;
325 write = 1;
326 } else if (din) {
327 data = (char *)din;
328 write = 0;
329 }
330
331 /*
332 * Check for alignment, if the buffer is aligned, do DMA transfer,
333 * PIO otherwise. This is a temporary workaround until proper bounce
334 * buffer is in place.
335 */
336 if (dma) {
337 if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
338 dma = 0;
339 if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
340 dma = 0;
341 }
342
343 if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
344 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
345 #if !CONFIG_IS_ENABLED(DM_SPI)
346 return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
347 #else
348 return mxs_spi_xfer_pio(priv, data, len, write, flags);
349 #endif
350 } else {
351 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
352 #if !CONFIG_IS_ENABLED(DM_SPI)
353 return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
354 #else
355 return mxs_spi_xfer_dma(priv, data, len, write, flags);
356 #endif
357 }
358 }
359
360 #if !CONFIG_IS_ENABLED(DM_SPI)
361 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
362 {
363 /* MXS SPI: 4 ports and 3 chip selects maximum */
364 if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
365 return 0;
366 else
367 return 1;
368 }
369
370 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
371 unsigned int max_hz, unsigned int mode)
372 {
373 struct mxs_spi_slave *mxs_slave;
374
375 if (!spi_cs_is_valid(bus, cs)) {
376 printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
377 return NULL;
378 }
379
380 mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
381 if (!mxs_slave)
382 return NULL;
383
384 if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
385 goto err_init;
386
387 mxs_slave->max_khz = max_hz / 1000;
388 mxs_slave->mode = mode;
389 mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
390
391 return &mxs_slave->slave;
392
393 err_init:
394 free(mxs_slave);
395 return NULL;
396 }
397
398 void spi_free_slave(struct spi_slave *slave)
399 {
400 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
401
402 free(mxs_slave);
403 }
404
405 int spi_claim_bus(struct spi_slave *slave)
406 {
407 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
408 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
409 u32 reg = 0;
410
411 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
412
413 writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
414 SSP_CTRL0_BUS_WIDTH_ONE_BIT,
415 &ssp_regs->hw_ssp_ctrl0);
416
417 reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
418 reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
419 reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
420 writel(reg, &ssp_regs->hw_ssp_ctrl1);
421
422 writel(0, &ssp_regs->hw_ssp_cmd0);
423
424 mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
425
426 return 0;
427 }
428
429 void spi_release_bus(struct spi_slave *slave)
430 {
431 }
432
433 #else /* CONFIG_DM_SPI */
434 /* Base numbers of i.MX2[38] clk for ssp0 IP block */
435 #define MXS_SSP_IMX23_CLKID_SSP0 33
436 #define MXS_SSP_IMX28_CLKID_SSP0 46
437
438 static int mxs_spi_probe(struct udevice *bus)
439 {
440 struct mxs_spi_platdata *plat = dev_get_platdata(bus);
441 struct mxs_spi_priv *priv = dev_get_priv(bus);
442 int ret;
443
444 debug("%s: probe\n", __func__);
445
446 #if CONFIG_IS_ENABLED(OF_PLATDATA)
447 struct dtd_fsl_imx_spi *dtplat = &plat->dtplat;
448 struct phandle_1_arg *p1a = &dtplat->clocks[0];
449
450 priv->regs = (struct mxs_ssp_regs *)dtplat->reg[0];
451 priv->dma_channel = dtplat->dmas[1];
452 priv->clk_id = p1a->arg[0];
453 priv->max_freq = dtplat->spi_max_frequency;
454 plat->num_cs = dtplat->num_cs;
455
456 debug("OF_PLATDATA: regs: 0x%x max freq: %d clkid: %d\n",
457 (unsigned int)priv->regs, priv->max_freq, priv->clk_id);
458 #else
459 priv->regs = (struct mxs_ssp_regs *)plat->base;
460 priv->max_freq = plat->frequency;
461
462 priv->dma_channel = plat->dma_id;
463 priv->clk_id = plat->clk_id;
464 #endif
465
466 mxs_reset_block(&priv->regs->hw_ssp_ctrl0_reg);
467
468 ret = mxs_dma_init_channel(priv->dma_channel);
469 if (ret) {
470 printf("%s: DMA init channel error %d\n", __func__, ret);
471 return ret;
472 }
473
474 return 0;
475 }
476
477 static int mxs_spi_claim_bus(struct udevice *dev)
478 {
479 struct udevice *bus = dev_get_parent(dev);
480 struct mxs_spi_priv *priv = dev_get_priv(bus);
481 struct mxs_ssp_regs *ssp_regs = priv->regs;
482 int cs = spi_chip_select(dev);
483
484 /*
485 * i.MX28 supports up to 3 CS (SSn0, SSn1, SSn2)
486 * To set them it uses following tuple (WAIT_FOR_IRQ,WAIT_FOR_CMD),
487 * where:
488 *
489 * WAIT_FOR_IRQ is bit 21 of HW_SSP_CTRL0
490 * WAIT_FOR_CMD is bit 20 (#defined as MXS_SSP_CHIPSELECT_SHIFT here) of
491 * HW_SSP_CTRL0
492 * SSn0 b00
493 * SSn1 b01
494 * SSn2 b10 (which require setting WAIT_FOR_IRQ)
495 *
496 * However, for now i.MX28 SPI driver will support up till 2 CSes
497 * (SSn0, and SSn1).
498 */
499
500 /* Ungate SSP clock and set active CS */
501 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
502 BIT(MXS_SSP_CHIPSELECT_SHIFT) |
503 SSP_CTRL0_CLKGATE, (cs << MXS_SSP_CHIPSELECT_SHIFT));
504
505 return 0;
506 }
507
508 static int mxs_spi_release_bus(struct udevice *dev)
509 {
510 struct udevice *bus = dev_get_parent(dev);
511 struct mxs_spi_priv *priv = dev_get_priv(bus);
512 struct mxs_ssp_regs *ssp_regs = priv->regs;
513
514 /* Gate SSP clock */
515 setbits_le32(&ssp_regs->hw_ssp_ctrl0, SSP_CTRL0_CLKGATE);
516
517 return 0;
518 }
519
520 static int mxs_spi_set_speed(struct udevice *bus, uint speed)
521 {
522 struct mxs_spi_priv *priv = dev_get_priv(bus);
523 #ifdef CONFIG_MX28
524 int clkid = priv->clk_id - MXS_SSP_IMX28_CLKID_SSP0;
525 #else /* CONFIG_MX23 */
526 int clkid = priv->clk_id - MXS_SSP_IMX23_CLKID_SSP0;
527 #endif
528 if (speed > priv->max_freq)
529 speed = priv->max_freq;
530
531 debug("%s speed: %u [Hz] clkid: %d\n", __func__, speed, clkid);
532 mxs_set_ssp_busclock(clkid, speed / 1000);
533
534 return 0;
535 }
536
537 static int mxs_spi_set_mode(struct udevice *bus, uint mode)
538 {
539 struct mxs_spi_priv *priv = dev_get_priv(bus);
540 struct mxs_ssp_regs *ssp_regs = priv->regs;
541 u32 reg;
542
543 priv->mode = mode;
544 debug("%s: mode 0x%x\n", __func__, mode);
545
546 reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
547 reg |= (priv->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
548 reg |= (priv->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
549 writel(reg, &ssp_regs->hw_ssp_ctrl1);
550
551 /* Single bit SPI support */
552 writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
553
554 return 0;
555 }
556
557 static const struct dm_spi_ops mxs_spi_ops = {
558 .claim_bus = mxs_spi_claim_bus,
559 .release_bus = mxs_spi_release_bus,
560 .xfer = mxs_spi_xfer,
561 .set_speed = mxs_spi_set_speed,
562 .set_mode = mxs_spi_set_mode,
563 /*
564 * cs_info is not needed, since we require all chip selects to be
565 * in the device tree explicitly
566 */
567 };
568
569 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
570 static int mxs_ofdata_to_platdata(struct udevice *bus)
571 {
572 struct mxs_spi_platdata *plat = bus->platdata;
573 u32 prop[2];
574 int ret;
575
576 plat->base = dev_read_addr(bus);
577 plat->frequency =
578 dev_read_u32_default(bus, "spi-max-frequency", 40000000);
579 plat->num_cs = dev_read_u32_default(bus, "num-cs", 2);
580
581 ret = dev_read_u32_array(bus, "dmas", prop, ARRAY_SIZE(prop));
582 if (ret) {
583 printf("%s: Reading 'dmas' property failed!\n", __func__);
584 return ret;
585 }
586 plat->dma_id = prop[1];
587
588 ret = dev_read_u32_array(bus, "clocks", prop, ARRAY_SIZE(prop));
589 if (ret) {
590 printf("%s: Reading 'clocks' property failed!\n", __func__);
591 return ret;
592 }
593 plat->clk_id = prop[1];
594
595 debug("%s: base=0x%x, max-frequency=%d num-cs=%d dma_id=%d clk_id=%d\n",
596 __func__, (uint)plat->base, plat->frequency, plat->num_cs,
597 plat->dma_id, plat->clk_id);
598
599 return 0;
600 }
601
602 static const struct udevice_id mxs_spi_ids[] = {
603 { .compatible = "fsl,imx23-spi" },
604 { .compatible = "fsl,imx28-spi" },
605 { }
606 };
607 #endif
608
609 U_BOOT_DRIVER(mxs_spi) = {
610 #ifdef CONFIG_MX28
611 .name = "fsl_imx28_spi",
612 #else /* CONFIG_MX23 */
613 .name = "fsl_imx23_spi",
614 #endif
615 .id = UCLASS_SPI,
616 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
617 .of_match = mxs_spi_ids,
618 .ofdata_to_platdata = mxs_ofdata_to_platdata,
619 #endif
620 .platdata_auto_alloc_size = sizeof(struct mxs_spi_platdata),
621 .ops = &mxs_spi_ops,
622 .priv_auto_alloc_size = sizeof(struct mxs_spi_priv),
623 .probe = mxs_spi_probe,
624 };
625 #endif
626