1 // SPDX-License-Identifier: GPL-2.0
2 /**
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
11 * to uboot.
12 *
13 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
14 */
15
16 #include <common.h>
17 #include <cpu_func.h>
18 #include <malloc.h>
19 #include <dwc3-uboot.h>
20 #include <asm/dma-mapping.h>
21 #include <linux/ioport.h>
22 #include <dm.h>
23 #include <generic-phy.h>
24 #include <linux/usb/ch9.h>
25 #include <linux/usb/gadget.h>
26
27 #include "core.h"
28 #include "gadget.h"
29 #include "io.h"
30
31 #include "linux-compat.h"
32
33 static LIST_HEAD(dwc3_list);
34 /* -------------------------------------------------------------------------- */
35
dwc3_set_mode(struct dwc3 * dwc,u32 mode)36 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
37 {
38 u32 reg;
39
40 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
41 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
42 reg |= DWC3_GCTL_PRTCAPDIR(mode);
43 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
44 }
45
46 /**
47 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
48 * @dwc: pointer to our context structure
49 */
dwc3_core_soft_reset(struct dwc3 * dwc)50 static int dwc3_core_soft_reset(struct dwc3 *dwc)
51 {
52 u32 reg;
53
54 /* Before Resetting PHY, put Core in Reset */
55 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
56 reg |= DWC3_GCTL_CORESOFTRESET;
57 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
58
59 /* Assert USB3 PHY reset */
60 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
61 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
62 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
63
64 /* Assert USB2 PHY reset */
65 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
66 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
67 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
68
69 mdelay(100);
70
71 /* Clear USB3 PHY reset */
72 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
73 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
74 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
75
76 /* Clear USB2 PHY reset */
77 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
78 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
79 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
80
81 mdelay(100);
82
83 /* After PHYs are stable we can take Core out of reset state */
84 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
85 reg &= ~DWC3_GCTL_CORESOFTRESET;
86 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
87
88 return 0;
89 }
90
91 /**
92 * dwc3_free_one_event_buffer - Frees one event buffer
93 * @dwc: Pointer to our controller context structure
94 * @evt: Pointer to event buffer to be freed
95 */
dwc3_free_one_event_buffer(struct dwc3 * dwc,struct dwc3_event_buffer * evt)96 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
97 struct dwc3_event_buffer *evt)
98 {
99 dma_free_coherent(evt->buf);
100 }
101
102 /**
103 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
104 * @dwc: Pointer to our controller context structure
105 * @length: size of the event buffer
106 *
107 * Returns a pointer to the allocated event buffer structure on success
108 * otherwise ERR_PTR(errno).
109 */
dwc3_alloc_one_event_buffer(struct dwc3 * dwc,unsigned length)110 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
111 unsigned length)
112 {
113 struct dwc3_event_buffer *evt;
114
115 evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt),
116 GFP_KERNEL);
117 if (!evt)
118 return ERR_PTR(-ENOMEM);
119
120 evt->dwc = dwc;
121 evt->length = length;
122 evt->buf = dma_alloc_coherent(length,
123 (unsigned long *)&evt->dma);
124 if (!evt->buf)
125 return ERR_PTR(-ENOMEM);
126
127 dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
128
129 return evt;
130 }
131
132 /**
133 * dwc3_free_event_buffers - frees all allocated event buffers
134 * @dwc: Pointer to our controller context structure
135 */
dwc3_free_event_buffers(struct dwc3 * dwc)136 static void dwc3_free_event_buffers(struct dwc3 *dwc)
137 {
138 struct dwc3_event_buffer *evt;
139 int i;
140
141 for (i = 0; i < dwc->num_event_buffers; i++) {
142 evt = dwc->ev_buffs[i];
143 if (evt)
144 dwc3_free_one_event_buffer(dwc, evt);
145 }
146 }
147
148 /**
149 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
150 * @dwc: pointer to our controller context structure
151 * @length: size of event buffer
152 *
153 * Returns 0 on success otherwise negative errno. In the error case, dwc
154 * may contain some buffers allocated but not all which were requested.
155 */
dwc3_alloc_event_buffers(struct dwc3 * dwc,unsigned length)156 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
157 {
158 int num;
159 int i;
160
161 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
162 dwc->num_event_buffers = num;
163
164 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
165 sizeof(*dwc->ev_buffs) * num);
166 if (!dwc->ev_buffs)
167 return -ENOMEM;
168
169 for (i = 0; i < num; i++) {
170 struct dwc3_event_buffer *evt;
171
172 evt = dwc3_alloc_one_event_buffer(dwc, length);
173 if (IS_ERR(evt)) {
174 dev_err(dwc->dev, "can't allocate event buffer\n");
175 return PTR_ERR(evt);
176 }
177 dwc->ev_buffs[i] = evt;
178 }
179
180 return 0;
181 }
182
183 /**
184 * dwc3_event_buffers_setup - setup our allocated event buffers
185 * @dwc: pointer to our controller context structure
186 *
187 * Returns 0 on success otherwise negative errno.
188 */
dwc3_event_buffers_setup(struct dwc3 * dwc)189 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
190 {
191 struct dwc3_event_buffer *evt;
192 int n;
193
194 for (n = 0; n < dwc->num_event_buffers; n++) {
195 evt = dwc->ev_buffs[n];
196 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
197 evt->buf, (unsigned long long) evt->dma,
198 evt->length);
199
200 evt->lpos = 0;
201
202 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
203 lower_32_bits(evt->dma));
204 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
205 upper_32_bits(evt->dma));
206 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
207 DWC3_GEVNTSIZ_SIZE(evt->length));
208 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
209 }
210
211 return 0;
212 }
213
dwc3_event_buffers_cleanup(struct dwc3 * dwc)214 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
215 {
216 struct dwc3_event_buffer *evt;
217 int n;
218
219 for (n = 0; n < dwc->num_event_buffers; n++) {
220 evt = dwc->ev_buffs[n];
221
222 evt->lpos = 0;
223
224 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
225 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
226 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
227 | DWC3_GEVNTSIZ_SIZE(0));
228 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
229 }
230 }
231
dwc3_alloc_scratch_buffers(struct dwc3 * dwc)232 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
233 {
234 if (!dwc->has_hibernation)
235 return 0;
236
237 if (!dwc->nr_scratch)
238 return 0;
239
240 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
241 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
242 if (!dwc->scratchbuf)
243 return -ENOMEM;
244
245 return 0;
246 }
247
dwc3_setup_scratch_buffers(struct dwc3 * dwc)248 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
249 {
250 dma_addr_t scratch_addr;
251 u32 param;
252 int ret;
253
254 if (!dwc->has_hibernation)
255 return 0;
256
257 if (!dwc->nr_scratch)
258 return 0;
259
260 scratch_addr = dma_map_single(dwc->scratchbuf,
261 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
262 DMA_BIDIRECTIONAL);
263 if (dma_mapping_error(dwc->dev, scratch_addr)) {
264 dev_err(dwc->dev, "failed to map scratch buffer\n");
265 ret = -EFAULT;
266 goto err0;
267 }
268
269 dwc->scratch_addr = scratch_addr;
270
271 param = lower_32_bits(scratch_addr);
272
273 ret = dwc3_send_gadget_generic_command(dwc,
274 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
275 if (ret < 0)
276 goto err1;
277
278 param = upper_32_bits(scratch_addr);
279
280 ret = dwc3_send_gadget_generic_command(dwc,
281 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
282 if (ret < 0)
283 goto err1;
284
285 return 0;
286
287 err1:
288 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch *
289 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
290
291 err0:
292 return ret;
293 }
294
dwc3_free_scratch_buffers(struct dwc3 * dwc)295 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
296 {
297 if (!dwc->has_hibernation)
298 return;
299
300 if (!dwc->nr_scratch)
301 return;
302
303 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch *
304 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
305 kfree(dwc->scratchbuf);
306 }
307
dwc3_core_num_eps(struct dwc3 * dwc)308 static void dwc3_core_num_eps(struct dwc3 *dwc)
309 {
310 struct dwc3_hwparams *parms = &dwc->hwparams;
311
312 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
313 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
314
315 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
316 dwc->num_in_eps, dwc->num_out_eps);
317 }
318
dwc3_cache_hwparams(struct dwc3 * dwc)319 static void dwc3_cache_hwparams(struct dwc3 *dwc)
320 {
321 struct dwc3_hwparams *parms = &dwc->hwparams;
322
323 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
324 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
325 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
326 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
327 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
328 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
329 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
330 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
331 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
332 }
333
334 /**
335 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
336 * @dwc: Pointer to our controller context structure
337 */
dwc3_phy_setup(struct dwc3 * dwc)338 static void dwc3_phy_setup(struct dwc3 *dwc)
339 {
340 u32 reg;
341
342 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
343
344 /*
345 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
346 * to '0' during coreConsultant configuration. So default value
347 * will be '0' when the core is reset. Application needs to set it
348 * to '1' after the core initialization is completed.
349 */
350 if (dwc->revision > DWC3_REVISION_194A)
351 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
352
353 if (dwc->u2ss_inp3_quirk)
354 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
355
356 if (dwc->req_p1p2p3_quirk)
357 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
358
359 if (dwc->del_p1p2p3_quirk)
360 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
361
362 if (dwc->del_phy_power_chg_quirk)
363 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
364
365 if (dwc->lfps_filter_quirk)
366 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
367
368 if (dwc->rx_detect_poll_quirk)
369 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
370
371 if (dwc->tx_de_emphasis_quirk)
372 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
373
374 if (dwc->dis_u3_susphy_quirk)
375 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
376
377 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
378
379 mdelay(100);
380
381 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
382
383 /*
384 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
385 * '0' during coreConsultant configuration. So default value will
386 * be '0' when the core is reset. Application needs to set it to
387 * '1' after the core initialization is completed.
388 */
389 if (dwc->revision > DWC3_REVISION_194A)
390 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
391
392 if (dwc->dis_u2_susphy_quirk)
393 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
394
395 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
396
397 mdelay(100);
398 }
399
400 /**
401 * dwc3_core_init - Low-level initialization of DWC3 Core
402 * @dwc: Pointer to our controller context structure
403 *
404 * Returns 0 on success otherwise negative errno.
405 */
dwc3_core_init(struct dwc3 * dwc)406 static int dwc3_core_init(struct dwc3 *dwc)
407 {
408 unsigned long timeout;
409 u32 hwparams4 = dwc->hwparams.hwparams4;
410 u32 reg;
411 int ret;
412
413 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
414 /* This should read as U3 followed by revision number */
415 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
416 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
417 ret = -ENODEV;
418 goto err0;
419 }
420 dwc->revision = reg;
421
422 /* Handle USB2.0-only core configuration */
423 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
424 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
425 if (dwc->maximum_speed == USB_SPEED_SUPER)
426 dwc->maximum_speed = USB_SPEED_HIGH;
427 }
428
429 /* issue device SoftReset too */
430 timeout = 5000;
431 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
432 while (timeout--) {
433 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
434 if (!(reg & DWC3_DCTL_CSFTRST))
435 break;
436 };
437
438 if (!timeout) {
439 dev_err(dwc->dev, "Reset Timed Out\n");
440 ret = -ETIMEDOUT;
441 goto err0;
442 }
443
444 dwc3_phy_setup(dwc);
445
446 ret = dwc3_core_soft_reset(dwc);
447 if (ret)
448 goto err0;
449
450 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
451 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
452
453 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
454 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
455 /**
456 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
457 * issue which would cause xHCI compliance tests to fail.
458 *
459 * Because of that we cannot enable clock gating on such
460 * configurations.
461 *
462 * Refers to:
463 *
464 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
465 * SOF/ITP Mode Used
466 */
467 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
468 dwc->dr_mode == USB_DR_MODE_OTG) &&
469 (dwc->revision >= DWC3_REVISION_210A &&
470 dwc->revision <= DWC3_REVISION_250A))
471 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
472 else
473 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
474 break;
475 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
476 /* enable hibernation here */
477 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
478
479 /*
480 * REVISIT Enabling this bit so that host-mode hibernation
481 * will work. Device-mode hibernation is not yet implemented.
482 */
483 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
484 break;
485 default:
486 dev_dbg(dwc->dev, "No power optimization available\n");
487 }
488
489 /* check if current dwc3 is on simulation board */
490 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
491 dev_dbg(dwc->dev, "it is on FPGA board\n");
492 dwc->is_fpga = true;
493 }
494
495 if(dwc->disable_scramble_quirk && !dwc->is_fpga)
496 WARN(true,
497 "disable_scramble cannot be used on non-FPGA builds\n");
498
499 if (dwc->disable_scramble_quirk && dwc->is_fpga)
500 reg |= DWC3_GCTL_DISSCRAMBLE;
501 else
502 reg &= ~DWC3_GCTL_DISSCRAMBLE;
503
504 if (dwc->u2exit_lfps_quirk)
505 reg |= DWC3_GCTL_U2EXIT_LFPS;
506
507 /*
508 * WORKAROUND: DWC3 revisions <1.90a have a bug
509 * where the device can fail to connect at SuperSpeed
510 * and falls back to high-speed mode which causes
511 * the device to enter a Connect/Disconnect loop
512 */
513 if (dwc->revision < DWC3_REVISION_190A)
514 reg |= DWC3_GCTL_U2RSTECN;
515
516 dwc3_core_num_eps(dwc);
517
518 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
519
520 ret = dwc3_alloc_scratch_buffers(dwc);
521 if (ret)
522 goto err0;
523
524 ret = dwc3_setup_scratch_buffers(dwc);
525 if (ret)
526 goto err1;
527
528 return 0;
529
530 err1:
531 dwc3_free_scratch_buffers(dwc);
532
533 err0:
534 return ret;
535 }
536
dwc3_core_exit(struct dwc3 * dwc)537 static void dwc3_core_exit(struct dwc3 *dwc)
538 {
539 dwc3_free_scratch_buffers(dwc);
540 }
541
dwc3_core_init_mode(struct dwc3 * dwc)542 static int dwc3_core_init_mode(struct dwc3 *dwc)
543 {
544 int ret;
545
546 switch (dwc->dr_mode) {
547 case USB_DR_MODE_PERIPHERAL:
548 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
549 ret = dwc3_gadget_init(dwc);
550 if (ret) {
551 dev_err(dev, "failed to initialize gadget\n");
552 return ret;
553 }
554 break;
555 case USB_DR_MODE_HOST:
556 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
557 ret = dwc3_host_init(dwc);
558 if (ret) {
559 dev_err(dev, "failed to initialize host\n");
560 return ret;
561 }
562 break;
563 case USB_DR_MODE_OTG:
564 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
565 ret = dwc3_host_init(dwc);
566 if (ret) {
567 dev_err(dev, "failed to initialize host\n");
568 return ret;
569 }
570
571 ret = dwc3_gadget_init(dwc);
572 if (ret) {
573 dev_err(dev, "failed to initialize gadget\n");
574 return ret;
575 }
576 break;
577 default:
578 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
579 return -EINVAL;
580 }
581
582 return 0;
583 }
584
dwc3_gadget_run(struct dwc3 * dwc)585 static void dwc3_gadget_run(struct dwc3 *dwc)
586 {
587 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
588 mdelay(100);
589 }
590
dwc3_core_exit_mode(struct dwc3 * dwc)591 static void dwc3_core_exit_mode(struct dwc3 *dwc)
592 {
593 switch (dwc->dr_mode) {
594 case USB_DR_MODE_PERIPHERAL:
595 dwc3_gadget_exit(dwc);
596 break;
597 case USB_DR_MODE_HOST:
598 dwc3_host_exit(dwc);
599 break;
600 case USB_DR_MODE_OTG:
601 dwc3_host_exit(dwc);
602 dwc3_gadget_exit(dwc);
603 break;
604 default:
605 /* do nothing */
606 break;
607 }
608
609 /*
610 * switch back to peripheral mode
611 * This enables the phy to enter idle and then, if enabled, suspend.
612 */
613 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
614 dwc3_gadget_run(dwc);
615 }
616
dwc3_uboot_hsphy_mode(struct dwc3_device * dwc3_dev,struct dwc3 * dwc)617 static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
618 struct dwc3 *dwc)
619 {
620 enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode;
621 u32 reg;
622
623 /* Set dwc3 usb2 phy config */
624 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
625
626 switch (hsphy_mode) {
627 case USBPHY_INTERFACE_MODE_UTMI:
628 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
629 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
630 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
631 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
632 break;
633 case USBPHY_INTERFACE_MODE_UTMIW:
634 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
635 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
636 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
637 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
638 break;
639 default:
640 break;
641 }
642
643 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
644 }
645
646 #define DWC3_ALIGN_MASK (16 - 1)
647
648 /**
649 * dwc3_uboot_init - dwc3 core uboot initialization code
650 * @dwc3_dev: struct dwc3_device containing initialization data
651 *
652 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
653 * kernel driver). Pointer to dwc3_device should be passed containing
654 * base address and other initialization data. Returns '0' on success and
655 * a negative value on failure.
656 *
657 * Generally called from board_usb_init() implemented in board file.
658 */
dwc3_uboot_init(struct dwc3_device * dwc3_dev)659 int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
660 {
661 struct dwc3 *dwc;
662 struct device *dev = NULL;
663 u8 lpm_nyet_threshold;
664 u8 tx_de_emphasis;
665 u8 hird_threshold;
666
667 int ret;
668
669 void *mem;
670
671 mem = devm_kzalloc((struct udevice *)dev,
672 sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
673 if (!mem)
674 return -ENOMEM;
675
676 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
677 dwc->mem = mem;
678
679 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
680 DWC3_GLOBALS_REGS_START);
681
682 /* default to highest possible threshold */
683 lpm_nyet_threshold = 0xff;
684
685 /* default to -3.5dB de-emphasis */
686 tx_de_emphasis = 1;
687
688 /*
689 * default to assert utmi_sleep_n and use maximum allowed HIRD
690 * threshold value of 0b1100
691 */
692 hird_threshold = 12;
693
694 dwc->maximum_speed = dwc3_dev->maximum_speed;
695 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
696 if (dwc3_dev->lpm_nyet_threshold)
697 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
698 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
699 if (dwc3_dev->hird_threshold)
700 hird_threshold = dwc3_dev->hird_threshold;
701
702 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
703 dwc->dr_mode = dwc3_dev->dr_mode;
704
705 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
706 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
707 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
708 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
709 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
710 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
711 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
712 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
713 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
714 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
715
716 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
717 if (dwc3_dev->tx_de_emphasis)
718 tx_de_emphasis = dwc3_dev->tx_de_emphasis;
719
720 /* default to superspeed if no maximum_speed passed */
721 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
722 dwc->maximum_speed = USB_SPEED_SUPER;
723
724 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
725 dwc->tx_de_emphasis = tx_de_emphasis;
726
727 dwc->hird_threshold = hird_threshold
728 | (dwc->is_utmi_l1_suspend << 4);
729
730 dwc->index = dwc3_dev->index;
731
732 dwc3_cache_hwparams(dwc);
733
734 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
735 if (ret) {
736 dev_err(dwc->dev, "failed to allocate event buffers\n");
737 return -ENOMEM;
738 }
739
740 if (!IS_ENABLED(CONFIG_USB_DWC3_GADGET))
741 dwc->dr_mode = USB_DR_MODE_HOST;
742 else if (!IS_ENABLED(CONFIG_USB_HOST))
743 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
744
745 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
746 dwc->dr_mode = USB_DR_MODE_OTG;
747
748 ret = dwc3_core_init(dwc);
749 if (ret) {
750 dev_err(dev, "failed to initialize core\n");
751 goto err0;
752 }
753
754 dwc3_uboot_hsphy_mode(dwc3_dev, dwc);
755
756 ret = dwc3_event_buffers_setup(dwc);
757 if (ret) {
758 dev_err(dwc->dev, "failed to setup event buffers\n");
759 goto err1;
760 }
761
762 ret = dwc3_core_init_mode(dwc);
763 if (ret)
764 goto err2;
765
766 list_add_tail(&dwc->list, &dwc3_list);
767
768 return 0;
769
770 err2:
771 dwc3_event_buffers_cleanup(dwc);
772
773 err1:
774 dwc3_core_exit(dwc);
775
776 err0:
777 dwc3_free_event_buffers(dwc);
778
779 return ret;
780 }
781
782 /**
783 * dwc3_uboot_exit - dwc3 core uboot cleanup code
784 * @index: index of this controller
785 *
786 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
787 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
788 * should be passed and should match with the index passed in
789 * dwc3_device during init.
790 *
791 * Generally called from board file.
792 */
dwc3_uboot_exit(int index)793 void dwc3_uboot_exit(int index)
794 {
795 struct dwc3 *dwc;
796
797 list_for_each_entry(dwc, &dwc3_list, list) {
798 if (dwc->index != index)
799 continue;
800
801 dwc3_core_exit_mode(dwc);
802 dwc3_event_buffers_cleanup(dwc);
803 dwc3_free_event_buffers(dwc);
804 dwc3_core_exit(dwc);
805 list_del(&dwc->list);
806 kfree(dwc->mem);
807 break;
808 }
809 }
810
811 /**
812 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
813 * @index: index of this controller
814 *
815 * Invokes dwc3 gadget interrupts.
816 *
817 * Generally called from board file.
818 */
dwc3_uboot_handle_interrupt(int index)819 void dwc3_uboot_handle_interrupt(int index)
820 {
821 struct dwc3 *dwc = NULL;
822
823 list_for_each_entry(dwc, &dwc3_list, list) {
824 if (dwc->index != index)
825 continue;
826
827 dwc3_gadget_uboot_handle_interrupt(dwc);
828 break;
829 }
830 }
831
832 MODULE_ALIAS("platform:dwc3");
833 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
834 MODULE_LICENSE("GPL v2");
835 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
836
837 #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
dwc3_setup_phy(struct udevice * dev,struct phy ** array,int * num_phys)838 int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys)
839 {
840 int i, ret, count;
841 struct phy *usb_phys;
842
843 /* Return if no phy declared */
844 if (!dev_read_prop(dev, "phys", NULL))
845 return 0;
846 count = dev_count_phandle_with_args(dev, "phys", "#phy-cells");
847 if (count <= 0)
848 return count;
849
850 usb_phys = devm_kcalloc(dev, count, sizeof(struct phy),
851 GFP_KERNEL);
852 if (!usb_phys)
853 return -ENOMEM;
854
855 for (i = 0; i < count; i++) {
856 ret = generic_phy_get_by_index(dev, i, &usb_phys[i]);
857 if (ret && ret != -ENOENT) {
858 pr_err("Failed to get USB PHY%d for %s\n",
859 i, dev->name);
860 return ret;
861 }
862 }
863
864 for (i = 0; i < count; i++) {
865 ret = generic_phy_init(&usb_phys[i]);
866 if (ret) {
867 pr_err("Can't init USB PHY%d for %s\n",
868 i, dev->name);
869 goto phys_init_err;
870 }
871 }
872
873 for (i = 0; i < count; i++) {
874 ret = generic_phy_power_on(&usb_phys[i]);
875 if (ret) {
876 pr_err("Can't power USB PHY%d for %s\n",
877 i, dev->name);
878 goto phys_poweron_err;
879 }
880 }
881
882 *array = usb_phys;
883 *num_phys = count;
884 return 0;
885
886 phys_poweron_err:
887 for (i = count - 1; i >= 0; i--)
888 generic_phy_power_off(&usb_phys[i]);
889
890 for (i = 0; i < count; i++)
891 generic_phy_exit(&usb_phys[i]);
892
893 return ret;
894
895 phys_init_err:
896 for (; i >= 0; i--)
897 generic_phy_exit(&usb_phys[i]);
898
899 return ret;
900 }
901
dwc3_shutdown_phy(struct udevice * dev,struct phy * usb_phys,int num_phys)902 int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys)
903 {
904 int i, ret;
905
906 for (i = 0; i < num_phys; i++) {
907 if (!generic_phy_valid(&usb_phys[i]))
908 continue;
909
910 ret = generic_phy_power_off(&usb_phys[i]);
911 ret |= generic_phy_exit(&usb_phys[i]);
912 if (ret) {
913 pr_err("Can't shutdown USB PHY%d for %s\n",
914 i, dev->name);
915 }
916 }
917
918 return 0;
919 }
920 #endif
921
922 #if CONFIG_IS_ENABLED(DM_USB)
dwc3_of_parse(struct dwc3 * dwc)923 void dwc3_of_parse(struct dwc3 *dwc)
924 {
925 const u8 *tmp;
926 struct udevice *dev = dwc->dev;
927 u8 lpm_nyet_threshold;
928 u8 tx_de_emphasis;
929 u8 hird_threshold;
930
931 /* default to highest possible threshold */
932 lpm_nyet_threshold = 0xff;
933
934 /* default to -3.5dB de-emphasis */
935 tx_de_emphasis = 1;
936
937 /*
938 * default to assert utmi_sleep_n and use maximum allowed HIRD
939 * threshold value of 0b1100
940 */
941 hird_threshold = 12;
942
943 dwc->has_lpm_erratum = dev_read_bool(dev,
944 "snps,has-lpm-erratum");
945 tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
946 if (tmp)
947 lpm_nyet_threshold = *tmp;
948
949 dwc->is_utmi_l1_suspend = dev_read_bool(dev,
950 "snps,is-utmi-l1-suspend");
951 tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
952 if (tmp)
953 hird_threshold = *tmp;
954
955 dwc->disable_scramble_quirk = dev_read_bool(dev,
956 "snps,disable_scramble_quirk");
957 dwc->u2exit_lfps_quirk = dev_read_bool(dev,
958 "snps,u2exit_lfps_quirk");
959 dwc->u2ss_inp3_quirk = dev_read_bool(dev,
960 "snps,u2ss_inp3_quirk");
961 dwc->req_p1p2p3_quirk = dev_read_bool(dev,
962 "snps,req_p1p2p3_quirk");
963 dwc->del_p1p2p3_quirk = dev_read_bool(dev,
964 "snps,del_p1p2p3_quirk");
965 dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
966 "snps,del_phy_power_chg_quirk");
967 dwc->lfps_filter_quirk = dev_read_bool(dev,
968 "snps,lfps_filter_quirk");
969 dwc->rx_detect_poll_quirk = dev_read_bool(dev,
970 "snps,rx_detect_poll_quirk");
971 dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
972 "snps,dis_u3_susphy_quirk");
973 dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
974 "snps,dis_u2_susphy_quirk");
975 dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
976 "snps,tx_de_emphasis_quirk");
977 tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
978 if (tmp)
979 tx_de_emphasis = *tmp;
980
981 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
982 dwc->tx_de_emphasis = tx_de_emphasis;
983
984 dwc->hird_threshold = hird_threshold
985 | (dwc->is_utmi_l1_suspend << 4);
986 }
987
dwc3_init(struct dwc3 * dwc)988 int dwc3_init(struct dwc3 *dwc)
989 {
990 int ret;
991
992 dwc3_cache_hwparams(dwc);
993
994 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
995 if (ret) {
996 dev_err(dwc->dev, "failed to allocate event buffers\n");
997 return -ENOMEM;
998 }
999
1000 ret = dwc3_core_init(dwc);
1001 if (ret) {
1002 dev_err(dev, "failed to initialize core\n");
1003 goto core_fail;
1004 }
1005
1006 ret = dwc3_event_buffers_setup(dwc);
1007 if (ret) {
1008 dev_err(dwc->dev, "failed to setup event buffers\n");
1009 goto event_fail;
1010 }
1011
1012 ret = dwc3_core_init_mode(dwc);
1013 if (ret)
1014 goto mode_fail;
1015
1016 return 0;
1017
1018 mode_fail:
1019 dwc3_event_buffers_cleanup(dwc);
1020
1021 event_fail:
1022 dwc3_core_exit(dwc);
1023
1024 core_fail:
1025 dwc3_free_event_buffers(dwc);
1026
1027 return ret;
1028 }
1029
dwc3_remove(struct dwc3 * dwc)1030 void dwc3_remove(struct dwc3 *dwc)
1031 {
1032 dwc3_core_exit_mode(dwc);
1033 dwc3_event_buffers_cleanup(dwc);
1034 dwc3_free_event_buffers(dwc);
1035 dwc3_core_exit(dwc);
1036 kfree(dwc->mem);
1037 }
1038 #endif
1039