• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /*
2  * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef IMX8M_GPC_H
8 #define IMX8M_GPC_H
9 
10 #define LPCR_A53_BSC			0x0
11 #define LPCR_A53_BSC2			0x108
12 #define LPCR_A53_AD			0x4
13 #define LPCR_M4				0x8
14 #define SLPCR				0x14
15 #define MST_CPU_MAPPING			0x18
16 #define MLPCR				0x20
17 #define PGC_ACK_SEL_A53			0x24
18 #define IMR1_CORE0_A53			0x30
19 #define IMR1_CORE1_A53			0x40
20 #define IMR1_CORE2_A53			0x1C0
21 #define IMR1_CORE3_A53			0x1D0
22 #define IMR1_CORE0_M4			0x50
23 #define SLT0_CFG			0xB0
24 #define GPC_PU_PWRHSK			0x1FC
25 #define PGC_CPU_0_1_MAPPING		0xEC
26 #define CPU_PGC_UP_TRG			0xF0
27 #define PU_PGC_UP_TRG			0xF8
28 #define CPU_PGC_DN_TRG			0xFC
29 #define PU_PGC_DN_TRG			0x104
30 #define A53_CORE0_PGC			0x800
31 #define A53_PLAT_PGC			0x900
32 #define PLAT_PGC_PCR			0x900
33 #define PGC_SCU_TIMING			0x910
34 
35 #define MASK_DSM_TRIGGER_A53		BIT(31)
36 #define IRQ_SRC_A53_WUP			BIT(30)
37 #define IRQ_SRC_A53_WUP_SHIFT		30
38 #define IRQ_SRC_C1			BIT(29)
39 #define IRQ_SRC_C0			BIT(28)
40 #define IRQ_SRC_C3			BIT(23)
41 #define IRQ_SRC_C2			BIT(22)
42 #define CPU_CLOCK_ON_LPM		BIT(14)
43 #define A53_CLK_ON_LPM			BIT(14)
44 #define MASTER0_LPM_HSK			BIT(6)
45 
46 #define L2PGE				BIT(31)
47 #define EN_L2_WFI_PDN			BIT(5)
48 #define EN_PLAT_PDN			BIT(4)
49 
50 #define SLPCR_EN_DSM			BIT(31)
51 #define SLPCR_RBC_EN			BIT(30)
52 #define SLPCR_A53_FASTWUP_STOP_MODE	BIT(17)
53 #define SLPCR_A53_FASTWUP_WAIT_MODE	BIT(16)
54 #define SLPCR_VSTBY			BIT(2)
55 #define SLPCR_SBYOS			BIT(1)
56 #define SLPCR_BYPASS_PMIC_READY		BIT(0)
57 #define SLPCR_RBC_COUNT_SHIFT		24
58 #define SLPCR_STBY_COUNT_SHFT		3
59 
60 #define A53_DUMMY_PDN_ACK		BIT(15)
61 #define A53_DUMMY_PUP_ACK		BIT(31)
62 #define A53_PLAT_PDN_ACK		BIT(2)
63 #define A53_PLAT_PUP_ACK		BIT(18)
64 
65 #define PLAT_PUP_SLT_CTRL		BIT(9)
66 #define PLAT_PDN_SLT_CTRL		BIT(8)
67 
68 #define SLT_PLAT_PDN			BIT(8)
69 #define SLT_PLAT_PUP			BIT(9)
70 
71 #define MASTER1_MAPPING			BIT(1)
72 #define MASTER2_MAPPING			BIT(2)
73 
74 /* helper macro */
75 #define A53_LPM_MASK	U(0xF)
76 #define A53_LPM_WAIT	U(0x5)
77 #define A53_LPM_STOP	U(0xA)
78 #define LPM_MODE(local_state)		((local_state) == PLAT_WAIT_RET_STATE ? A53_LPM_WAIT : A53_LPM_STOP)
79 
80 #define DSM_MODE_MASK	BIT(31)
81 
82 #define A53_CORE_WUP_SRC(core_id)	(1 << ((core_id) < 2 ? 28 + (core_id) : 22 + (core_id) - 2))
83 #define COREx_PGC_PCR(core_id)		(0x800 + (core_id) * 0x40)
84 #define COREx_WFI_PDN(core_id)		(1 << ((core_id) < 2 ? (core_id) * 2 : ((core_id) - 2) * 2 + 16))
85 #define COREx_IRQ_WUP(core_id)		((core_id) < 2 ? (1 << ((core_id) * 2 + 8)) : (1 << ((core_id) * 2 + 20)))
86 #define COREx_LPM_PUP(core_id)		((core_id) < 2 ? (1 << ((core_id) * 2 + 9)) : (1 << ((core_id) * 2 + 21)))
87 #define SLTx_CFG(n)			((SLT0_CFG + ((n) * 4)))
88 #define SLT_COREx_PUP(core_id)		(0x2 << ((core_id) * 2))
89 
90 #define IRQ_IMR_NUM	4
91 #define IMR_MASK_ALL	0xffffffff
92 
93 /* function declare */
94 void imx_gpc_init(void);
95 void imx_set_cpu_secure_entry(unsigned int core_index, uintptr_t sec_entrypoint);
96 void imx_set_cpu_pwr_off(unsigned int core_index);
97 void imx_set_cpu_pwr_on(unsigned int core_index);
98 void imx_set_cpu_lpm(unsigned int core_index, bool pdn);
99 void imx_set_cluster_standby(bool retention);
100 void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state);
101 void imx_noc_slot_config(bool pdn);
102 void imx_set_sys_wakeup(unsigned int last_core, bool pdn);
103 void imx_set_sys_lpm(unsigned last_core, bool retention);
104 void imx_set_rbc_count(void);
105 void imx_clear_rbc_count(void);
106 
107 #endif /*IMX8M_GPC_H */
108