1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 #define CONFIG_ARMV7_PSCI_1_0 10 11 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 12 13 #define CONFIG_SYS_FSL_CLK 14 15 #define CONFIG_SKIP_LOWLEVEL_INIT 16 #define CONFIG_DEEP_SLEEP 17 18 /* 19 * Size of malloc() pool 20 */ 21 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 22 23 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 24 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 25 26 #define CONFIG_SYS_CLK_FREQ 100000000 27 #define CONFIG_DDR_CLK_FREQ 100000000 28 29 #define DDR_SDRAM_CFG 0x470c0008 30 #define DDR_CS0_BNDS 0x008000bf 31 #define DDR_CS0_CONFIG 0x80014302 32 #define DDR_TIMING_CFG_0 0x50550004 33 #define DDR_TIMING_CFG_1 0xbcb38c56 34 #define DDR_TIMING_CFG_2 0x0040d120 35 #define DDR_TIMING_CFG_3 0x010e1000 36 #define DDR_TIMING_CFG_4 0x00000001 37 #define DDR_TIMING_CFG_5 0x03401400 38 #define DDR_SDRAM_CFG_2 0x00401010 39 #define DDR_SDRAM_MODE 0x00061c60 40 #define DDR_SDRAM_MODE_2 0x00180000 41 #define DDR_SDRAM_INTERVAL 0x18600618 42 #define DDR_DDR_WRLVL_CNTL 0x8655f605 43 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 44 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 45 #define DDR_DDR_CDR1 0x80040000 46 #define DDR_DDR_CDR2 0x00000001 47 #define DDR_SDRAM_CLK_CNTL 0x02000000 48 #define DDR_DDR_ZQ_CNTL 0x89080600 49 #define DDR_CS0_CONFIG_2 0 50 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 51 #define SDRAM_CFG2_D_INIT 0x00000010 52 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 53 #define SDRAM_CFG2_FRC_SR 0x80000000 54 #define SDRAM_CFG_BI 0x00000001 55 56 #ifdef CONFIG_RAMBOOT_PBL 57 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 58 #endif 59 60 #ifdef CONFIG_SD_BOOT 61 #ifdef CONFIG_SD_BOOT_QSPI 62 #define CONFIG_SYS_FSL_PBL_RCW \ 63 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg 64 #else 65 #define CONFIG_SYS_FSL_PBL_RCW \ 66 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg 67 #endif 68 69 #ifdef CONFIG_NXP_ESBC 70 /* 71 * HDR would be appended at end of image and copied to DDR along 72 * with U-Boot image. 73 */ 74 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 75 #endif /* ifdef CONFIG_NXP_ESBC */ 76 77 #define CONFIG_SPL_MAX_SIZE 0x1a000 78 #define CONFIG_SPL_STACK 0x1001d000 79 #define CONFIG_SPL_PAD_TO 0x1c000 80 81 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 82 CONFIG_SYS_MONITOR_LEN) 83 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 84 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 85 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 86 87 #ifdef CONFIG_U_BOOT_HDR_SIZE 88 /* 89 * HDR would be appended at end of image and copied to DDR along 90 * with U-Boot image. Here u-boot max. size is 512K. So if binary 91 * size increases then increase this size in case of secure boot as 92 * it uses raw u-boot image instead of fit image. 93 */ 94 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 95 #else 96 #define CONFIG_SYS_MONITOR_LEN 0x100000 97 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 98 #endif 99 100 #define PHYS_SDRAM 0x80000000 101 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 102 103 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 104 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 105 106 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 107 108 /* 109 * IFC Definitions 110 */ 111 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 112 #define CONFIG_FSL_IFC 113 #define CONFIG_SYS_FLASH_BASE 0x60000000 114 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 115 116 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 117 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 118 CSPR_PORT_SIZE_16 | \ 119 CSPR_MSEL_NOR | \ 120 CSPR_V) 121 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 122 123 /* NOR Flash Timing Params */ 124 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 125 CSOR_NOR_TRHZ_80) 126 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 127 FTIM0_NOR_TEADC(0x5) | \ 128 FTIM0_NOR_TAVDS(0x0) | \ 129 FTIM0_NOR_TEAHC(0x5)) 130 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 131 FTIM1_NOR_TRAD_NOR(0x1A) | \ 132 FTIM1_NOR_TSEQRAD_NOR(0x13)) 133 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 134 FTIM2_NOR_TCH(0x4) | \ 135 FTIM2_NOR_TWP(0x1c) | \ 136 FTIM2_NOR_TWPH(0x0e)) 137 #define CONFIG_SYS_NOR_FTIM3 0 138 139 #define CONFIG_SYS_FLASH_QUIET_TEST 140 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 141 142 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 143 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 144 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 145 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 146 147 #define CONFIG_SYS_FLASH_EMPTY_INFO 148 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 149 150 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 151 #define CONFIG_SYS_WRITE_SWAPPED_DATA 152 #endif 153 154 /* CPLD */ 155 156 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 157 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 158 159 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 160 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 161 CSPR_PORT_SIZE_8 | \ 162 CSPR_MSEL_GPCM | \ 163 CSPR_V) 164 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 165 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 166 CSOR_NOR_NOR_MODE_AVD_NOR | \ 167 CSOR_NOR_TRHZ_80) 168 169 /* CPLD Timing parameters for IFC GPCM */ 170 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 171 FTIM0_GPCM_TEADC(0xf) | \ 172 FTIM0_GPCM_TEAHC(0xf)) 173 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 174 FTIM1_GPCM_TRAD(0x3f)) 175 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 176 FTIM2_GPCM_TCH(0xf) | \ 177 FTIM2_GPCM_TWP(0xff)) 178 #define CONFIG_SYS_FPGA_FTIM3 0x0 179 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 180 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 181 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 182 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 183 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 184 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 185 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 186 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 187 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 188 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 189 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 190 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 191 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 192 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 193 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 194 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 195 196 /* 197 * Serial Port 198 */ 199 #ifdef CONFIG_LPUART 200 #define CONFIG_LPUART_32B_REG 201 #else 202 #define CONFIG_SYS_NS16550_SERIAL 203 #ifndef CONFIG_DM_SERIAL 204 #define CONFIG_SYS_NS16550_REG_SIZE 1 205 #endif 206 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 207 #endif 208 209 /* 210 * I2C 211 */ 212 #define CONFIG_SYS_I2C 213 #define CONFIG_SYS_I2C_MXC 214 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 215 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 216 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 217 218 /* EEPROM */ 219 #define CONFIG_ID_EEPROM 220 #define CONFIG_SYS_I2C_EEPROM_NXID 221 #define CONFIG_SYS_EEPROM_BUS_NUM 1 222 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 223 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 224 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 225 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 226 227 /* 228 * MMC 229 */ 230 231 /* SPI */ 232 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 233 /* QSPI */ 234 #define QSPI0_AMBA_BASE 0x40000000 235 #define FSL_QSPI_FLASH_SIZE (1 << 24) 236 #define FSL_QSPI_FLASH_NUM 2 237 238 /* DSPI */ 239 #endif 240 241 /* DM SPI */ 242 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 243 #define CONFIG_DM_SPI_FLASH 244 #endif 245 246 /* 247 * Video 248 */ 249 #ifdef CONFIG_VIDEO_FSL_DCU_FB 250 #define CONFIG_VIDEO_LOGO 251 #define CONFIG_VIDEO_BMP_LOGO 252 253 #define CONFIG_FSL_DCU_SII9022A 254 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 255 #define CONFIG_SYS_I2C_DVI_ADDR 0x39 256 #endif 257 258 /* 259 * eTSEC 260 */ 261 262 #ifdef CONFIG_TSEC_ENET 263 #define CONFIG_ETHPRIME "ethernet@2d10000" 264 #endif 265 266 /* PCIe */ 267 #define CONFIG_PCIE1 /* PCIE controller 1 */ 268 #define CONFIG_PCIE2 /* PCIE controller 2 */ 269 270 #ifdef CONFIG_PCI 271 #define CONFIG_PCI_SCAN_SHOW 272 #endif 273 274 #define CONFIG_CMDLINE_TAG 275 276 #define CONFIG_PEN_ADDR_BIG_ENDIAN 277 #define CONFIG_LAYERSCAPE_NS_ACCESS 278 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 279 #define COUNTER_FREQUENCY 12500000 280 281 #define CONFIG_HWCONFIG 282 #define HWCONFIG_BUFFER_SIZE 256 283 284 #define CONFIG_FSL_DEVICE_DISABLE 285 286 #define BOOT_TARGET_DEVICES(func) \ 287 func(MMC, mmc, 0) \ 288 func(USB, usb, 0) \ 289 func(DHCP, dhcp, na) 290 #include <config_distro_bootcmd.h> 291 292 #ifdef CONFIG_LPUART 293 #define CONFIG_EXTRA_ENV_SETTINGS \ 294 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 295 "initrd_high=0xffffffff\0" \ 296 "fdt_high=0xffffffff\0" \ 297 "fdt_addr=0x64f00000\0" \ 298 "kernel_addr=0x65000000\0" \ 299 "scriptaddr=0x80000000\0" \ 300 "scripthdraddr=0x80080000\0" \ 301 "fdtheader_addr_r=0x80100000\0" \ 302 "kernelheader_addr_r=0x80200000\0" \ 303 "kernel_addr_r=0x81000000\0" \ 304 "fdt_addr_r=0x90000000\0" \ 305 "ramdisk_addr_r=0xa0000000\0" \ 306 "load_addr=0xa0000000\0" \ 307 "kernel_size=0x2800000\0" \ 308 "kernel_addr_sd=0x8000\0" \ 309 "kernel_size_sd=0x14000\0" \ 310 BOOTENV \ 311 "boot_scripts=ls1021atwr_boot.scr\0" \ 312 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ 313 "scan_dev_for_boot_part=" \ 314 "part list ${devtype} ${devnum} devplist; " \ 315 "env exists devplist || setenv devplist 1; " \ 316 "for distro_bootpart in ${devplist}; do " \ 317 "if fstype ${devtype} " \ 318 "${devnum}:${distro_bootpart} " \ 319 "bootfstype; then " \ 320 "run scan_dev_for_boot; " \ 321 "fi; " \ 322 "done\0" \ 323 "scan_dev_for_boot=" \ 324 "echo Scanning ${devtype} " \ 325 "${devnum}:${distro_bootpart}...; " \ 326 "for prefix in ${boot_prefixes}; do " \ 327 "run scan_dev_for_scripts; " \ 328 "done;" \ 329 "\0" \ 330 "boot_a_script=" \ 331 "load ${devtype} ${devnum}:${distro_bootpart} " \ 332 "${scriptaddr} ${prefix}${script}; " \ 333 "env exists secureboot && load ${devtype} " \ 334 "${devnum}:${distro_bootpart} " \ 335 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ 336 "env exists secureboot " \ 337 "&& esbc_validate ${scripthdraddr};" \ 338 "source ${scriptaddr}\0" \ 339 "installer=load mmc 0:2 $load_addr " \ 340 "/flex_installer_arm32.itb; " \ 341 "bootm $load_addr#ls1021atwr\0" \ 342 "qspi_bootcmd=echo Trying load from qspi..;" \ 343 "sf probe && sf read $load_addr " \ 344 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \ 345 "nor_bootcmd=echo Trying load from nor..;" \ 346 "cp.b $kernel_addr $load_addr " \ 347 "$kernel_size && bootm $load_addr#$board\0" 348 #else 349 #define CONFIG_EXTRA_ENV_SETTINGS \ 350 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 351 "initrd_high=0xffffffff\0" \ 352 "fdt_high=0xffffffff\0" \ 353 "fdt_addr=0x64f00000\0" \ 354 "kernel_addr=0x61000000\0" \ 355 "kernelheader_addr=0x60800000\0" \ 356 "scriptaddr=0x80000000\0" \ 357 "scripthdraddr=0x80080000\0" \ 358 "fdtheader_addr_r=0x80100000\0" \ 359 "kernelheader_addr_r=0x80200000\0" \ 360 "kernel_addr_r=0x81000000\0" \ 361 "kernelheader_size=0x40000\0" \ 362 "fdt_addr_r=0x90000000\0" \ 363 "ramdisk_addr_r=0xa0000000\0" \ 364 "load_addr=0xa0000000\0" \ 365 "kernel_size=0x2800000\0" \ 366 "kernel_addr_sd=0x8000\0" \ 367 "kernel_size_sd=0x14000\0" \ 368 "kernelhdr_addr_sd=0x4000\0" \ 369 "kernelhdr_size_sd=0x10\0" \ 370 BOOTENV \ 371 "boot_scripts=ls1021atwr_boot.scr\0" \ 372 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ 373 "scan_dev_for_boot_part=" \ 374 "part list ${devtype} ${devnum} devplist; " \ 375 "env exists devplist || setenv devplist 1; " \ 376 "for distro_bootpart in ${devplist}; do " \ 377 "if fstype ${devtype} " \ 378 "${devnum}:${distro_bootpart} " \ 379 "bootfstype; then " \ 380 "run scan_dev_for_boot; " \ 381 "fi; " \ 382 "done\0" \ 383 "scan_dev_for_boot=" \ 384 "echo Scanning ${devtype} " \ 385 "${devnum}:${distro_bootpart}...; " \ 386 "for prefix in ${boot_prefixes}; do " \ 387 "run scan_dev_for_scripts; " \ 388 "done;" \ 389 "\0" \ 390 "boot_a_script=" \ 391 "load ${devtype} ${devnum}:${distro_bootpart} " \ 392 "${scriptaddr} ${prefix}${script}; " \ 393 "env exists secureboot && load ${devtype} " \ 394 "${devnum}:${distro_bootpart} " \ 395 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 396 "&& esbc_validate ${scripthdraddr};" \ 397 "source ${scriptaddr}\0" \ 398 "qspi_bootcmd=echo Trying load from qspi..;" \ 399 "sf probe && sf read $load_addr " \ 400 "$kernel_addr $kernel_size; env exists secureboot " \ 401 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 402 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 403 "bootm $load_addr#$board\0" \ 404 "nor_bootcmd=echo Trying load from nor..;" \ 405 "cp.b $kernel_addr $load_addr " \ 406 "$kernel_size; env exists secureboot " \ 407 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ 408 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 409 "bootm $load_addr#$board\0" \ 410 "sd_bootcmd=echo Trying load from SD ..;" \ 411 "mmcinfo && mmc read $load_addr " \ 412 "$kernel_addr_sd $kernel_size_sd && " \ 413 "env exists secureboot && mmc read $kernelheader_addr_r " \ 414 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 415 " && esbc_validate ${kernelheader_addr_r};" \ 416 "bootm $load_addr#$board\0" 417 #endif 418 419 #undef CONFIG_BOOTCOMMAND 420 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 421 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ 422 "env exists secureboot && esbc_halt" 423 #elif defined(CONFIG_SD_BOOT) 424 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ 425 "env exists secureboot && esbc_halt;" 426 #else 427 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \ 428 "env exists secureboot && esbc_halt;" 429 #endif 430 431 /* 432 * Miscellaneous configurable options 433 */ 434 435 #define CONFIG_SYS_MEMTEST_START 0x80000000 436 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 437 438 #define CONFIG_SYS_LOAD_ADDR 0x82000000 439 440 #define CONFIG_LS102XA_STREAM_ID 441 442 #define CONFIG_SYS_INIT_SP_OFFSET \ 443 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 444 #define CONFIG_SYS_INIT_SP_ADDR \ 445 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 446 447 #ifdef CONFIG_SPL_BUILD 448 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 449 #else 450 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 451 #endif 452 453 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 454 455 /* 456 * Environment 457 */ 458 #define CONFIG_ENV_OVERWRITE 459 460 #if defined(CONFIG_SD_BOOT) 461 #define CONFIG_SYS_MMC_ENV_DEV 0 462 #endif 463 464 #include <asm/fsl_secure_boot.h> 465 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 466 467 #endif 468