1 /*
2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2019, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9 #include <string.h>
10
11 #include <arch_helpers.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <lib/mmio.h>
15 #include <lib/utils.h>
16 #include <lib/xlat_tables/xlat_tables_v2.h>
17
18 #include <mce.h>
19 #include <memctrl.h>
20 #include <memctrl_v2.h>
21 #include <smmu.h>
22 #include <tegra_def.h>
23 #include <tegra_platform.h>
24
25 /* Video Memory base and size (live values) */
26 static uint64_t video_mem_base;
27 static uint64_t video_mem_size_mb;
28
29 /*
30 * The following platform setup functions are weakly defined. They
31 * provide typical implementations that will be overridden by a SoC.
32 */
33 #pragma weak plat_memctrl_tzdram_setup
34
plat_memctrl_tzdram_setup(uint64_t phys_base,uint64_t size_in_bytes)35 void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
36 {
37 ; /* do nothing */
38 }
39
40 /*
41 * Init Memory controller during boot.
42 */
tegra_memctrl_setup(void)43 void tegra_memctrl_setup(void)
44 {
45 uint32_t val;
46 const uint32_t *mc_streamid_override_regs;
47 uint32_t num_streamid_override_regs;
48 const mc_streamid_security_cfg_t *mc_streamid_sec_cfgs;
49 uint32_t num_streamid_sec_cfgs;
50 const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
51 uint32_t i;
52
53 INFO("Tegra Memory Controller (v2)\n");
54
55 /* Program the SMMU pagesize */
56 tegra_smmu_init();
57
58 /* Get the settings from the platform */
59 assert(plat_mc_settings != NULL);
60 mc_streamid_override_regs = plat_mc_settings->streamid_override_cfg;
61 num_streamid_override_regs = plat_mc_settings->num_streamid_override_cfgs;
62 mc_streamid_sec_cfgs = plat_mc_settings->streamid_security_cfg;
63 num_streamid_sec_cfgs = plat_mc_settings->num_streamid_security_cfgs;
64
65 /* Program all the Stream ID overrides */
66 for (i = 0; i < num_streamid_override_regs; i++)
67 tegra_mc_streamid_write_32(mc_streamid_override_regs[i],
68 MC_STREAM_ID_MAX);
69
70 /* Program the security config settings for all Stream IDs */
71 for (i = 0; i < num_streamid_sec_cfgs; i++) {
72 val = mc_streamid_sec_cfgs[i].override_enable << 16 |
73 mc_streamid_sec_cfgs[i].override_client_inputs << 8 |
74 mc_streamid_sec_cfgs[i].override_client_ns_flag << 0;
75 tegra_mc_streamid_write_32(mc_streamid_sec_cfgs[i].offset, val);
76 }
77
78 /*
79 * All requests at boot time, and certain requests during
80 * normal run time, are physically addressed and must bypass
81 * the SMMU. The client hub logic implements a hardware bypass
82 * path around the Translation Buffer Units (TBU). During
83 * boot-time, the SMMU_BYPASS_CTRL register (which defaults to
84 * TBU_BYPASS mode) will be used to steer all requests around
85 * the uninitialized TBUs. During normal operation, this register
86 * is locked into TBU_BYPASS_SID config, which routes requests
87 * with special StreamID 0x7f on the bypass path and all others
88 * through the selected TBU. This is done to disable SMMU Bypass
89 * mode, as it could be used to circumvent SMMU security checks.
90 */
91 tegra_mc_write_32(MC_SMMU_BYPASS_CONFIG,
92 MC_SMMU_BYPASS_CONFIG_SETTINGS);
93
94 /*
95 * Re-configure MSS to allow ROC to deal with ordering of the
96 * Memory Controller traffic. This is needed as the Memory Controller
97 * boots with MSS having all control, but ROC provides a performance
98 * boost as compared to MSS.
99 */
100 if (plat_mc_settings->reconfig_mss_clients != NULL) {
101 plat_mc_settings->reconfig_mss_clients();
102 }
103
104 /* Program overrides for MC transactions */
105 if (plat_mc_settings->set_txn_overrides != NULL) {
106 plat_mc_settings->set_txn_overrides();
107 }
108 }
109
110 /*
111 * Restore Memory Controller settings after "System Suspend"
112 */
tegra_memctrl_restore_settings(void)113 void tegra_memctrl_restore_settings(void)
114 {
115 const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
116
117 assert(plat_mc_settings != NULL);
118
119 /*
120 * Re-configure MSS to allow ROC to deal with ordering of the
121 * Memory Controller traffic. This is needed as the Memory Controller
122 * resets during System Suspend with MSS having all control, but ROC
123 * provides a performance boost as compared to MSS.
124 */
125 if (plat_mc_settings->reconfig_mss_clients != NULL) {
126 plat_mc_settings->reconfig_mss_clients();
127 }
128
129 /* Program overrides for MC transactions */
130 if (plat_mc_settings->set_txn_overrides != NULL) {
131 plat_mc_settings->set_txn_overrides();
132 }
133
134 /* video memory carveout region */
135 if (video_mem_base != 0ULL) {
136 tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO,
137 (uint32_t)video_mem_base);
138 tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
139 (uint32_t)(video_mem_base >> 32));
140 tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size_mb);
141
142 /*
143 * MCE propagates the VideoMem configuration values across the
144 * CCPLEX.
145 */
146 mce_update_gsc_videomem();
147 }
148 }
149
150 /*
151 * Secure the BL31 DRAM aperture.
152 *
153 * phys_base = physical base of TZDRAM aperture
154 * size_in_bytes = size of aperture in bytes
155 */
tegra_memctrl_tzdram_setup(uint64_t phys_base,uint32_t size_in_bytes)156 void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes)
157 {
158 /*
159 * Perform platform specific steps.
160 */
161 plat_memctrl_tzdram_setup(phys_base, size_in_bytes);
162 }
163
164 /*
165 * Secure the BL31 TZRAM aperture.
166 *
167 * phys_base = physical base of TZRAM aperture
168 * size_in_bytes = size of aperture in bytes
169 */
tegra_memctrl_tzram_setup(uint64_t phys_base,uint32_t size_in_bytes)170 void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
171 {
172 uint32_t index;
173 uint32_t total_128kb_blocks = size_in_bytes >> 17;
174 uint32_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12;
175 uint32_t val;
176
177 INFO("Configuring TrustZone SRAM Memory Carveout\n");
178
179 /*
180 * Reset the access configuration registers to restrict access
181 * to the TZRAM aperture
182 */
183 for (index = MC_TZRAM_CLIENT_ACCESS0_CFG0;
184 index < ((uint32_t)MC_TZRAM_CARVEOUT_CFG + (uint32_t)MC_GSC_CONFIG_REGS_SIZE);
185 index += 4U) {
186 tegra_mc_write_32(index, 0);
187 }
188
189 /*
190 * Enable CPU access configuration registers to access the TZRAM aperture
191 */
192 if (!tegra_chipid_is_t186()) {
193 val = tegra_mc_read_32(MC_TZRAM_CLIENT_ACCESS1_CFG0);
194 val |= TZRAM_ALLOW_MPCORER | TZRAM_ALLOW_MPCOREW;
195 tegra_mc_write_32(MC_TZRAM_CLIENT_ACCESS1_CFG0, val);
196 }
197
198 /*
199 * Set the TZRAM base. TZRAM base must be 4k aligned, at least.
200 */
201 assert((phys_base & (uint64_t)0xFFF) == 0U);
202 tegra_mc_write_32(MC_TZRAM_BASE_LO, (uint32_t)phys_base);
203 tegra_mc_write_32(MC_TZRAM_BASE_HI,
204 (uint32_t)(phys_base >> 32) & MC_GSC_BASE_HI_MASK);
205
206 /*
207 * Set the TZRAM size
208 *
209 * total size = (number of 128KB blocks) + (number of remaining 4KB
210 * blocks)
211 *
212 */
213 val = (residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) |
214 total_128kb_blocks;
215 tegra_mc_write_32(MC_TZRAM_SIZE, val);
216
217 /*
218 * Lock the configuration settings by disabling TZ-only lock
219 * and locking the configuration against any future changes
220 * at all.
221 */
222 val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG);
223 val &= (uint32_t)~MC_GSC_ENABLE_TZ_LOCK_BIT;
224 val |= MC_GSC_LOCK_CFG_SETTINGS_BIT;
225 if (!tegra_chipid_is_t186()) {
226 val |= MC_GSC_ENABLE_CPU_SECURE_BIT;
227 }
228 tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val);
229
230 /*
231 * MCE propagates the security configuration values across the
232 * CCPLEX.
233 */
234 mce_update_gsc_tzram();
235 }
236
tegra_lock_videomem_nonoverlap(uint64_t phys_base,uint64_t size_in_bytes)237 static void tegra_lock_videomem_nonoverlap(uint64_t phys_base,
238 uint64_t size_in_bytes)
239 {
240 uint32_t index;
241 uint64_t total_128kb_blocks = size_in_bytes >> 17;
242 uint64_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12;
243 uint64_t val;
244
245 /*
246 * Reset the access configuration registers to restrict access to
247 * old Videomem aperture
248 */
249 for (index = MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0;
250 index < ((uint32_t)MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 + (uint32_t)MC_GSC_CONFIG_REGS_SIZE);
251 index += 4U) {
252 tegra_mc_write_32(index, 0);
253 }
254
255 /*
256 * Set the base. It must be 4k aligned, at least.
257 */
258 assert((phys_base & (uint64_t)0xFFF) == 0U);
259 tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, (uint32_t)phys_base);
260 tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_HI,
261 (uint32_t)(phys_base >> 32) & (uint32_t)MC_GSC_BASE_HI_MASK);
262
263 /*
264 * Set the aperture size
265 *
266 * total size = (number of 128KB blocks) + (number of remaining 4KB
267 * blocks)
268 *
269 */
270 val = (uint32_t)((residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) |
271 total_128kb_blocks);
272 tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_SIZE, (uint32_t)val);
273
274 /*
275 * Lock the configuration settings by enabling TZ-only lock and
276 * locking the configuration against any future changes from NS
277 * world.
278 */
279 tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_CFG,
280 (uint32_t)MC_GSC_ENABLE_TZ_LOCK_BIT);
281
282 /*
283 * MCE propagates the GSC configuration values across the
284 * CCPLEX.
285 */
286 }
287
tegra_unlock_videomem_nonoverlap(void)288 static void tegra_unlock_videomem_nonoverlap(void)
289 {
290 /* Clear the base */
291 tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, 0);
292 tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_HI, 0);
293
294 /* Clear the size */
295 tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_SIZE, 0);
296 }
297
tegra_clear_videomem(uintptr_t non_overlap_area_start,unsigned long long non_overlap_area_size)298 static void tegra_clear_videomem(uintptr_t non_overlap_area_start,
299 unsigned long long non_overlap_area_size)
300 {
301 int ret;
302
303 /*
304 * Map the NS memory first, clean it and then unmap it.
305 */
306 ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */
307 non_overlap_area_start, /* VA */
308 non_overlap_area_size, /* size */
309 MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */
310 assert(ret == 0);
311
312 zero_normalmem((void *)non_overlap_area_start, non_overlap_area_size);
313 flush_dcache_range(non_overlap_area_start, non_overlap_area_size);
314
315 (void)mmap_remove_dynamic_region(non_overlap_area_start,
316 non_overlap_area_size);
317 }
318
319 /*
320 * Program the Video Memory carveout region
321 *
322 * phys_base = physical base of aperture
323 * size_in_bytes = size of aperture in bytes
324 */
tegra_memctrl_videomem_setup(uint64_t phys_base,uint32_t size_in_bytes)325 void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
326 {
327 uintptr_t vmem_end_old = video_mem_base + (video_mem_size_mb << 20);
328 uintptr_t vmem_end_new = phys_base + size_in_bytes;
329 unsigned long long non_overlap_area_size;
330
331 /*
332 * Setup the Memory controller to restrict CPU accesses to the Video
333 * Memory region
334 */
335 INFO("Configuring Video Memory Carveout\n");
336
337 /*
338 * Configure Memory Controller directly for the first time.
339 */
340 if (video_mem_base == 0U)
341 goto done;
342
343 /*
344 * Lock the non overlapping memory being cleared so that other masters
345 * do not accidently write to it. The memory would be unlocked once
346 * the non overlapping region is cleared and the new memory
347 * settings take effect.
348 */
349 tegra_lock_videomem_nonoverlap(video_mem_base,
350 video_mem_size_mb << 20);
351
352 /*
353 * Clear the old regions now being exposed. The following cases
354 * can occur -
355 *
356 * 1. clear whole old region (no overlap with new region)
357 * 2. clear old sub-region below new base
358 * 3. clear old sub-region above new end
359 */
360 INFO("Cleaning previous Video Memory Carveout\n");
361
362 if ((phys_base > vmem_end_old) || (video_mem_base > vmem_end_new)) {
363 tegra_clear_videomem(video_mem_base,
364 video_mem_size_mb << 20U);
365 } else {
366 if (video_mem_base < phys_base) {
367 non_overlap_area_size = phys_base - video_mem_base;
368 tegra_clear_videomem(video_mem_base, non_overlap_area_size);
369 }
370 if (vmem_end_old > vmem_end_new) {
371 non_overlap_area_size = vmem_end_old - vmem_end_new;
372 tegra_clear_videomem(vmem_end_new, non_overlap_area_size);
373 }
374 }
375
376 done:
377 /* program the Videomem aperture */
378 tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base);
379 tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
380 (uint32_t)(phys_base >> 32));
381 tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20);
382
383 /* unlock the previous locked nonoverlapping aperture */
384 tegra_unlock_videomem_nonoverlap();
385
386 /* store new values */
387 video_mem_base = phys_base;
388 video_mem_size_mb = size_in_bytes >> 20;
389
390 /*
391 * MCE propagates the VideoMem configuration values across the
392 * CCPLEX.
393 */
394 mce_update_gsc_videomem();
395 }
396
397 /*
398 * This feature exists only for v1 of the Tegra Memory Controller.
399 */
tegra_memctrl_disable_ahb_redirection(void)400 void tegra_memctrl_disable_ahb_redirection(void)
401 {
402 ; /* do nothing */
403 }
404
tegra_memctrl_clear_pending_interrupts(void)405 void tegra_memctrl_clear_pending_interrupts(void)
406 {
407 ; /* do nothing */
408 }
409