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1 /*
2  * Copyright 2010 Christoph Bumiller
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #include "pipe/p_defines.h"
24 #include "util/u_framebuffer.h"
25 #include "util/u_helpers.h"
26 #include "util/u_inlines.h"
27 #include "util/u_transfer.h"
28 
29 #include "tgsi/tgsi_parse.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_serialize.h"
32 
33 #include "nvc0/nvc0_stateobj.h"
34 #include "nvc0/nvc0_context.h"
35 #include "nvc0/nvc0_query_hw.h"
36 
37 #include "nvc0/nvc0_3d.xml.h"
38 
39 #include "nouveau_gldefs.h"
40 
41 static inline uint32_t
nvc0_colormask(unsigned mask)42 nvc0_colormask(unsigned mask)
43 {
44     uint32_t ret = 0;
45 
46     if (mask & PIPE_MASK_R)
47         ret |= 0x0001;
48     if (mask & PIPE_MASK_G)
49         ret |= 0x0010;
50     if (mask & PIPE_MASK_B)
51         ret |= 0x0100;
52     if (mask & PIPE_MASK_A)
53         ret |= 0x1000;
54 
55     return ret;
56 }
57 
58 #define NVC0_BLEND_FACTOR_CASE(a, b) \
59    case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
60 
61 static inline uint32_t
nvc0_blend_fac(unsigned factor)62 nvc0_blend_fac(unsigned factor)
63 {
64    switch (factor) {
65    NVC0_BLEND_FACTOR_CASE(ONE, ONE);
66    NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
67    NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
68    NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
69    NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
70    NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
71    NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
72    NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
73    NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
74    NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
75    NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
76    NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
77    NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
78    NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
79    NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
80    NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
81    NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
82    NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
83    NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
84    default:
85       return NV50_BLEND_FACTOR_ZERO;
86    }
87 }
88 
89 static void *
nvc0_blend_state_create(struct pipe_context * pipe,const struct pipe_blend_state * cso)90 nvc0_blend_state_create(struct pipe_context *pipe,
91                         const struct pipe_blend_state *cso)
92 {
93    struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
94    int i;
95    int r; /* reference */
96    uint32_t ms;
97    uint8_t blend_en = 0;
98    bool indep_masks = false;
99    bool indep_funcs = false;
100 
101    so->pipe = *cso;
102 
103    /* check which states actually have differing values */
104    if (cso->independent_blend_enable) {
105       for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
106       blend_en |= 1 << r;
107       for (i = r + 1; i < 8; ++i) {
108          if (!cso->rt[i].blend_enable)
109             continue;
110          blend_en |= 1 << i;
111          if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
112              cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
113              cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
114              cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
115              cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
116              cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
117             indep_funcs = true;
118             break;
119          }
120       }
121       for (; i < 8; ++i)
122          blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
123 
124       for (i = 1; i < 8; ++i) {
125          if (cso->rt[i].colormask != cso->rt[0].colormask) {
126             indep_masks = true;
127             break;
128          }
129       }
130    } else {
131       r = 0;
132       if (cso->rt[0].blend_enable)
133          blend_en = 0xff;
134    }
135 
136    if (cso->logicop_enable) {
137       SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
138       SB_DATA    (so, 1);
139       SB_DATA    (so, nvgl_logicop_func(cso->logicop_func));
140 
141       SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
142    } else {
143       SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
144 
145       SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
146       SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
147       if (indep_funcs) {
148          for (i = 0; i < 8; ++i) {
149             if (cso->rt[i].blend_enable) {
150                SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
151                SB_DATA    (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
152                SB_DATA    (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
153                SB_DATA    (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
154                SB_DATA    (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
155                SB_DATA    (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
156                SB_DATA    (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
157             }
158          }
159       } else
160       if (blend_en) {
161          SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
162          SB_DATA    (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
163          SB_DATA    (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
164          SB_DATA    (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
165          SB_DATA    (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
166          SB_DATA    (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
167          SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
168          SB_DATA    (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
169       }
170 
171       SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
172       if (indep_masks) {
173          SB_BEGIN_3D(so, COLOR_MASK(0), 8);
174          for (i = 0; i < 8; ++i)
175             SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
176       } else {
177          SB_BEGIN_3D(so, COLOR_MASK(0), 1);
178          SB_DATA    (so, nvc0_colormask(cso->rt[0].colormask));
179       }
180    }
181 
182    ms = 0;
183    if (cso->alpha_to_coverage)
184       ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
185    if (cso->alpha_to_one)
186       ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
187 
188    SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
189    SB_DATA    (so, ms);
190 
191    assert(so->size <= ARRAY_SIZE(so->state));
192    return so;
193 }
194 
195 static void
nvc0_blend_state_bind(struct pipe_context * pipe,void * hwcso)196 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
197 {
198     struct nvc0_context *nvc0 = nvc0_context(pipe);
199 
200     nvc0->blend = hwcso;
201     nvc0->dirty_3d |= NVC0_NEW_3D_BLEND;
202 }
203 
204 static void
nvc0_blend_state_delete(struct pipe_context * pipe,void * hwcso)205 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
206 {
207     FREE(hwcso);
208 }
209 
210 /* NOTE: ignoring line_last_pixel */
211 static void *
nvc0_rasterizer_state_create(struct pipe_context * pipe,const struct pipe_rasterizer_state * cso)212 nvc0_rasterizer_state_create(struct pipe_context *pipe,
213                              const struct pipe_rasterizer_state *cso)
214 {
215     struct nvc0_rasterizer_stateobj *so;
216     uint16_t class_3d = nouveau_screen(pipe->screen)->class_3d;
217     uint32_t reg;
218 
219     so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
220     if (!so)
221         return NULL;
222     so->pipe = *cso;
223 
224     /* Scissor enables are handled in scissor state, we will not want to
225      * always emit 16 commands, one for each scissor rectangle, here.
226      */
227 
228     SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
229     SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
230 
231     SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
232     SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
233     SB_DATA    (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
234 
235     SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
236 
237     SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
238     if (cso->line_smooth || cso->multisample)
239        SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
240     else
241        SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
242     SB_DATA    (so, fui(cso->line_width));
243 
244     SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
245     if (cso->line_stipple_enable) {
246         SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
247         SB_DATA    (so, (cso->line_stipple_pattern << 8) |
248                          cso->line_stipple_factor);
249 
250     }
251 
252     SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
253     if (!cso->point_size_per_vertex) {
254        SB_BEGIN_3D(so, POINT_SIZE, 1);
255        SB_DATA    (so, fui(cso->point_size));
256     }
257 
258     reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
259        NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
260        NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
261 
262     SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
263     SB_DATA    (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
264     SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
265     SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
266 
267     if (class_3d >= GM200_3D_CLASS) {
268        SB_IMMED_3D(so, FILL_RECTANGLE,
269                    cso->fill_front == PIPE_POLYGON_MODE_FILL_RECTANGLE ?
270                    NVC0_3D_FILL_RECTANGLE_ENABLE : 0);
271     }
272 
273     SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
274     SB_DATA    (so, nvgl_polygon_mode(cso->fill_front));
275     SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
276     SB_DATA    (so, nvgl_polygon_mode(cso->fill_back));
277     SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
278 
279     SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
280     SB_DATA    (so, cso->cull_face != PIPE_FACE_NONE);
281     SB_DATA    (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
282                                      NVC0_3D_FRONT_FACE_CW);
283     switch (cso->cull_face) {
284     case PIPE_FACE_FRONT_AND_BACK:
285        SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
286        break;
287     case PIPE_FACE_FRONT:
288        SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
289        break;
290     case PIPE_FACE_BACK:
291     default:
292        SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
293        break;
294     }
295 
296     SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
297     SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
298     SB_DATA    (so, cso->offset_point);
299     SB_DATA    (so, cso->offset_line);
300     SB_DATA    (so, cso->offset_tri);
301 
302     if (cso->offset_point || cso->offset_line || cso->offset_tri) {
303         SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
304         SB_DATA    (so, fui(cso->offset_scale));
305         if (!cso->offset_units_unscaled) {
306            SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
307            SB_DATA    (so, fui(cso->offset_units * 2.0f));
308         }
309         SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
310         SB_DATA    (so, fui(cso->offset_clamp));
311     }
312 
313     if (cso->depth_clip_near)
314        reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
315     else
316        reg =
317           NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
318           NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
319           NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
320           NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
321 
322     SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
323     SB_DATA    (so, reg);
324 
325     SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
326 
327     SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
328 
329     if (class_3d >= GM200_3D_CLASS) {
330         if (cso->conservative_raster_mode != PIPE_CONSERVATIVE_RASTER_OFF) {
331             bool post_snap = cso->conservative_raster_mode ==
332                 PIPE_CONSERVATIVE_RASTER_POST_SNAP;
333             uint32_t state = cso->subpixel_precision_x;
334             state |= cso->subpixel_precision_y << 4;
335             state |= (uint32_t)(cso->conservative_raster_dilate * 4) << 8;
336             state |= (post_snap || class_3d < GP100_3D_CLASS) ? 1 << 10 : 0;
337             SB_IMMED_3D(so, MACRO_CONSERVATIVE_RASTER_STATE, state);
338         } else {
339             SB_IMMED_3D(so, CONSERVATIVE_RASTER, 0);
340         }
341     }
342 
343     assert(so->size <= ARRAY_SIZE(so->state));
344     return (void *)so;
345 }
346 
347 static void
nvc0_rasterizer_state_bind(struct pipe_context * pipe,void * hwcso)348 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
349 {
350    struct nvc0_context *nvc0 = nvc0_context(pipe);
351 
352    nvc0->rast = hwcso;
353    nvc0->dirty_3d |= NVC0_NEW_3D_RASTERIZER;
354 }
355 
356 static void
nvc0_rasterizer_state_delete(struct pipe_context * pipe,void * hwcso)357 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
358 {
359    FREE(hwcso);
360 }
361 
362 static void *
nvc0_zsa_state_create(struct pipe_context * pipe,const struct pipe_depth_stencil_alpha_state * cso)363 nvc0_zsa_state_create(struct pipe_context *pipe,
364                       const struct pipe_depth_stencil_alpha_state *cso)
365 {
366    struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
367 
368    so->pipe = *cso;
369 
370    SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
371    if (cso->depth.enabled) {
372       SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
373       SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
374       SB_DATA    (so, nvgl_comparison_op(cso->depth.func));
375    }
376 
377    SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth.bounds_test);
378    if (cso->depth.bounds_test) {
379       SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
380       SB_DATA    (so, fui(cso->depth.bounds_min));
381       SB_DATA    (so, fui(cso->depth.bounds_max));
382    }
383 
384    if (cso->stencil[0].enabled) {
385       SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
386       SB_DATA    (so, 1);
387       SB_DATA    (so, nvgl_stencil_op(cso->stencil[0].fail_op));
388       SB_DATA    (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
389       SB_DATA    (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
390       SB_DATA    (so, nvgl_comparison_op(cso->stencil[0].func));
391       SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
392       SB_DATA    (so, cso->stencil[0].valuemask);
393       SB_DATA    (so, cso->stencil[0].writemask);
394    } else {
395       SB_IMMED_3D(so, STENCIL_ENABLE, 0);
396    }
397 
398    if (cso->stencil[1].enabled) {
399       assert(cso->stencil[0].enabled);
400       SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
401       SB_DATA    (so, 1);
402       SB_DATA    (so, nvgl_stencil_op(cso->stencil[1].fail_op));
403       SB_DATA    (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
404       SB_DATA    (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
405       SB_DATA    (so, nvgl_comparison_op(cso->stencil[1].func));
406       SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
407       SB_DATA    (so, cso->stencil[1].writemask);
408       SB_DATA    (so, cso->stencil[1].valuemask);
409    } else
410    if (cso->stencil[0].enabled) {
411       SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
412    }
413 
414    SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha.enabled);
415    if (cso->alpha.enabled) {
416       SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
417       SB_DATA    (so, fui(cso->alpha.ref_value));
418       SB_DATA    (so, nvgl_comparison_op(cso->alpha.func));
419    }
420 
421    assert(so->size <= ARRAY_SIZE(so->state));
422    return (void *)so;
423 }
424 
425 static void
nvc0_zsa_state_bind(struct pipe_context * pipe,void * hwcso)426 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
427 {
428    struct nvc0_context *nvc0 = nvc0_context(pipe);
429 
430    nvc0->zsa = hwcso;
431    nvc0->dirty_3d |= NVC0_NEW_3D_ZSA;
432 }
433 
434 static void
nvc0_zsa_state_delete(struct pipe_context * pipe,void * hwcso)435 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
436 {
437    FREE(hwcso);
438 }
439 
440 /* ====================== SAMPLERS AND TEXTURES ================================
441  */
442 
443 #define NV50_TSC_WRAP_CASE(n) \
444     case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
445 
446 static void
nvc0_sampler_state_delete(struct pipe_context * pipe,void * hwcso)447 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
448 {
449    unsigned s, i;
450 
451    for (s = 0; s < 6; ++s)
452       for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
453          if (nvc0_context(pipe)->samplers[s][i] == hwcso)
454             nvc0_context(pipe)->samplers[s][i] = NULL;
455 
456    nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
457 
458    FREE(hwcso);
459 }
460 
461 static inline void
nvc0_stage_sampler_states_bind(struct nvc0_context * nvc0,unsigned s,unsigned nr,void ** hwcsos)462 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0,
463                                unsigned s,
464                                unsigned nr, void **hwcsos)
465 {
466    unsigned highest_found = 0;
467    unsigned i;
468 
469    for (i = 0; i < nr; ++i) {
470       struct nv50_tsc_entry *hwcso = hwcsos ? nv50_tsc_entry(hwcsos[i]) : NULL;
471       struct nv50_tsc_entry *old = nvc0->samplers[s][i];
472 
473       if (hwcso)
474          highest_found = i;
475 
476       if (hwcso == old)
477          continue;
478       nvc0->samplers_dirty[s] |= 1 << i;
479 
480       nvc0->samplers[s][i] = hwcso;
481       if (old)
482          nvc0_screen_tsc_unlock(nvc0->screen, old);
483    }
484    if (nr >= nvc0->num_samplers[s])
485       nvc0->num_samplers[s] = highest_found + 1;
486 }
487 
488 static void
nvc0_bind_sampler_states(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned nr,void ** samplers)489 nvc0_bind_sampler_states(struct pipe_context *pipe,
490                          enum pipe_shader_type shader,
491                          unsigned start, unsigned nr, void **samplers)
492 {
493    const unsigned s = nvc0_shader_stage(shader);
494 
495    assert(start == 0);
496    nvc0_stage_sampler_states_bind(nvc0_context(pipe), s, nr, samplers);
497 
498    if (s == 5)
499       nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
500    else
501       nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SAMPLERS;
502 }
503 
504 
505 /* NOTE: only called when not referenced anywhere, won't be bound */
506 static void
nvc0_sampler_view_destroy(struct pipe_context * pipe,struct pipe_sampler_view * view)507 nvc0_sampler_view_destroy(struct pipe_context *pipe,
508                           struct pipe_sampler_view *view)
509 {
510    pipe_resource_reference(&view->texture, NULL);
511 
512    nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
513 
514    FREE(nv50_tic_entry(view));
515 }
516 
517 static inline void
nvc0_stage_set_sampler_views(struct nvc0_context * nvc0,int s,unsigned nr,struct pipe_sampler_view ** views)518 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
519                              unsigned nr,
520                              struct pipe_sampler_view **views)
521 {
522    unsigned i;
523 
524    for (i = 0; i < nr; ++i) {
525       struct pipe_sampler_view *view = views ? views[i] : NULL;
526       struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
527 
528       if (view == nvc0->textures[s][i])
529          continue;
530       nvc0->textures_dirty[s] |= 1 << i;
531 
532       if (view && view->texture) {
533          struct pipe_resource *res = view->texture;
534          if (res->target == PIPE_BUFFER &&
535              (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
536             nvc0->textures_coherent[s] |= 1 << i;
537          else
538             nvc0->textures_coherent[s] &= ~(1 << i);
539       } else {
540          nvc0->textures_coherent[s] &= ~(1 << i);
541       }
542 
543       if (old) {
544          if (s == 5)
545             nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
546          else
547             nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
548          nvc0_screen_tic_unlock(nvc0->screen, old);
549       }
550 
551       pipe_sampler_view_reference(&nvc0->textures[s][i], view);
552    }
553 
554    for (i = nr; i < nvc0->num_textures[s]; ++i) {
555       struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
556       if (old) {
557          if (s == 5)
558             nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
559          else
560             nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
561          nvc0_screen_tic_unlock(nvc0->screen, old);
562          pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
563       }
564    }
565 
566    nvc0->num_textures[s] = nr;
567 }
568 
569 static void
nvc0_set_sampler_views(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned nr,struct pipe_sampler_view ** views)570 nvc0_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader,
571                        unsigned start, unsigned nr,
572                        struct pipe_sampler_view **views)
573 {
574    const unsigned s = nvc0_shader_stage(shader);
575 
576    assert(start == 0);
577    nvc0_stage_set_sampler_views(nvc0_context(pipe), s, nr, views);
578 
579    if (s == 5)
580       nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
581    else
582       nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_TEXTURES;
583 }
584 
585 /* ============================= SHADERS =======================================
586  */
587 
588 static void *
nvc0_sp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso,unsigned type)589 nvc0_sp_state_create(struct pipe_context *pipe,
590                      const struct pipe_shader_state *cso, unsigned type)
591 {
592    struct nvc0_program *prog;
593 
594    prog = CALLOC_STRUCT(nvc0_program);
595    if (!prog)
596       return NULL;
597 
598    prog->type = type;
599    prog->pipe.type = cso->type;
600 
601    switch(cso->type) {
602    case PIPE_SHADER_IR_TGSI:
603       prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
604       break;
605    case PIPE_SHADER_IR_NIR:
606       prog->pipe.ir.nir = cso->ir.nir;
607       break;
608    default:
609       assert(!"unsupported IR!");
610       free(prog);
611       return NULL;
612    }
613 
614    if (cso->stream_output.num_outputs)
615       prog->pipe.stream_output = cso->stream_output;
616 
617    prog->translated = nvc0_program_translate(
618       prog, nvc0_context(pipe)->screen->base.device->chipset,
619       nvc0_context(pipe)->screen->base.disk_shader_cache,
620       &nouveau_context(pipe)->debug);
621 
622    return (void *)prog;
623 }
624 
625 static void
nvc0_sp_state_delete(struct pipe_context * pipe,void * hwcso)626 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
627 {
628    struct nvc0_program *prog = (struct nvc0_program *)hwcso;
629 
630    nvc0_program_destroy(nvc0_context(pipe), prog);
631 
632    if (prog->pipe.type == PIPE_SHADER_IR_TGSI)
633       FREE((void *)prog->pipe.tokens);
634    else if (prog->pipe.type == PIPE_SHADER_IR_NIR)
635       ralloc_free(prog->pipe.ir.nir);
636    FREE(prog);
637 }
638 
639 static void *
nvc0_vp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso)640 nvc0_vp_state_create(struct pipe_context *pipe,
641                      const struct pipe_shader_state *cso)
642 {
643    return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
644 }
645 
646 static void
nvc0_vp_state_bind(struct pipe_context * pipe,void * hwcso)647 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
648 {
649     struct nvc0_context *nvc0 = nvc0_context(pipe);
650 
651     nvc0->vertprog = hwcso;
652     nvc0->dirty_3d |= NVC0_NEW_3D_VERTPROG;
653 }
654 
655 static void *
nvc0_fp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso)656 nvc0_fp_state_create(struct pipe_context *pipe,
657                      const struct pipe_shader_state *cso)
658 {
659    return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
660 }
661 
662 static void
nvc0_fp_state_bind(struct pipe_context * pipe,void * hwcso)663 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
664 {
665     struct nvc0_context *nvc0 = nvc0_context(pipe);
666 
667     nvc0->fragprog = hwcso;
668     nvc0->dirty_3d |= NVC0_NEW_3D_FRAGPROG;
669 }
670 
671 static void *
nvc0_gp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso)672 nvc0_gp_state_create(struct pipe_context *pipe,
673                      const struct pipe_shader_state *cso)
674 {
675    return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
676 }
677 
678 static void
nvc0_gp_state_bind(struct pipe_context * pipe,void * hwcso)679 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
680 {
681     struct nvc0_context *nvc0 = nvc0_context(pipe);
682 
683     nvc0->gmtyprog = hwcso;
684     nvc0->dirty_3d |= NVC0_NEW_3D_GMTYPROG;
685 }
686 
687 static void *
nvc0_tcp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso)688 nvc0_tcp_state_create(struct pipe_context *pipe,
689                      const struct pipe_shader_state *cso)
690 {
691    return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
692 }
693 
694 static void
nvc0_tcp_state_bind(struct pipe_context * pipe,void * hwcso)695 nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
696 {
697     struct nvc0_context *nvc0 = nvc0_context(pipe);
698 
699     nvc0->tctlprog = hwcso;
700     nvc0->dirty_3d |= NVC0_NEW_3D_TCTLPROG;
701 }
702 
703 static void *
nvc0_tep_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso)704 nvc0_tep_state_create(struct pipe_context *pipe,
705                      const struct pipe_shader_state *cso)
706 {
707    return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
708 }
709 
710 static void
nvc0_tep_state_bind(struct pipe_context * pipe,void * hwcso)711 nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
712 {
713     struct nvc0_context *nvc0 = nvc0_context(pipe);
714 
715     nvc0->tevlprog = hwcso;
716     nvc0->dirty_3d |= NVC0_NEW_3D_TEVLPROG;
717 }
718 
719 static void *
nvc0_cp_state_create(struct pipe_context * pipe,const struct pipe_compute_state * cso)720 nvc0_cp_state_create(struct pipe_context *pipe,
721                      const struct pipe_compute_state *cso)
722 {
723    struct nvc0_program *prog;
724 
725    prog = CALLOC_STRUCT(nvc0_program);
726    if (!prog)
727       return NULL;
728    prog->type = PIPE_SHADER_COMPUTE;
729    prog->pipe.type = cso->ir_type;
730 
731    prog->cp.smem_size = cso->req_local_mem;
732    prog->cp.lmem_size = cso->req_private_mem;
733    prog->parm_size = cso->req_input_mem;
734 
735    switch(cso->ir_type) {
736    case PIPE_SHADER_IR_TGSI:
737       prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
738       break;
739    case PIPE_SHADER_IR_NIR:
740       prog->pipe.ir.nir = (nir_shader *)cso->prog;
741       break;
742    case PIPE_SHADER_IR_NIR_SERIALIZED: {
743       struct blob_reader reader;
744       const struct pipe_binary_program_header *hdr = cso->prog;
745 
746       blob_reader_init(&reader, hdr->blob, hdr->num_bytes);
747       prog->pipe.ir.nir = nir_deserialize(NULL, pipe->screen->get_compiler_options(pipe->screen, PIPE_SHADER_IR_NIR, PIPE_SHADER_COMPUTE), &reader);
748       prog->pipe.type = PIPE_SHADER_IR_NIR;
749       break;
750    }
751    default:
752       assert(!"unsupported IR!");
753       free(prog);
754       return NULL;
755    }
756 
757    prog->translated = nvc0_program_translate(
758       prog, nvc0_context(pipe)->screen->base.device->chipset,
759       nvc0_context(pipe)->screen->base.disk_shader_cache,
760       &nouveau_context(pipe)->debug);
761 
762    return (void *)prog;
763 }
764 
765 static void
nvc0_cp_state_bind(struct pipe_context * pipe,void * hwcso)766 nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
767 {
768     struct nvc0_context *nvc0 = nvc0_context(pipe);
769 
770     nvc0->compprog = hwcso;
771     nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
772 }
773 
774 static void
nvc0_set_constant_buffer(struct pipe_context * pipe,enum pipe_shader_type shader,uint index,const struct pipe_constant_buffer * cb)775 nvc0_set_constant_buffer(struct pipe_context *pipe,
776                          enum pipe_shader_type shader, uint index,
777                          const struct pipe_constant_buffer *cb)
778 {
779    struct nvc0_context *nvc0 = nvc0_context(pipe);
780    struct pipe_resource *res = cb ? cb->buffer : NULL;
781    const unsigned s = nvc0_shader_stage(shader);
782    const unsigned i = index;
783 
784    if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
785       if (nvc0->constbuf[s][i].user)
786          nvc0->constbuf[s][i].u.buf = NULL;
787       else
788       if (nvc0->constbuf[s][i].u.buf)
789          nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
790 
791       nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
792    } else {
793       if (nvc0->constbuf[s][i].user)
794          nvc0->constbuf[s][i].u.buf = NULL;
795       else
796       if (nvc0->constbuf[s][i].u.buf)
797          nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_CB(s, i));
798 
799       nvc0->dirty_3d |= NVC0_NEW_3D_CONSTBUF;
800    }
801    nvc0->constbuf_dirty[s] |= 1 << i;
802 
803    if (nvc0->constbuf[s][i].u.buf)
804       nv04_resource(nvc0->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
805    pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
806 
807    nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
808    if (nvc0->constbuf[s][i].user) {
809       nvc0->constbuf[s][i].u.data = cb->user_buffer;
810       nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
811       nvc0->constbuf_valid[s] |= 1 << i;
812       nvc0->constbuf_coherent[s] &= ~(1 << i);
813    } else
814    if (cb) {
815       nvc0->constbuf[s][i].offset = cb->buffer_offset;
816       nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
817       nvc0->constbuf_valid[s] |= 1 << i;
818       if (res && res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
819          nvc0->constbuf_coherent[s] |= 1 << i;
820       else
821          nvc0->constbuf_coherent[s] &= ~(1 << i);
822    }
823    else {
824       nvc0->constbuf_valid[s] &= ~(1 << i);
825       nvc0->constbuf_coherent[s] &= ~(1 << i);
826    }
827 }
828 
829 /* =============================================================================
830  */
831 
832 static void
nvc0_set_blend_color(struct pipe_context * pipe,const struct pipe_blend_color * bcol)833 nvc0_set_blend_color(struct pipe_context *pipe,
834                      const struct pipe_blend_color *bcol)
835 {
836     struct nvc0_context *nvc0 = nvc0_context(pipe);
837 
838     nvc0->blend_colour = *bcol;
839     nvc0->dirty_3d |= NVC0_NEW_3D_BLEND_COLOUR;
840 }
841 
842 static void
nvc0_set_stencil_ref(struct pipe_context * pipe,const struct pipe_stencil_ref * sr)843 nvc0_set_stencil_ref(struct pipe_context *pipe,
844                      const struct pipe_stencil_ref *sr)
845 {
846     struct nvc0_context *nvc0 = nvc0_context(pipe);
847 
848     nvc0->stencil_ref = *sr;
849     nvc0->dirty_3d |= NVC0_NEW_3D_STENCIL_REF;
850 }
851 
852 static void
nvc0_set_clip_state(struct pipe_context * pipe,const struct pipe_clip_state * clip)853 nvc0_set_clip_state(struct pipe_context *pipe,
854                     const struct pipe_clip_state *clip)
855 {
856     struct nvc0_context *nvc0 = nvc0_context(pipe);
857 
858     memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
859 
860     nvc0->dirty_3d |= NVC0_NEW_3D_CLIP;
861 }
862 
863 static void
nvc0_set_sample_mask(struct pipe_context * pipe,unsigned sample_mask)864 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
865 {
866     struct nvc0_context *nvc0 = nvc0_context(pipe);
867 
868     nvc0->sample_mask = sample_mask;
869     nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_MASK;
870 }
871 
872 static void
nvc0_set_min_samples(struct pipe_context * pipe,unsigned min_samples)873 nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
874 {
875    struct nvc0_context *nvc0 = nvc0_context(pipe);
876 
877    if (nvc0->min_samples != min_samples) {
878       nvc0->min_samples = min_samples;
879       nvc0->dirty_3d |= NVC0_NEW_3D_MIN_SAMPLES;
880    }
881 }
882 
883 static void
nvc0_set_framebuffer_state(struct pipe_context * pipe,const struct pipe_framebuffer_state * fb)884 nvc0_set_framebuffer_state(struct pipe_context *pipe,
885                            const struct pipe_framebuffer_state *fb)
886 {
887     struct nvc0_context *nvc0 = nvc0_context(pipe);
888 
889     nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
890 
891     util_copy_framebuffer_state(&nvc0->framebuffer, fb);
892 
893     nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER | NVC0_NEW_3D_SAMPLE_LOCATIONS |
894        NVC0_NEW_3D_TEXTURES;
895     nvc0->dirty_cp |= NVC0_NEW_CP_TEXTURES;
896 }
897 
898 static void
nvc0_set_sample_locations(struct pipe_context * pipe,size_t size,const uint8_t * locations)899 nvc0_set_sample_locations(struct pipe_context *pipe,
900                           size_t size, const uint8_t *locations)
901 {
902     struct nvc0_context *nvc0 = nvc0_context(pipe);
903 
904     nvc0->sample_locations_enabled = size && locations;
905     if (size > sizeof(nvc0->sample_locations))
906        size = sizeof(nvc0->sample_locations);
907     memcpy(nvc0->sample_locations, locations, size);
908 
909     nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_LOCATIONS;
910 }
911 
912 static void
nvc0_set_polygon_stipple(struct pipe_context * pipe,const struct pipe_poly_stipple * stipple)913 nvc0_set_polygon_stipple(struct pipe_context *pipe,
914                          const struct pipe_poly_stipple *stipple)
915 {
916     struct nvc0_context *nvc0 = nvc0_context(pipe);
917 
918     nvc0->stipple = *stipple;
919     nvc0->dirty_3d |= NVC0_NEW_3D_STIPPLE;
920 }
921 
922 static void
nvc0_set_scissor_states(struct pipe_context * pipe,unsigned start_slot,unsigned num_scissors,const struct pipe_scissor_state * scissor)923 nvc0_set_scissor_states(struct pipe_context *pipe,
924                         unsigned start_slot,
925                         unsigned num_scissors,
926                         const struct pipe_scissor_state *scissor)
927 {
928    struct nvc0_context *nvc0 = nvc0_context(pipe);
929    int i;
930 
931    assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
932    for (i = 0; i < num_scissors; i++) {
933       if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
934          continue;
935       nvc0->scissors[start_slot + i] = scissor[i];
936       nvc0->scissors_dirty |= 1 << (start_slot + i);
937       nvc0->dirty_3d |= NVC0_NEW_3D_SCISSOR;
938    }
939 }
940 
941 static void
nvc0_set_viewport_states(struct pipe_context * pipe,unsigned start_slot,unsigned num_viewports,const struct pipe_viewport_state * vpt)942 nvc0_set_viewport_states(struct pipe_context *pipe,
943                          unsigned start_slot,
944                          unsigned num_viewports,
945                          const struct pipe_viewport_state *vpt)
946 {
947    struct nvc0_context *nvc0 = nvc0_context(pipe);
948    int i;
949 
950    assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
951    for (i = 0; i < num_viewports; i++) {
952       if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
953          continue;
954       nvc0->viewports[start_slot + i] = vpt[i];
955       nvc0->viewports_dirty |= 1 << (start_slot + i);
956       nvc0->dirty_3d |= NVC0_NEW_3D_VIEWPORT;
957    }
958 
959 }
960 
961 static void
nvc0_set_window_rectangles(struct pipe_context * pipe,bool include,unsigned num_rectangles,const struct pipe_scissor_state * rectangles)962 nvc0_set_window_rectangles(struct pipe_context *pipe,
963                            bool include,
964                            unsigned num_rectangles,
965                            const struct pipe_scissor_state *rectangles)
966 {
967    struct nvc0_context *nvc0 = nvc0_context(pipe);
968 
969    nvc0->window_rect.inclusive = include;
970    nvc0->window_rect.rects = MIN2(num_rectangles, NVC0_MAX_WINDOW_RECTANGLES);
971    memcpy(nvc0->window_rect.rect, rectangles,
972           sizeof(struct pipe_scissor_state) * nvc0->window_rect.rects);
973 
974    nvc0->dirty_3d |= NVC0_NEW_3D_WINDOW_RECTS;
975 }
976 
977 static void
nvc0_set_tess_state(struct pipe_context * pipe,const float default_tess_outer[4],const float default_tess_inner[2])978 nvc0_set_tess_state(struct pipe_context *pipe,
979                     const float default_tess_outer[4],
980                     const float default_tess_inner[2])
981 {
982    struct nvc0_context *nvc0 = nvc0_context(pipe);
983 
984    memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float));
985    memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float));
986    nvc0->dirty_3d |= NVC0_NEW_3D_TESSFACTOR;
987 }
988 
989 static void
nvc0_set_vertex_buffers(struct pipe_context * pipe,unsigned start_slot,unsigned count,const struct pipe_vertex_buffer * vb)990 nvc0_set_vertex_buffers(struct pipe_context *pipe,
991                         unsigned start_slot, unsigned count,
992                         const struct pipe_vertex_buffer *vb)
993 {
994     struct nvc0_context *nvc0 = nvc0_context(pipe);
995     unsigned i;
996 
997     nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX);
998     nvc0->dirty_3d |= NVC0_NEW_3D_ARRAYS;
999 
1000     util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
1001                                   start_slot, count);
1002 
1003     if (!vb) {
1004        nvc0->vbo_user &= ~(((1ull << count) - 1) << start_slot);
1005        nvc0->constant_vbos &= ~(((1ull << count) - 1) << start_slot);
1006        nvc0->vtxbufs_coherent &= ~(((1ull << count) - 1) << start_slot);
1007        return;
1008     }
1009 
1010     for (i = 0; i < count; ++i) {
1011        unsigned dst_index = start_slot + i;
1012 
1013        if (vb[i].is_user_buffer) {
1014           nvc0->vbo_user |= 1 << dst_index;
1015           if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
1016              nvc0->constant_vbos |= 1 << dst_index;
1017           else
1018              nvc0->constant_vbos &= ~(1 << dst_index);
1019           nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1020        } else {
1021           nvc0->vbo_user &= ~(1 << dst_index);
1022           nvc0->constant_vbos &= ~(1 << dst_index);
1023 
1024           if (vb[i].buffer.resource &&
1025               vb[i].buffer.resource->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
1026              nvc0->vtxbufs_coherent |= (1 << dst_index);
1027           else
1028              nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1029        }
1030     }
1031 }
1032 
1033 static void
nvc0_vertex_state_bind(struct pipe_context * pipe,void * hwcso)1034 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1035 {
1036     struct nvc0_context *nvc0 = nvc0_context(pipe);
1037 
1038     nvc0->vertex = hwcso;
1039     nvc0->dirty_3d |= NVC0_NEW_3D_VERTEX;
1040 }
1041 
1042 static struct pipe_stream_output_target *
nvc0_so_target_create(struct pipe_context * pipe,struct pipe_resource * res,unsigned offset,unsigned size)1043 nvc0_so_target_create(struct pipe_context *pipe,
1044                       struct pipe_resource *res,
1045                       unsigned offset, unsigned size)
1046 {
1047    struct nv04_resource *buf = (struct nv04_resource *)res;
1048    struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
1049    if (!targ)
1050       return NULL;
1051 
1052    targ->pq = pipe->create_query(pipe, NVC0_HW_QUERY_TFB_BUFFER_OFFSET, 0);
1053    if (!targ->pq) {
1054       FREE(targ);
1055       return NULL;
1056    }
1057    targ->clean = true;
1058 
1059    targ->pipe.buffer_size = size;
1060    targ->pipe.buffer_offset = offset;
1061    targ->pipe.context = pipe;
1062    targ->pipe.buffer = NULL;
1063    pipe_resource_reference(&targ->pipe.buffer, res);
1064    pipe_reference_init(&targ->pipe.reference, 1);
1065 
1066    assert(buf->base.target == PIPE_BUFFER);
1067    util_range_add(&buf->base, &buf->valid_buffer_range, offset, offset + size);
1068 
1069    return &targ->pipe;
1070 }
1071 
1072 static void
nvc0_so_target_save_offset(struct pipe_context * pipe,struct pipe_stream_output_target * ptarg,unsigned index,bool * serialize)1073 nvc0_so_target_save_offset(struct pipe_context *pipe,
1074                            struct pipe_stream_output_target *ptarg,
1075                            unsigned index, bool *serialize)
1076 {
1077    struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1078 
1079    if (*serialize) {
1080       *serialize = false;
1081       PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1);
1082       IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0);
1083 
1084       NOUVEAU_DRV_STAT(nouveau_screen(pipe->screen), gpu_serialize_count, 1);
1085    }
1086 
1087    nvc0_query(targ->pq)->index = index;
1088    pipe->end_query(pipe, targ->pq);
1089 }
1090 
1091 static void
nvc0_so_target_destroy(struct pipe_context * pipe,struct pipe_stream_output_target * ptarg)1092 nvc0_so_target_destroy(struct pipe_context *pipe,
1093                        struct pipe_stream_output_target *ptarg)
1094 {
1095    struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1096    pipe->destroy_query(pipe, targ->pq);
1097    pipe_resource_reference(&targ->pipe.buffer, NULL);
1098    FREE(targ);
1099 }
1100 
1101 static void
nvc0_set_transform_feedback_targets(struct pipe_context * pipe,unsigned num_targets,struct pipe_stream_output_target ** targets,const unsigned * offsets)1102 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1103                                     unsigned num_targets,
1104                                     struct pipe_stream_output_target **targets,
1105                                     const unsigned *offsets)
1106 {
1107    struct nvc0_context *nvc0 = nvc0_context(pipe);
1108    unsigned i;
1109    bool serialize = true;
1110 
1111    assert(num_targets <= 4);
1112 
1113    for (i = 0; i < num_targets; ++i) {
1114       const bool changed = nvc0->tfbbuf[i] != targets[i];
1115       const bool append = (offsets[i] == ((unsigned)-1));
1116       if (!changed && append)
1117          continue;
1118       nvc0->tfbbuf_dirty |= 1 << i;
1119 
1120       if (nvc0->tfbbuf[i] && changed)
1121          nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1122 
1123       if (targets[i] && !append)
1124          nvc0_so_target(targets[i])->clean = true;
1125 
1126       pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1127    }
1128    for (; i < nvc0->num_tfbbufs; ++i) {
1129       if (nvc0->tfbbuf[i]) {
1130          nvc0->tfbbuf_dirty |= 1 << i;
1131          nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1132          pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1133       }
1134    }
1135    nvc0->num_tfbbufs = num_targets;
1136 
1137    if (nvc0->tfbbuf_dirty) {
1138       nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TFB);
1139       nvc0->dirty_3d |= NVC0_NEW_3D_TFB_TARGETS;
1140    }
1141 }
1142 
1143 static void
nvc0_bind_surfaces_range(struct nvc0_context * nvc0,const unsigned t,unsigned start,unsigned nr,struct pipe_surface ** psurfaces)1144 nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1145                          unsigned start, unsigned nr,
1146                          struct pipe_surface **psurfaces)
1147 {
1148    const unsigned end = start + nr;
1149    const unsigned mask = ((1 << nr) - 1) << start;
1150    unsigned i;
1151 
1152    if (psurfaces) {
1153       for (i = start; i < end; ++i) {
1154          const unsigned p = i - start;
1155          if (psurfaces[p])
1156             nvc0->surfaces_valid[t] |= (1 << i);
1157          else
1158             nvc0->surfaces_valid[t] &= ~(1 << i);
1159          pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1160       }
1161    } else {
1162       for (i = start; i < end; ++i)
1163          pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1164       nvc0->surfaces_valid[t] &= ~mask;
1165    }
1166    nvc0->surfaces_dirty[t] |= mask;
1167 
1168    if (t == 0)
1169       nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1170    else
1171       nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1172 }
1173 
1174 static void
nvc0_set_compute_resources(struct pipe_context * pipe,unsigned start,unsigned nr,struct pipe_surface ** resources)1175 nvc0_set_compute_resources(struct pipe_context *pipe,
1176                            unsigned start, unsigned nr,
1177                            struct pipe_surface **resources)
1178 {
1179    nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1180 
1181    nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1182 }
1183 
1184 static bool
nvc0_bind_images_range(struct nvc0_context * nvc0,const unsigned s,unsigned start,unsigned nr,const struct pipe_image_view * pimages)1185 nvc0_bind_images_range(struct nvc0_context *nvc0, const unsigned s,
1186                        unsigned start, unsigned nr,
1187                        const struct pipe_image_view *pimages)
1188 {
1189    const unsigned end = start + nr;
1190    unsigned mask = 0;
1191    unsigned i;
1192 
1193    assert(s < 6);
1194 
1195    if (pimages) {
1196       for (i = start; i < end; ++i) {
1197          struct pipe_image_view *img = &nvc0->images[s][i];
1198          const unsigned p = i - start;
1199 
1200          if (img->resource == pimages[p].resource &&
1201              img->format == pimages[p].format &&
1202              img->access == pimages[p].access) {
1203             if (img->resource == NULL)
1204                continue;
1205             if (img->resource->target == PIPE_BUFFER &&
1206                 img->u.buf.offset == pimages[p].u.buf.offset &&
1207                 img->u.buf.size == pimages[p].u.buf.size)
1208                continue;
1209             if (img->resource->target != PIPE_BUFFER &&
1210                 img->u.tex.first_layer == pimages[p].u.tex.first_layer &&
1211                 img->u.tex.last_layer == pimages[p].u.tex.last_layer &&
1212                 img->u.tex.level == pimages[p].u.tex.level)
1213                continue;
1214          }
1215 
1216          mask |= (1 << i);
1217          if (pimages[p].resource)
1218             nvc0->images_valid[s] |= (1 << i);
1219          else
1220             nvc0->images_valid[s] &= ~(1 << i);
1221 
1222          img->format = pimages[p].format;
1223          img->access = pimages[p].access;
1224          if (pimages[p].resource && pimages[p].resource->target == PIPE_BUFFER)
1225             img->u.buf = pimages[p].u.buf;
1226          else
1227             img->u.tex = pimages[p].u.tex;
1228 
1229          pipe_resource_reference(
1230                &img->resource, pimages[p].resource);
1231 
1232          if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1233             if (nvc0->images_tic[s][i]) {
1234                struct nv50_tic_entry *old =
1235                   nv50_tic_entry(nvc0->images_tic[s][i]);
1236                nvc0_screen_tic_unlock(nvc0->screen, old);
1237                pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1238             }
1239 
1240             nvc0->images_tic[s][i] =
1241                gm107_create_texture_view_from_image(&nvc0->base.pipe,
1242                                                     &pimages[p]);
1243          }
1244       }
1245       if (!mask)
1246          return false;
1247    } else {
1248       mask = ((1 << nr) - 1) << start;
1249       if (!(nvc0->images_valid[s] & mask))
1250          return false;
1251       for (i = start; i < end; ++i) {
1252          pipe_resource_reference(&nvc0->images[s][i].resource, NULL);
1253          if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1254             struct nv50_tic_entry *old = nv50_tic_entry(nvc0->images_tic[s][i]);
1255             if (old) {
1256                nvc0_screen_tic_unlock(nvc0->screen, old);
1257                pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1258             }
1259          }
1260       }
1261       nvc0->images_valid[s] &= ~mask;
1262    }
1263    nvc0->images_dirty[s] |= mask;
1264 
1265    if (s == 5)
1266       nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1267    else
1268       nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1269 
1270    return true;
1271 }
1272 
1273 static void
nvc0_set_shader_images(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned nr,const struct pipe_image_view * images)1274 nvc0_set_shader_images(struct pipe_context *pipe,
1275                        enum pipe_shader_type shader,
1276                        unsigned start, unsigned nr,
1277                        const struct pipe_image_view *images)
1278 {
1279    const unsigned s = nvc0_shader_stage(shader);
1280    if (!nvc0_bind_images_range(nvc0_context(pipe), s, start, nr, images))
1281       return;
1282 
1283    if (s == 5)
1284       nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1285    else
1286       nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SURFACES;
1287 }
1288 
1289 static bool
nvc0_bind_buffers_range(struct nvc0_context * nvc0,const unsigned t,unsigned start,unsigned nr,const struct pipe_shader_buffer * pbuffers)1290 nvc0_bind_buffers_range(struct nvc0_context *nvc0, const unsigned t,
1291                         unsigned start, unsigned nr,
1292                         const struct pipe_shader_buffer *pbuffers)
1293 {
1294    const unsigned end = start + nr;
1295    unsigned mask = 0;
1296    unsigned i;
1297 
1298    assert(t < 6);
1299 
1300    if (pbuffers) {
1301       for (i = start; i < end; ++i) {
1302          struct pipe_shader_buffer *buf = &nvc0->buffers[t][i];
1303          const unsigned p = i - start;
1304          if (buf->buffer == pbuffers[p].buffer &&
1305              buf->buffer_offset == pbuffers[p].buffer_offset &&
1306              buf->buffer_size == pbuffers[p].buffer_size)
1307             continue;
1308 
1309          mask |= (1 << i);
1310          if (pbuffers[p].buffer)
1311             nvc0->buffers_valid[t] |= (1 << i);
1312          else
1313             nvc0->buffers_valid[t] &= ~(1 << i);
1314          buf->buffer_offset = pbuffers[p].buffer_offset;
1315          buf->buffer_size = pbuffers[p].buffer_size;
1316          pipe_resource_reference(&buf->buffer, pbuffers[p].buffer);
1317       }
1318       if (!mask)
1319          return false;
1320    } else {
1321       mask = ((1 << nr) - 1) << start;
1322       if (!(nvc0->buffers_valid[t] & mask))
1323          return false;
1324       for (i = start; i < end; ++i)
1325          pipe_resource_reference(&nvc0->buffers[t][i].buffer, NULL);
1326       nvc0->buffers_valid[t] &= ~mask;
1327    }
1328    nvc0->buffers_dirty[t] |= mask;
1329 
1330    if (t == 5)
1331       nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_BUF);
1332    else
1333       nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_BUF);
1334 
1335    return true;
1336 }
1337 
1338 static void
nvc0_set_shader_buffers(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned nr,const struct pipe_shader_buffer * buffers,unsigned writable_bitmask)1339 nvc0_set_shader_buffers(struct pipe_context *pipe,
1340                         enum pipe_shader_type shader,
1341                         unsigned start, unsigned nr,
1342                         const struct pipe_shader_buffer *buffers,
1343                         unsigned writable_bitmask)
1344 {
1345    const unsigned s = nvc0_shader_stage(shader);
1346    if (!nvc0_bind_buffers_range(nvc0_context(pipe), s, start, nr, buffers))
1347       return;
1348 
1349    if (s == 5)
1350       nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_BUFFERS;
1351    else
1352       nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_BUFFERS;
1353 }
1354 
1355 static inline void
nvc0_set_global_handle(uint32_t * phandle,struct pipe_resource * res)1356 nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1357 {
1358    struct nv04_resource *buf = nv04_resource(res);
1359    if (buf) {
1360       uint64_t address = buf->address + *phandle;
1361       /* even though it's a pointer to uint32_t that's fine */
1362       memcpy(phandle, &address, 8);
1363    } else {
1364       *phandle = 0;
1365    }
1366 }
1367 
1368 static void
nvc0_set_global_bindings(struct pipe_context * pipe,unsigned start,unsigned nr,struct pipe_resource ** resources,uint32_t ** handles)1369 nvc0_set_global_bindings(struct pipe_context *pipe,
1370                          unsigned start, unsigned nr,
1371                          struct pipe_resource **resources,
1372                          uint32_t **handles)
1373 {
1374    struct nvc0_context *nvc0 = nvc0_context(pipe);
1375    struct pipe_resource **ptr;
1376    unsigned i;
1377    const unsigned end = start + nr;
1378 
1379    if (!nr)
1380       return;
1381 
1382    if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1383       const unsigned old_size = nvc0->global_residents.size;
1384       if (util_dynarray_resize(&nvc0->global_residents, struct pipe_resource *, end)) {
1385          memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1386                 nvc0->global_residents.size - old_size);
1387       } else {
1388          NOUVEAU_ERR("Could not resize global residents array\n");
1389          return;
1390       }
1391    }
1392 
1393    if (resources) {
1394       ptr = util_dynarray_element(
1395          &nvc0->global_residents, struct pipe_resource *, start);
1396       for (i = 0; i < nr; ++i) {
1397          pipe_resource_reference(&ptr[i], resources[i]);
1398          nvc0_set_global_handle(handles[i], resources[i]);
1399       }
1400    } else {
1401       ptr = util_dynarray_element(
1402          &nvc0->global_residents, struct pipe_resource *, start);
1403       for (i = 0; i < nr; ++i)
1404          pipe_resource_reference(&ptr[i], NULL);
1405    }
1406 
1407    nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1408 
1409    nvc0->dirty_cp |= NVC0_NEW_CP_GLOBALS;
1410 }
1411 
1412 void
nvc0_init_state_functions(struct nvc0_context * nvc0)1413 nvc0_init_state_functions(struct nvc0_context *nvc0)
1414 {
1415    struct pipe_context *pipe = &nvc0->base.pipe;
1416 
1417    pipe->create_blend_state = nvc0_blend_state_create;
1418    pipe->bind_blend_state = nvc0_blend_state_bind;
1419    pipe->delete_blend_state = nvc0_blend_state_delete;
1420 
1421    pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1422    pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1423    pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1424 
1425    pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1426    pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1427    pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1428 
1429    pipe->create_sampler_state = nv50_sampler_state_create;
1430    pipe->delete_sampler_state = nvc0_sampler_state_delete;
1431    pipe->bind_sampler_states = nvc0_bind_sampler_states;
1432 
1433    pipe->create_sampler_view = nvc0_create_sampler_view;
1434    pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1435    pipe->set_sampler_views = nvc0_set_sampler_views;
1436 
1437    pipe->create_vs_state = nvc0_vp_state_create;
1438    pipe->create_fs_state = nvc0_fp_state_create;
1439    pipe->create_gs_state = nvc0_gp_state_create;
1440    pipe->create_tcs_state = nvc0_tcp_state_create;
1441    pipe->create_tes_state = nvc0_tep_state_create;
1442    pipe->bind_vs_state = nvc0_vp_state_bind;
1443    pipe->bind_fs_state = nvc0_fp_state_bind;
1444    pipe->bind_gs_state = nvc0_gp_state_bind;
1445    pipe->bind_tcs_state = nvc0_tcp_state_bind;
1446    pipe->bind_tes_state = nvc0_tep_state_bind;
1447    pipe->delete_vs_state = nvc0_sp_state_delete;
1448    pipe->delete_fs_state = nvc0_sp_state_delete;
1449    pipe->delete_gs_state = nvc0_sp_state_delete;
1450    pipe->delete_tcs_state = nvc0_sp_state_delete;
1451    pipe->delete_tes_state = nvc0_sp_state_delete;
1452 
1453    pipe->create_compute_state = nvc0_cp_state_create;
1454    pipe->bind_compute_state = nvc0_cp_state_bind;
1455    pipe->delete_compute_state = nvc0_sp_state_delete;
1456 
1457    pipe->set_blend_color = nvc0_set_blend_color;
1458    pipe->set_stencil_ref = nvc0_set_stencil_ref;
1459    pipe->set_clip_state = nvc0_set_clip_state;
1460    pipe->set_sample_mask = nvc0_set_sample_mask;
1461    pipe->set_min_samples = nvc0_set_min_samples;
1462    pipe->set_constant_buffer = nvc0_set_constant_buffer;
1463    pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1464    pipe->set_sample_locations = nvc0_set_sample_locations;
1465    pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1466    pipe->set_scissor_states = nvc0_set_scissor_states;
1467    pipe->set_viewport_states = nvc0_set_viewport_states;
1468    pipe->set_window_rectangles = nvc0_set_window_rectangles;
1469    pipe->set_tess_state = nvc0_set_tess_state;
1470 
1471    pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1472    pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1473    pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1474 
1475    pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1476 
1477    pipe->create_stream_output_target = nvc0_so_target_create;
1478    pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1479    pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1480 
1481    pipe->set_global_binding = nvc0_set_global_bindings;
1482    pipe->set_compute_resources = nvc0_set_compute_resources;
1483    pipe->set_shader_images = nvc0_set_shader_images;
1484    pipe->set_shader_buffers = nvc0_set_shader_buffers;
1485 
1486    nvc0->sample_mask = ~0;
1487    nvc0->min_samples = 1;
1488    nvc0->default_tess_outer[0] =
1489    nvc0->default_tess_outer[1] =
1490    nvc0->default_tess_outer[2] =
1491    nvc0->default_tess_outer[3] = 1.0;
1492    nvc0->default_tess_inner[0] =
1493    nvc0->default_tess_inner[1] = 1.0;
1494 }
1495