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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * UniPhier SC (System Control) block registers
4  *
5  * Copyright (C) 2011-2015 Panasonic Corporation
6  * Copyright (C) 2015-2016 Socionext Inc.
7  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8  */
9 
10 #ifndef ARCH_SC_REGS_H
11 #define ARCH_SC_REGS_H
12 
13 #ifndef __ASSEMBLY__
14 #include <linux/compiler.h>
15 #define sc_base			((void __iomem *)SC_BASE)
16 #endif
17 
18 #define SC_BASE			0x61840000
19 
20 #define SC_DPLLCTRL		0x1200
21 #define SC_DPLLCTRL_SSC_EN		(0x1 << 31)
22 #define SC_DPLLCTRL_FOUTMODE_MASK        (0xf << 16)
23 #define SC_DPLLCTRL_SSC_RATE		(0x1 << 15)
24 
25 #define SC_DPLLCTRL2		0x1204
26 #define SC_DPLLCTRL2_NRSTDS		(0x1 << 28)
27 
28 #define SC_DPLLCTRL3		0x1208
29 #define SC_DPLLCTRL3_LPFSEL_COEF2	(0x0 << 31)
30 #define SC_DPLLCTRL3_LPFSEL_COEF3	(0x1 << 31)
31 
32 #define SC_UPLLCTRL		0x1210
33 
34 #define SC_VPLL27ACTRL		0x1270
35 #define SC_VPLL27ACTRL2		0x1274
36 #define SC_VPLL27ACTRL3		0x1278
37 
38 #define SC_VPLL27BCTRL		0x1290
39 #define SC_VPLL27BCTRL2		0x1294
40 #define SC_VPLL27BCTRL3		0x1298
41 
42 #define SC_RSTCTRL		0x2000
43 #define SC_RSTCTRL_NRST_USB3B0		(0x1 << 17)	/* USB3 #0 bus */
44 #define SC_RSTCTRL_NRST_USB3C0		(0x1 << 16)	/* USB3 #0 core */
45 #define SC_RSTCTRL_NRST_ETHER		(0x1 << 12)
46 #define SC_RSTCTRL_NRST_GIO		(0x1 <<  6)
47 /* Pro4 or older */
48 #define SC_RSTCTRL_NRST_UMC1		(0x1 <<  5)
49 #define SC_RSTCTRL_NRST_UMC0		(0x1 <<  4)
50 #define SC_RSTCTRL_NRST_NAND		(0x1 <<  2)
51 
52 #define SC_RSTCTRL2		0x2004
53 #define SC_RSTCTRL2_NRST_USB3B1		(0x1 << 17)	/* USB3 #1 bus */
54 #define SC_RSTCTRL2_NRST_USB3C1		(0x1 << 16)	/* USB3 #1 core */
55 
56 #define SC_RSTCTRL3		0x2008
57 
58 /* Pro5 or newer */
59 #define SC_RSTCTRL4		0x200c
60 #define SC_RSTCTRL4_NRST_UMCSB		(0x1 << 12)	/* UMC system bus */
61 #define SC_RSTCTRL4_NRST_UMCA2		(0x1 << 10)	/* UMC ch2 standby */
62 #define SC_RSTCTRL4_NRST_UMCA1		(0x1 <<  9)	/* UMC ch1 standby */
63 #define SC_RSTCTRL4_NRST_UMCA0		(0x1 <<  8)	/* UMC ch0 standby */
64 #define SC_RSTCTRL4_NRST_UMC32		(0x1 <<  6)	/* UMC ch2 */
65 #define SC_RSTCTRL4_NRST_UMC31		(0x1 <<  5)	/* UMC ch1 */
66 #define SC_RSTCTRL4_NRST_UMC30		(0x1 <<  4)	/* UMC ch0 */
67 
68 #define SC_RSTCTRL5		0x2010
69 
70 #define SC_RSTCTRL6		0x2014
71 
72 #define SC_CLKCTRL		0x2104
73 #define SC_CLKCTRL_CEN_USB31		(0x1 << 17)	/* USB3 #1 */
74 #define SC_CLKCTRL_CEN_USB30		(0x1 << 16)	/* USB3 #0 */
75 #define SC_CLKCTRL_CEN_ETHER		(0x1 << 12)
76 #define SC_CLKCTRL_CEN_GIO		(0x1 <<  6)
77 /* Pro4 or older */
78 #define SC_CLKCTRL_CEN_UMC		(0x1 <<  4)
79 #define SC_CLKCTRL_CEN_NAND		(0x1 <<  2)
80 #define SC_CLKCTRL_CEN_SBC		(0x1 <<  1)
81 #define SC_CLKCTRL_CEN_PERI		(0x1 <<  0)
82 
83 /* Pro5 or newer */
84 #define SC_CLKCTRL4		0x210c
85 #define SC_CLKCTRL4_CEN_UMCSB		(0x1 << 12)	/* UMC system bus */
86 #define SC_CLKCTRL4_CEN_UMC2		(0x1 <<  2)	/* UMC ch2 */
87 #define SC_CLKCTRL4_CEN_UMC1		(0x1 <<  1)	/* UMC ch1 */
88 #define SC_CLKCTRL4_CEN_UMC0		(0x1 <<  0)	/* UMC ch0 */
89 
90 /* System reset control register */
91 #define SC_IRQTIMSET		0x3000
92 #define SC_SLFRSTSEL		0x3010
93 #define SC_SLFRSTCTL		0x3014
94 
95 #endif /* ARCH_SC_REGS_H */
96