1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
4 *
5 * (C) Copyright 2006
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
9 * (C) Copyright 2003 Motorola Inc.
10 * Xianghua Xiao (X.Xiao@motorola.com)
11 */
12
13 #ifndef CONFIG_MPC83XX_SDRAM
14
15 #include <common.h>
16 #include <cpu_func.h>
17 #include <vsprintf.h>
18 #include <asm/processor.h>
19 #include <asm/io.h>
20 #include <i2c.h>
21 #include <spd.h>
22 #include <asm/mmu.h>
23 #include <spd_sdram.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
board_add_ram_info(int use_default)27 void board_add_ram_info(int use_default)
28 {
29 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
30 volatile ddr83xx_t *ddr = &immap->ddr;
31 char buf[32];
32
33 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
34 >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
35
36 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
37 if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
38 puts(", 16-bit");
39 else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
40 puts(", 32-bit");
41 else
42 puts(", unknown width");
43 #else
44 if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
45 puts(", 32-bit");
46 else
47 puts(", 64-bit");
48 #endif
49
50 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
51 puts(", ECC on");
52 else
53 puts(", ECC off");
54
55 printf(", %s MHz)", strmhz(buf, gd->mem_clk));
56
57 #if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
58 puts("\nSDRAM: ");
59 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
60 #endif
61 }
62
63 #ifdef CONFIG_SPD_EEPROM
64 #ifndef CONFIG_SYS_READ_SPD
65 #define CONFIG_SYS_READ_SPD i2c_read
66 #endif
67 #ifndef SPD_EEPROM_OFFSET
68 #define SPD_EEPROM_OFFSET 0
69 #endif
70 #ifndef SPD_EEPROM_ADDR_LEN
71 #define SPD_EEPROM_ADDR_LEN 1
72 #endif
73
74 /*
75 * Convert picoseconds into clock cycles (rounding up if needed).
76 */
77 int
picos_to_clk(int picos)78 picos_to_clk(int picos)
79 {
80 unsigned int mem_bus_clk;
81 int clks;
82
83 mem_bus_clk = gd->mem_clk >> 1;
84 clks = picos / (1000000000 / (mem_bus_clk / 1000));
85 if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
86 clks++;
87
88 return clks;
89 }
90
banksize(unsigned char row_dens)91 unsigned int banksize(unsigned char row_dens)
92 {
93 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
94 }
95
read_spd(uint addr)96 int read_spd(uint addr)
97 {
98 return ((int) addr);
99 }
100
101 #undef SPD_DEBUG
102 #ifdef SPD_DEBUG
spd_debug(spd_eeprom_t * spd)103 static void spd_debug(spd_eeprom_t *spd)
104 {
105 printf ("\nDIMM type: %-18.18s\n", spd->mpart);
106 printf ("SPD size: %d\n", spd->info_size);
107 printf ("EEPROM size: %d\n", 1 << spd->chip_size);
108 printf ("Memory type: %d\n", spd->mem_type);
109 printf ("Row addr: %d\n", spd->nrow_addr);
110 printf ("Column addr: %d\n", spd->ncol_addr);
111 printf ("# of rows: %d\n", spd->nrows);
112 printf ("Row density: %d\n", spd->row_dens);
113 printf ("# of banks: %d\n", spd->nbanks);
114 printf ("Data width: %d\n",
115 256 * spd->dataw_msb + spd->dataw_lsb);
116 printf ("Chip width: %d\n", spd->primw);
117 printf ("Refresh rate: %02X\n", spd->refresh);
118 printf ("CAS latencies: %02X\n", spd->cas_lat);
119 printf ("Write latencies: %02X\n", spd->write_lat);
120 printf ("tRP: %d\n", spd->trp);
121 printf ("tRCD: %d\n", spd->trcd);
122 printf ("\n");
123 }
124 #endif /* SPD_DEBUG */
125
spd_sdram()126 long int spd_sdram()
127 {
128 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
129 volatile ddr83xx_t *ddr = &immap->ddr;
130 volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
131 spd_eeprom_t spd;
132 unsigned int n_ranks;
133 unsigned int odt_rd_cfg, odt_wr_cfg;
134 unsigned char twr_clk, twtr_clk;
135 unsigned int sdram_type;
136 unsigned int memsize;
137 unsigned int law_size;
138 unsigned char caslat, caslat_ctrl;
139 unsigned int trfc, trfc_clk, trfc_low;
140 unsigned int trcd_clk, trtp_clk;
141 unsigned char cke_min_clk;
142 unsigned char add_lat, wr_lat;
143 unsigned char wr_data_delay;
144 unsigned char four_act;
145 unsigned char cpo;
146 unsigned char burstlen;
147 unsigned char odt_cfg, mode_odt_enable;
148 unsigned int max_bus_clk;
149 unsigned int max_data_rate, effective_data_rate;
150 unsigned int ddrc_clk;
151 unsigned int refresh_clk;
152 unsigned int sdram_cfg;
153 unsigned int ddrc_ecc_enable;
154 unsigned int pvr = get_pvr();
155
156 /*
157 * First disable the memory controller (could be enabled
158 * by the debugger)
159 */
160 clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0);
161 sync();
162 isync();
163
164 /* Read SPD parameters with I2C */
165 CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET,
166 SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd));
167 #ifdef SPD_DEBUG
168 spd_debug(&spd);
169 #endif
170 /* Check the memory type */
171 if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
172 debug("DDR: Module mem type is %02X\n", spd.mem_type);
173 return 0;
174 }
175
176 /* Check the number of physical bank */
177 if (spd.mem_type == SPD_MEMTYPE_DDR) {
178 n_ranks = spd.nrows;
179 } else {
180 n_ranks = (spd.nrows & 0x7) + 1;
181 }
182
183 if (n_ranks > 2) {
184 printf("DDR: The number of physical bank is %02X\n", n_ranks);
185 return 0;
186 }
187
188 /* Check if the number of row of the module is in the range of DDRC */
189 if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
190 printf("DDR: Row number is out of range of DDRC, row=%02X\n",
191 spd.nrow_addr);
192 return 0;
193 }
194
195 /* Check if the number of col of the module is in the range of DDRC */
196 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
197 printf("DDR: Col number is out of range of DDRC, col=%02X\n",
198 spd.ncol_addr);
199 return 0;
200 }
201
202 #ifdef CONFIG_SYS_DDRCDR_VALUE
203 /*
204 * Adjust DDR II IO voltage biasing. It just makes it work.
205 */
206 if(spd.mem_type == SPD_MEMTYPE_DDR2) {
207 immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
208 }
209 udelay(50000);
210 #endif
211
212 /*
213 * ODT configuration recommendation from DDR Controller Chapter.
214 */
215 odt_rd_cfg = 0; /* Never assert ODT */
216 odt_wr_cfg = 0; /* Never assert ODT */
217 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
218 odt_wr_cfg = 1; /* Assert ODT on writes to CSn */
219 }
220
221 /* Setup DDR chip select register */
222 #ifdef CONFIG_SYS_83XX_DDR_USES_CS0
223 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
224 ddr->cs_config[0] = ( 1 << 31
225 | (odt_rd_cfg << 20)
226 | (odt_wr_cfg << 16)
227 | ((spd.nbanks == 8 ? 1 : 0) << 14)
228 | ((spd.nrow_addr - 12) << 8)
229 | (spd.ncol_addr - 8) );
230 debug("\n");
231 debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
232 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
233
234 if (n_ranks == 2) {
235 ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
236 | ((banksize(spd.row_dens) >> 23) - 1) );
237 ddr->cs_config[1] = ( 1<<31
238 | (odt_rd_cfg << 20)
239 | (odt_wr_cfg << 16)
240 | ((spd.nbanks == 8 ? 1 : 0) << 14)
241 | ((spd.nrow_addr - 12) << 8)
242 | (spd.ncol_addr - 8) );
243 debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
244 debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
245 }
246
247 #else
248 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
249 ddr->cs_config[2] = ( 1 << 31
250 | (odt_rd_cfg << 20)
251 | (odt_wr_cfg << 16)
252 | ((spd.nbanks == 8 ? 1 : 0) << 14)
253 | ((spd.nrow_addr - 12) << 8)
254 | (spd.ncol_addr - 8) );
255 debug("\n");
256 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
257 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
258
259 if (n_ranks == 2) {
260 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
261 | ((banksize(spd.row_dens) >> 23) - 1) );
262 ddr->cs_config[3] = ( 1<<31
263 | (odt_rd_cfg << 20)
264 | (odt_wr_cfg << 16)
265 | ((spd.nbanks == 8 ? 1 : 0) << 14)
266 | ((spd.nrow_addr - 12) << 8)
267 | (spd.ncol_addr - 8) );
268 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
269 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
270 }
271 #endif
272
273 /*
274 * Figure out memory size in Megabytes.
275 */
276 memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
277
278 /*
279 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
280 */
281 law_size = 19 + __ilog2(memsize);
282
283 /*
284 * Set up LAWBAR for all of DDR.
285 */
286 ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
287 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
288 debug("DDR:bar=0x%08x\n", ecm->bar);
289 debug("DDR:ar=0x%08x\n", ecm->ar);
290
291 /*
292 * Find the largest CAS by locating the highest 1 bit
293 * in the spd.cas_lat field. Translate it to a DDR
294 * controller field value:
295 *
296 * CAS Lat DDR I DDR II Ctrl
297 * Clocks SPD Bit SPD Bit Value
298 * ------- ------- ------- -----
299 * 1.0 0 0001
300 * 1.5 1 0010
301 * 2.0 2 2 0011
302 * 2.5 3 0100
303 * 3.0 4 3 0101
304 * 3.5 5 0110
305 * 4.0 6 4 0111
306 * 4.5 1000
307 * 5.0 5 1001
308 */
309 caslat = __ilog2(spd.cas_lat);
310 if ((spd.mem_type == SPD_MEMTYPE_DDR)
311 && (caslat > 6)) {
312 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
313 return 0;
314 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
315 && (caslat < 2 || caslat > 5)) {
316 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
317 spd.cas_lat);
318 return 0;
319 }
320 debug("DDR: caslat SPD bit is %d\n", caslat);
321
322 max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
323 + (spd.clk_cycle & 0x0f));
324 max_data_rate = max_bus_clk * 2;
325
326 debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate);
327
328 ddrc_clk = gd->mem_clk / 1000000;
329 effective_data_rate = 0;
330
331 if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */
332 if (spd.cas_lat & 0x08)
333 caslat = 3;
334 else
335 caslat = 4;
336 if (ddrc_clk <= 460 && ddrc_clk > 350)
337 effective_data_rate = 400;
338 else if (ddrc_clk <=350 && ddrc_clk > 280)
339 effective_data_rate = 333;
340 else if (ddrc_clk <= 280 && ddrc_clk > 230)
341 effective_data_rate = 266;
342 else
343 effective_data_rate = 200;
344 } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
345 if (ddrc_clk <= 460 && ddrc_clk > 350) {
346 /* DDR controller clk at 350~460 */
347 effective_data_rate = 400; /* 5ns */
348 caslat = caslat;
349 } else if (ddrc_clk <= 350 && ddrc_clk > 280) {
350 /* DDR controller clk at 280~350 */
351 effective_data_rate = 333; /* 6ns */
352 if (spd.clk_cycle2 == 0x60)
353 caslat = caslat - 1;
354 else
355 caslat = caslat;
356 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
357 /* DDR controller clk at 230~280 */
358 effective_data_rate = 266; /* 7.5ns */
359 if (spd.clk_cycle3 == 0x75)
360 caslat = caslat - 2;
361 else if (spd.clk_cycle2 == 0x75)
362 caslat = caslat - 1;
363 else
364 caslat = caslat;
365 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
366 /* DDR controller clk at 90~230 */
367 effective_data_rate = 200; /* 10ns */
368 if (spd.clk_cycle3 == 0xa0)
369 caslat = caslat - 2;
370 else if (spd.clk_cycle2 == 0xa0)
371 caslat = caslat - 1;
372 else
373 caslat = caslat;
374 }
375 } else if (max_data_rate >= 323) { /* it is DDR 333 */
376 if (ddrc_clk <= 350 && ddrc_clk > 280) {
377 /* DDR controller clk at 280~350 */
378 effective_data_rate = 333; /* 6ns */
379 caslat = caslat;
380 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
381 /* DDR controller clk at 230~280 */
382 effective_data_rate = 266; /* 7.5ns */
383 if (spd.clk_cycle2 == 0x75)
384 caslat = caslat - 1;
385 else
386 caslat = caslat;
387 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
388 /* DDR controller clk at 90~230 */
389 effective_data_rate = 200; /* 10ns */
390 if (spd.clk_cycle3 == 0xa0)
391 caslat = caslat - 2;
392 else if (spd.clk_cycle2 == 0xa0)
393 caslat = caslat - 1;
394 else
395 caslat = caslat;
396 }
397 } else if (max_data_rate >= 256) { /* it is DDR 266 */
398 if (ddrc_clk <= 350 && ddrc_clk > 280) {
399 /* DDR controller clk at 280~350 */
400 printf("DDR: DDR controller freq is more than "
401 "max data rate of the module\n");
402 return 0;
403 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
404 /* DDR controller clk at 230~280 */
405 effective_data_rate = 266; /* 7.5ns */
406 caslat = caslat;
407 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
408 /* DDR controller clk at 90~230 */
409 effective_data_rate = 200; /* 10ns */
410 if (spd.clk_cycle2 == 0xa0)
411 caslat = caslat - 1;
412 }
413 } else if (max_data_rate >= 190) { /* it is DDR 200 */
414 if (ddrc_clk <= 350 && ddrc_clk > 230) {
415 /* DDR controller clk at 230~350 */
416 printf("DDR: DDR controller freq is more than "
417 "max data rate of the module\n");
418 return 0;
419 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
420 /* DDR controller clk at 90~230 */
421 effective_data_rate = 200; /* 10ns */
422 caslat = caslat;
423 }
424 }
425
426 debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate);
427 debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
428
429 /*
430 * Errata DDR6 work around: input enable 2 cycles earlier.
431 * including MPC834X Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
432 */
433 if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
434 if (caslat == 2)
435 ddr->debug_reg = 0x201c0000; /* CL=2 */
436 else if (caslat == 3)
437 ddr->debug_reg = 0x202c0000; /* CL=2.5 */
438 else if (caslat == 4)
439 ddr->debug_reg = 0x202c0000; /* CL=3.0 */
440
441 sync();
442
443 debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
444 }
445
446 /*
447 * Convert caslat clocks to DDR controller value.
448 * Force caslat_ctrl to be DDR Controller field-sized.
449 */
450 if (spd.mem_type == SPD_MEMTYPE_DDR) {
451 caslat_ctrl = (caslat + 1) & 0x07;
452 } else {
453 caslat_ctrl = (2 * caslat - 1) & 0x0f;
454 }
455
456 debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
457 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
458 caslat, caslat_ctrl);
459
460 /*
461 * Timing Config 0.
462 * Avoid writing for DDR I.
463 */
464 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
465 unsigned char taxpd_clk = 8; /* By the book. */
466 unsigned char tmrd_clk = 2; /* By the book. */
467 unsigned char act_pd_exit = 2; /* Empirical? */
468 unsigned char pre_pd_exit = 6; /* Empirical? */
469
470 ddr->timing_cfg_0 = (0
471 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
472 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
473 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
474 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
475 );
476 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
477 }
478
479 /*
480 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
481 * use conservative value.
482 * For DDR II, they are bytes 36 and 37, in quarter nanos.
483 */
484
485 if (spd.mem_type == SPD_MEMTYPE_DDR) {
486 twr_clk = 3; /* Clocks */
487 twtr_clk = 1; /* Clocks */
488 } else {
489 twr_clk = picos_to_clk(spd.twr * 250);
490 twtr_clk = picos_to_clk(spd.twtr * 250);
491 if (twtr_clk < 2)
492 twtr_clk = 2;
493 }
494
495 /*
496 * Calculate Trfc, in picos.
497 * DDR I: Byte 42 straight up in ns.
498 * DDR II: Byte 40 and 42 swizzled some, in ns.
499 */
500 if (spd.mem_type == SPD_MEMTYPE_DDR) {
501 trfc = spd.trfc * 1000; /* up to ps */
502 } else {
503 unsigned int byte40_table_ps[8] = {
504 0,
505 250,
506 330,
507 500,
508 660,
509 750,
510 0,
511 0
512 };
513
514 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
515 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
516 }
517 trfc_clk = picos_to_clk(trfc);
518
519 /*
520 * Trcd, Byte 29, from quarter nanos to ps and clocks.
521 */
522 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
523
524 /*
525 * Convert trfc_clk to DDR controller fields. DDR I should
526 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
527 * 83xx controller has an extended REFREC field of three bits.
528 * The controller automatically adds 8 clocks to this value,
529 * so preadjust it down 8 first before splitting it up.
530 */
531 trfc_low = (trfc_clk - 8) & 0xf;
532
533 ddr->timing_cfg_1 =
534 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */
535 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
536 (trcd_clk << 20 ) | /* ACTTORW */
537 (caslat_ctrl << 16 ) | /* CASLAT */
538 (trfc_low << 12 ) | /* REFEC */
539 ((twr_clk & 0x07) << 8) | /* WRRREC */
540 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */
541 ((twtr_clk & 0x07) << 0) /* WRTORD */
542 );
543
544 /*
545 * Additive Latency
546 * For DDR I, 0.
547 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
548 * which comes from Trcd, and also note that:
549 * add_lat + caslat must be >= 4
550 */
551 add_lat = 0;
552 if (spd.mem_type == SPD_MEMTYPE_DDR2
553 && (odt_wr_cfg || odt_rd_cfg)
554 && (caslat < 4)) {
555 add_lat = 4 - caslat;
556 if ((add_lat + caslat) < 4) {
557 add_lat = 0;
558 }
559 }
560
561 /*
562 * Write Data Delay
563 * Historically 0x2 == 4/8 clock delay.
564 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
565 */
566 wr_data_delay = 2;
567 #ifdef CONFIG_SYS_DDR_WRITE_DATA_DELAY
568 wr_data_delay = CONFIG_SYS_DDR_WRITE_DATA_DELAY;
569 #endif
570
571 /*
572 * Write Latency
573 * Read to Precharge
574 * Minimum CKE Pulse Width.
575 * Four Activate Window
576 */
577 if (spd.mem_type == SPD_MEMTYPE_DDR) {
578 /*
579 * This is a lie. It should really be 1, but if it is
580 * set to 1, bits overlap into the old controller's
581 * otherwise unused ACSM field. If we leave it 0, then
582 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
583 */
584 wr_lat = 0;
585
586 trtp_clk = 2; /* By the book. */
587 cke_min_clk = 1; /* By the book. */
588 four_act = 1; /* By the book. */
589
590 } else {
591 wr_lat = caslat - 1;
592
593 /* Convert SPD value from quarter nanos to picos. */
594 trtp_clk = picos_to_clk(spd.trtp * 250);
595 if (trtp_clk < 2)
596 trtp_clk = 2;
597 trtp_clk += add_lat;
598
599 cke_min_clk = 3; /* By the book. */
600 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
601 }
602
603 /*
604 * Empirically set ~MCAS-to-preamble override for DDR 2.
605 * Your mileage will vary.
606 */
607 cpo = 0;
608 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
609 #ifdef CONFIG_SYS_DDR_CPO
610 cpo = CONFIG_SYS_DDR_CPO;
611 #else
612 if (effective_data_rate == 266) {
613 cpo = 0x4; /* READ_LAT + 1/2 */
614 } else if (effective_data_rate == 333) {
615 cpo = 0x6; /* READ_LAT + 1 */
616 } else if (effective_data_rate == 400) {
617 cpo = 0x7; /* READ_LAT + 5/4 */
618 } else {
619 /* Automatic calibration */
620 cpo = 0x1f;
621 }
622 #endif
623 }
624
625 ddr->timing_cfg_2 = (0
626 | ((add_lat & 0x7) << 28) /* ADD_LAT */
627 | ((cpo & 0x1f) << 23) /* CPO */
628 | ((wr_lat & 0x7) << 19) /* WR_LAT */
629 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
630 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
631 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
632 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
633 );
634
635 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
636 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
637
638 /* Check DIMM data bus width */
639 if (spd.dataw_lsb < 64) {
640 if (spd.mem_type == SPD_MEMTYPE_DDR)
641 burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
642 else
643 burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
644 debug("\n DDR DIMM: data bus width is 32 bit");
645 } else {
646 burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
647 debug("\n DDR DIMM: data bus width is 64 bit");
648 }
649
650 /* Is this an ECC DDR chip? */
651 if (spd.config == 0x02)
652 debug(" with ECC\n");
653 else
654 debug(" without ECC\n");
655
656 /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
657 Burst type is sequential
658 */
659 if (spd.mem_type == SPD_MEMTYPE_DDR) {
660 switch (caslat) {
661 case 1:
662 ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
663 break;
664 case 2:
665 ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
666 break;
667 case 3:
668 ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
669 break;
670 case 4:
671 ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
672 break;
673 default:
674 printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
675 return 0;
676 }
677 } else {
678 mode_odt_enable = 0x0; /* Default disabled */
679 if (odt_wr_cfg || odt_rd_cfg) {
680 /*
681 * Bits 6 and 2 in Extended MRS(1)
682 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
683 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
684 */
685 mode_odt_enable = 0x40; /* 150 Ohm */
686 }
687
688 ddr->sdram_mode =
689 (0
690 | (1 << (16 + 10)) /* DQS Differential disable */
691 #ifdef CONFIG_SYS_DDR_MODE_WEAK
692 | (1 << (16 + 1)) /* weak driver (~60%) */
693 #endif
694 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
695 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
696 | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
697 | (caslat << 4) /* caslat */
698 | (burstlen << 0) /* Burst length */
699 );
700 }
701 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
702
703 /*
704 * Clear EMRS2 and EMRS3.
705 */
706 ddr->sdram_mode2 = 0;
707 debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
708
709 switch (spd.refresh) {
710 case 0x00:
711 case 0x80:
712 refresh_clk = picos_to_clk(15625000);
713 break;
714 case 0x01:
715 case 0x81:
716 refresh_clk = picos_to_clk(3900000);
717 break;
718 case 0x02:
719 case 0x82:
720 refresh_clk = picos_to_clk(7800000);
721 break;
722 case 0x03:
723 case 0x83:
724 refresh_clk = picos_to_clk(31300000);
725 break;
726 case 0x04:
727 case 0x84:
728 refresh_clk = picos_to_clk(62500000);
729 break;
730 case 0x05:
731 case 0x85:
732 refresh_clk = picos_to_clk(125000000);
733 break;
734 default:
735 refresh_clk = 0x512;
736 break;
737 }
738
739 /*
740 * Set BSTOPRE to 0x100 for page mode
741 * If auto-charge is used, set BSTOPRE = 0
742 */
743 ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
744 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
745
746 /*
747 * SDRAM Cfg 2
748 */
749 odt_cfg = 0;
750 #ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
751 if (odt_rd_cfg | odt_wr_cfg) {
752 odt_cfg = 0x2; /* ODT to IOs during reads */
753 }
754 #endif
755 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
756 ddr->sdram_cfg2 = (0
757 | (0 << 26) /* True DQS */
758 | (odt_cfg << 21) /* ODT only read */
759 | (1 << 12) /* 1 refresh at a time */
760 );
761
762 debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
763 }
764
765 #ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
766 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
767 #endif
768 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
769
770 sync();
771 isync();
772
773 udelay(600);
774
775 /*
776 * Figure out the settings for the sdram_cfg register. Build up
777 * the value in 'sdram_cfg' before writing since the write into
778 * the register will actually enable the memory controller, and all
779 * settings must be done before enabling.
780 *
781 * sdram_cfg[0] = 1 (ddr sdram logic enable)
782 * sdram_cfg[1] = 1 (self-refresh-enable)
783 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
784 * 010 DDR 1 SDRAM
785 * 011 DDR 2 SDRAM
786 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
787 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
788 */
789 if (spd.mem_type == SPD_MEMTYPE_DDR)
790 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
791 else
792 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
793
794 sdram_cfg = (0
795 | SDRAM_CFG_MEM_EN /* DDR enable */
796 | SDRAM_CFG_SREN /* Self refresh */
797 | sdram_type /* SDRAM type */
798 );
799
800 /* sdram_cfg[3] = RD_EN - registered DIMM enable */
801 if (spd.mod_attr & 0x02)
802 sdram_cfg |= SDRAM_CFG_RD_EN;
803
804 /* The DIMM is 32bit width */
805 if (spd.dataw_lsb < 64) {
806 if (spd.mem_type == SPD_MEMTYPE_DDR)
807 sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
808 if (spd.mem_type == SPD_MEMTYPE_DDR2)
809 sdram_cfg |= SDRAM_CFG_32_BE;
810 }
811
812 ddrc_ecc_enable = 0;
813
814 #if defined(CONFIG_DDR_ECC)
815 /* Enable ECC with sdram_cfg[2] */
816 if (spd.config == 0x02) {
817 sdram_cfg |= 0x20000000;
818 ddrc_ecc_enable = 1;
819 /* disable error detection */
820 ddr->err_disable = ~ECC_ERROR_ENABLE;
821 /* set single bit error threshold to maximum value,
822 * reset counter to zero */
823 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
824 (0 << ECC_ERROR_MAN_SBEC_SHIFT);
825 }
826
827 debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
828 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
829 #endif
830 debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
831
832 #if defined(CONFIG_DDR_2T_TIMING)
833 /*
834 * Enable 2T timing by setting sdram_cfg[16].
835 */
836 sdram_cfg |= SDRAM_CFG_2T_EN;
837 #endif
838 /* Enable controller, and GO! */
839 ddr->sdram_cfg = sdram_cfg;
840 sync();
841 isync();
842 udelay(500);
843
844 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
845 return memsize; /*in MBytes*/
846 }
847 #endif /* CONFIG_SPD_EEPROM */
848
849 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
mftbu(void)850 static inline u32 mftbu(void)
851 {
852 u32 rval;
853
854 asm volatile("mftbu %0" : "=r" (rval));
855 return rval;
856 }
857
mftb(void)858 static inline u32 mftb(void)
859 {
860 u32 rval;
861
862 asm volatile("mftb %0" : "=r" (rval));
863 return rval;
864 }
865
866 /*
867 * Use timebase counter, get_timer() is not available
868 * at this point of initialization yet.
869 */
get_tbms(void)870 static __inline__ unsigned long get_tbms (void)
871 {
872 unsigned long tbl;
873 unsigned long tbu1, tbu2;
874 unsigned long ms;
875 unsigned long long tmp;
876
877 ulong tbclk = get_tbclk();
878
879 /* get the timebase ticks */
880 do {
881 tbu1 = mftbu();
882 tbl = mftb();
883 tbu2 = mftbu();
884 } while (tbu1 != tbu2);
885
886 /* convert ticks to ms */
887 tmp = (unsigned long long)(tbu1);
888 tmp = (tmp << 32);
889 tmp += (unsigned long long)(tbl);
890 ms = tmp/(tbclk/1000);
891
892 return ms;
893 }
894
895 /*
896 * Initialize all of memory for ECC, then enable errors.
897 */
ddr_enable_ecc(unsigned int dram_size)898 void ddr_enable_ecc(unsigned int dram_size)
899 {
900 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
901 volatile ddr83xx_t *ddr= &immap->ddr;
902 unsigned long t_start, t_end;
903 register u64 *p;
904 register uint size;
905 unsigned int pattern[2];
906
907 icache_enable();
908 t_start = get_tbms();
909 pattern[0] = 0xdeadbeef;
910 pattern[1] = 0xdeadbeef;
911
912 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
913 dma_meminit(pattern[0], dram_size);
914 #else
915 debug("ddr init: CPU FP write method\n");
916 size = dram_size;
917 for (p = 0; p < (u64*)(size); p++) {
918 ppcDWstore((u32*)p, pattern);
919 }
920 sync();
921 #endif
922
923 t_end = get_tbms();
924 icache_disable();
925
926 debug("\nREADY!!\n");
927 debug("ddr init duration: %ld ms\n", t_end - t_start);
928
929 /* Clear All ECC Errors */
930 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
931 ddr->err_detect |= ECC_ERROR_DETECT_MME;
932 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
933 ddr->err_detect |= ECC_ERROR_DETECT_MBE;
934 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
935 ddr->err_detect |= ECC_ERROR_DETECT_SBE;
936 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
937 ddr->err_detect |= ECC_ERROR_DETECT_MSE;
938
939 /* Disable ECC-Interrupts */
940 ddr->err_int_en &= ECC_ERR_INT_DISABLE;
941
942 /* Enable errors for ECC */
943 ddr->err_disable &= ECC_ERROR_ENABLE;
944
945 sync();
946 isync();
947 }
948 #endif /* CONFIG_DDR_ECC */
949
950 #endif /* !CONFIG_MPC83XX_SDRAM */
951