1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 2 // All Rights Reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are 6 // met: 7 // 8 // - Redistributions of source code must retain the above copyright notice, 9 // this list of conditions and the following disclaimer. 10 // 11 // - Redistribution in binary form must reproduce the above copyright 12 // notice, this list of conditions and the following disclaimer in the 13 // documentation and/or other materials provided with the distribution. 14 // 15 // - Neither the name of Sun Microsystems or the names of contributors may 16 // be used to endorse or promote products derived from this software without 17 // specific prior written permission. 18 // 19 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 20 // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 23 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 26 // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 27 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 31 // The original source code covered by the above license above has been 32 // modified significantly by Google Inc. 33 // Copyright 2012 the V8 project authors. All rights reserved. 34 35 #ifndef V8_CODEGEN_MIPS_ASSEMBLER_MIPS_H_ 36 #define V8_CODEGEN_MIPS_ASSEMBLER_MIPS_H_ 37 38 #include <stdio.h> 39 #include <memory> 40 41 #include <set> 42 43 #include "src/codegen/assembler.h" 44 #include "src/codegen/external-reference.h" 45 #include "src/codegen/label.h" 46 #include "src/codegen/mips/constants-mips.h" 47 #include "src/codegen/mips/register-mips.h" 48 #include "src/objects/smi.h" 49 50 namespace v8 { 51 namespace internal { 52 53 class SafepointTableBuilder; 54 55 // Allow programmer to use Branch Delay Slot of Branches, Jumps, Calls. 56 enum BranchDelaySlot { USE_DELAY_SLOT, PROTECT }; 57 58 // ----------------------------------------------------------------------------- 59 // Machine instruction Operands. 60 61 // Class Operand represents a shifter operand in data processing instructions. 62 class Operand { 63 public: 64 // Immediate. 65 V8_INLINE explicit Operand(int32_t immediate, 66 RelocInfo::Mode rmode = RelocInfo::NONE) rm_(no_reg)67 : rm_(no_reg), rmode_(rmode) { 68 value_.immediate = immediate; 69 } Operand(const ExternalReference & f)70 V8_INLINE explicit Operand(const ExternalReference& f) 71 : rm_(no_reg), rmode_(RelocInfo::EXTERNAL_REFERENCE) { 72 value_.immediate = static_cast<int32_t>(f.address()); 73 } 74 V8_INLINE explicit Operand(const char* s); 75 explicit Operand(Handle<HeapObject> handle); Operand(Smi value)76 V8_INLINE explicit Operand(Smi value) : rm_(no_reg), rmode_(RelocInfo::NONE) { 77 value_.immediate = static_cast<intptr_t>(value.ptr()); 78 } 79 80 static Operand EmbeddedNumber(double number); // Smi or HeapNumber. 81 static Operand EmbeddedStringConstant(const StringConstantBase* str); 82 83 // Register. Operand(Register rm)84 V8_INLINE explicit Operand(Register rm) : rm_(rm) {} 85 86 // Return true if this is a register operand. 87 V8_INLINE bool is_reg() const; 88 89 inline int32_t immediate() const; 90 IsImmediate()91 bool IsImmediate() const { return !rm_.is_valid(); } 92 heap_object_request()93 HeapObjectRequest heap_object_request() const { 94 DCHECK(IsHeapObjectRequest()); 95 return value_.heap_object_request; 96 } 97 IsHeapObjectRequest()98 bool IsHeapObjectRequest() const { 99 DCHECK_IMPLIES(is_heap_object_request_, IsImmediate()); 100 DCHECK_IMPLIES(is_heap_object_request_, 101 rmode_ == RelocInfo::FULL_EMBEDDED_OBJECT || 102 rmode_ == RelocInfo::CODE_TARGET); 103 return is_heap_object_request_; 104 } 105 rm()106 Register rm() const { return rm_; } 107 rmode()108 RelocInfo::Mode rmode() const { return rmode_; } 109 110 private: 111 Register rm_; 112 union Value { Value()113 Value() {} 114 HeapObjectRequest heap_object_request; // if is_heap_object_request_ 115 int32_t immediate; // otherwise 116 } value_; // valid if rm_ == no_reg 117 bool is_heap_object_request_ = false; 118 RelocInfo::Mode rmode_; 119 120 friend class Assembler; 121 // friend class MacroAssembler; 122 }; 123 124 // On MIPS we have only one addressing mode with base_reg + offset. 125 // Class MemOperand represents a memory operand in load and store instructions. 126 class V8_EXPORT_PRIVATE MemOperand : public Operand { 127 public: 128 // Immediate value attached to offset. 129 enum OffsetAddend { offset_minus_one = -1, offset_zero = 0 }; 130 131 explicit MemOperand(Register rn, int32_t offset = 0); 132 explicit MemOperand(Register rn, int32_t unit, int32_t multiplier, 133 OffsetAddend offset_addend = offset_zero); offset()134 int32_t offset() const { return offset_; } 135 OffsetIsInt16Encodable()136 bool OffsetIsInt16Encodable() const { return is_int16(offset_); } 137 138 private: 139 int32_t offset_; 140 141 friend class Assembler; 142 }; 143 144 class V8_EXPORT_PRIVATE Assembler : public AssemblerBase { 145 public: 146 // Create an assembler. Instructions and relocation information are emitted 147 // into a buffer, with the instructions starting from the beginning and the 148 // relocation information starting from the end of the buffer. See CodeDesc 149 // for a detailed comment on the layout (globals.h). 150 // 151 // If the provided buffer is nullptr, the assembler allocates and grows its 152 // own buffer. Otherwise it takes ownership of the provided buffer. 153 explicit Assembler(const AssemblerOptions&, 154 std::unique_ptr<AssemblerBuffer> = {}); 155 ~Assembler()156 virtual ~Assembler() {} 157 158 // GetCode emits any pending (non-emitted) code and fills the descriptor desc. 159 static constexpr int kNoHandlerTable = 0; 160 static constexpr SafepointTableBuilder* kNoSafepointTable = nullptr; 161 void GetCode(Isolate* isolate, CodeDesc* desc, 162 SafepointTableBuilder* safepoint_table_builder, 163 int handler_table_offset); 164 165 // Convenience wrapper for code without safepoint or handler tables. GetCode(Isolate * isolate,CodeDesc * desc)166 void GetCode(Isolate* isolate, CodeDesc* desc) { 167 GetCode(isolate, desc, kNoSafepointTable, kNoHandlerTable); 168 } 169 170 // Unused on this architecture. MaybeEmitOutOfLineConstantPool()171 void MaybeEmitOutOfLineConstantPool() {} 172 173 // Mips uses BlockTrampolinePool to prevent generating trampoline inside a 174 // continuous instruction block. For Call instrution, it prevents generating 175 // trampoline between jalr and delay slot instruction. In the destructor of 176 // BlockTrampolinePool, it must check if it needs to generate trampoline 177 // immediately, if it does not do this, the branch range will go beyond the 178 // max branch offset, that means the pc_offset after call CheckTrampolinePool 179 // may be not the Call instruction's location. So we use last_call_pc here for 180 // safepoint record. pc_offset_for_safepoint()181 int pc_offset_for_safepoint() { 182 #ifdef DEBUG 183 Instr instr1 = 184 instr_at(static_cast<int>(last_call_pc_ - buffer_start_ - kInstrSize)); 185 Instr instr2 = instr_at( 186 static_cast<int>(last_call_pc_ - buffer_start_ - kInstrSize * 2)); 187 if (GetOpcodeField(instr1) != SPECIAL) { // instr1 == jialc. 188 DCHECK(IsMipsArchVariant(kMips32r6) && GetOpcodeField(instr1) == POP76 && 189 GetRs(instr1) == 0); 190 } else { 191 if (GetFunctionField(instr1) == SLL) { // instr1 == nop, instr2 == jalr. 192 DCHECK(GetOpcodeField(instr2) == SPECIAL && 193 GetFunctionField(instr2) == JALR); 194 } else { // instr1 == jalr. 195 DCHECK(GetFunctionField(instr1) == JALR); 196 } 197 } 198 #endif 199 return static_cast<int>(last_call_pc_ - buffer_start_); 200 } 201 202 // Label operations & relative jumps (PPUM Appendix D). 203 // 204 // Takes a branch opcode (cc) and a label (L) and generates 205 // either a backward branch or a forward branch and links it 206 // to the label fixup chain. Usage: 207 // 208 // Label L; // unbound label 209 // j(cc, &L); // forward branch to unbound label 210 // bind(&L); // bind label to the current pc 211 // j(cc, &L); // backward branch to bound label 212 // bind(&L); // illegal: a label may be bound only once 213 // 214 // Note: The same Label can be used for forward and backward branches 215 // but it may be bound only once. 216 void bind(Label* L); // Binds an unbound label L to current code position. 217 218 enum OffsetSize : int { kOffset26 = 26, kOffset21 = 21, kOffset16 = 16 }; 219 220 // Determines if Label is bound and near enough so that branch instruction 221 // can be used to reach it, instead of jump instruction. 222 bool is_near(Label* L); 223 bool is_near(Label* L, OffsetSize bits); 224 bool is_near_branch(Label* L); is_near_pre_r6(Label * L)225 inline bool is_near_pre_r6(Label* L) { 226 DCHECK(!IsMipsArchVariant(kMips32r6)); 227 return pc_offset() - L->pos() < kMaxBranchOffset - 4 * kInstrSize; 228 } is_near_r6(Label * L)229 inline bool is_near_r6(Label* L) { 230 DCHECK(IsMipsArchVariant(kMips32r6)); 231 return pc_offset() - L->pos() < kMaxCompactBranchOffset - 4 * kInstrSize; 232 } 233 234 int BranchOffset(Instr instr); 235 236 // Returns the branch offset to the given label from the current code 237 // position. Links the label to the current position if it is still unbound. 238 // Manages the jump elimination optimization if the second parameter is true. 239 int32_t branch_offset_helper(Label* L, OffsetSize bits); branch_offset(Label * L)240 inline int32_t branch_offset(Label* L) { 241 return branch_offset_helper(L, OffsetSize::kOffset16); 242 } branch_offset21(Label * L)243 inline int32_t branch_offset21(Label* L) { 244 return branch_offset_helper(L, OffsetSize::kOffset21); 245 } branch_offset26(Label * L)246 inline int32_t branch_offset26(Label* L) { 247 return branch_offset_helper(L, OffsetSize::kOffset26); 248 } shifted_branch_offset(Label * L)249 inline int32_t shifted_branch_offset(Label* L) { 250 return branch_offset(L) >> 2; 251 } shifted_branch_offset21(Label * L)252 inline int32_t shifted_branch_offset21(Label* L) { 253 return branch_offset21(L) >> 2; 254 } shifted_branch_offset26(Label * L)255 inline int32_t shifted_branch_offset26(Label* L) { 256 return branch_offset26(L) >> 2; 257 } 258 uint32_t jump_address(Label* L); 259 uint32_t branch_long_offset(Label* L); 260 261 // Puts a labels target address at the given position. 262 // The high 8 bits are set to zero. 263 void label_at_put(Label* L, int at_offset); 264 265 // Read/Modify the code target address in the branch/call instruction at pc. 266 // The isolate argument is unused (and may be nullptr) when skipping flushing. 267 static Address target_address_at(Address pc); 268 V8_INLINE static void set_target_address_at( 269 Address pc, Address target, 270 ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED) { 271 set_target_value_at(pc, static_cast<uint32_t>(target), icache_flush_mode); 272 } 273 // On MIPS there is no Constant Pool so we skip that parameter. target_address_at(Address pc,Address constant_pool)274 V8_INLINE static Address target_address_at(Address pc, 275 Address constant_pool) { 276 return target_address_at(pc); 277 } 278 V8_INLINE static void set_target_address_at( 279 Address pc, Address constant_pool, Address target, 280 ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED) { 281 set_target_address_at(pc, target, icache_flush_mode); 282 } 283 284 static void set_target_value_at( 285 Address pc, uint32_t target, 286 ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED); 287 288 // This sets the branch destination (which gets loaded at the call address). 289 // This is for calls and branches within generated code. The serializer 290 // has already deserialized the lui/ori instructions etc. 291 inline static void deserialization_set_special_target_at( 292 Address instruction_payload, Code code, Address target); 293 294 // Get the size of the special target encoded at 'instruction_payload'. 295 inline static int deserialization_special_target_size( 296 Address instruction_payload); 297 298 // This sets the internal reference at the pc. 299 inline static void deserialization_set_target_internal_reference_at( 300 Address pc, Address target, 301 RelocInfo::Mode mode = RelocInfo::INTERNAL_REFERENCE); 302 303 // Difference between address of current opcode and target address offset. 304 static constexpr int kBranchPCOffset = kInstrSize; 305 306 // Difference between address of current opcode and target address offset, 307 // when we are generatinga sequence of instructions for long relative PC 308 // branches. It is distance between address of the first instruction in 309 // the jump sequence, and the value that ra gets after calling nal(). 310 static constexpr int kLongBranchPCOffset = 3 * kInstrSize; 311 312 // Adjust ra register in branch delay slot of bal instruction in order to skip 313 // instructions not needed after optimization of PIC in 314 // TurboAssembler::BranchAndLink method. 315 static constexpr int kOptimizedBranchAndLinkLongReturnOffset = 3 * kInstrSize; 316 317 // Offset of target relative address in calls/jumps for builtins. It is 318 // distance between instruction that is placed just after calling 319 // RecordRelocInfo, and the value that ra gets aftr calling nal(). 320 static constexpr int kRelativeJumpForBuiltinsOffset = 1 * kInstrSize; 321 // Relative target address of jumps for builtins when we use lui, ori, dsll, 322 // ori sequence when loading address that cannot fit into 32 bits. 323 static constexpr int kRelativeCallForBuiltinsOffset = 3 * kInstrSize; 324 325 // Here we are patching the address in the LUI/ORI instruction pair. 326 // These values are used in the serialization process and must be zero for 327 // MIPS platform, as Code, Embedded Object or External-reference pointers 328 // are split across two consecutive instructions and don't exist separately 329 // in the code, so the serializer should not step forwards in memory after 330 // a target is resolved and written. 331 332 static constexpr int kSpecialTargetSize = 0; 333 334 // Number of consecutive instructions used to store 32bit constant. This 335 // constant is used in RelocInfo::target_address_address() function to tell 336 // serializer address of the instruction that follows LUI/ORI instruction 337 // pair. 338 static constexpr int kInstructionsFor32BitConstant = 2; 339 340 // Max offset for instructions with 16-bit offset field 341 static constexpr int kMaxBranchOffset = (1 << (18 - 1)) - 1; 342 343 // Max offset for compact branch instructions with 26-bit offset field 344 static constexpr int kMaxCompactBranchOffset = (1 << (28 - 1)) - 1; 345 346 static constexpr int kTrampolineSlotsSize = 347 IsMipsArchVariant(kMips32r6) ? 2 * kInstrSize : 7 * kInstrSize; 348 GetScratchRegisterList()349 RegList* GetScratchRegisterList() { return &scratch_register_list_; } 350 351 // --------------------------------------------------------------------------- 352 // Code generation. 353 354 // Insert the smallest number of nop instructions 355 // possible to align the pc offset to a multiple 356 // of m. m must be a power of 2 (>= 4). 357 void Align(int m); 358 // Insert the smallest number of zero bytes possible to align the pc offset 359 // to a mulitple of m. m must be a power of 2 (>= 2). 360 void DataAlign(int m); 361 // Aligns code to something that's optimal for a jump target for the platform. 362 void CodeTargetAlign(); 363 364 // Different nop operations are used by the code generator to detect certain 365 // states of the generated code. 366 enum NopMarkerTypes { 367 NON_MARKING_NOP = 0, 368 DEBUG_BREAK_NOP, 369 // IC markers. 370 PROPERTY_ACCESS_INLINED, 371 PROPERTY_ACCESS_INLINED_CONTEXT, 372 PROPERTY_ACCESS_INLINED_CONTEXT_DONT_DELETE, 373 // Helper values. 374 LAST_CODE_MARKER, 375 FIRST_IC_MARKER = PROPERTY_ACCESS_INLINED, 376 }; 377 378 // Type == 0 is the default non-marking nop. For mips this is a 379 // sll(zero_reg, zero_reg, 0). We use rt_reg == at for non-zero 380 // marking, to avoid conflict with ssnop and ehb instructions. 381 void nop(unsigned int type = 0) { 382 DCHECK_LT(type, 32); 383 Register nop_rt_reg = (type == 0) ? zero_reg : at; 384 sll(zero_reg, nop_rt_reg, type, true); 385 } 386 387 // --------Branch-and-jump-instructions---------- 388 // We don't use likely variant of instructions. 389 void b(int16_t offset); b(Label * L)390 inline void b(Label* L) { b(shifted_branch_offset(L)); } 391 void bal(int16_t offset); bal(Label * L)392 inline void bal(Label* L) { bal(shifted_branch_offset(L)); } 393 void bc(int32_t offset); bc(Label * L)394 inline void bc(Label* L) { bc(shifted_branch_offset26(L)); } 395 void balc(int32_t offset); balc(Label * L)396 inline void balc(Label* L) { balc(shifted_branch_offset26(L)); } 397 398 void beq(Register rs, Register rt, int16_t offset); beq(Register rs,Register rt,Label * L)399 inline void beq(Register rs, Register rt, Label* L) { 400 beq(rs, rt, shifted_branch_offset(L)); 401 } 402 void bgez(Register rs, int16_t offset); 403 void bgezc(Register rt, int16_t offset); bgezc(Register rt,Label * L)404 inline void bgezc(Register rt, Label* L) { 405 bgezc(rt, shifted_branch_offset(L)); 406 } 407 void bgeuc(Register rs, Register rt, int16_t offset); bgeuc(Register rs,Register rt,Label * L)408 inline void bgeuc(Register rs, Register rt, Label* L) { 409 bgeuc(rs, rt, shifted_branch_offset(L)); 410 } 411 void bgec(Register rs, Register rt, int16_t offset); bgec(Register rs,Register rt,Label * L)412 inline void bgec(Register rs, Register rt, Label* L) { 413 bgec(rs, rt, shifted_branch_offset(L)); 414 } 415 void bgezal(Register rs, int16_t offset); 416 void bgezalc(Register rt, int16_t offset); bgezalc(Register rt,Label * L)417 inline void bgezalc(Register rt, Label* L) { 418 bgezalc(rt, shifted_branch_offset(L)); 419 } 420 void bgezall(Register rs, int16_t offset); bgezall(Register rs,Label * L)421 inline void bgezall(Register rs, Label* L) { 422 bgezall(rs, branch_offset(L) >> 2); 423 } 424 void bgtz(Register rs, int16_t offset); 425 void bgtzc(Register rt, int16_t offset); bgtzc(Register rt,Label * L)426 inline void bgtzc(Register rt, Label* L) { 427 bgtzc(rt, shifted_branch_offset(L)); 428 } 429 void blez(Register rs, int16_t offset); 430 void blezc(Register rt, int16_t offset); blezc(Register rt,Label * L)431 inline void blezc(Register rt, Label* L) { 432 blezc(rt, shifted_branch_offset(L)); 433 } 434 void bltz(Register rs, int16_t offset); 435 void bltzc(Register rt, int16_t offset); bltzc(Register rt,Label * L)436 inline void bltzc(Register rt, Label* L) { 437 bltzc(rt, shifted_branch_offset(L)); 438 } 439 void bltuc(Register rs, Register rt, int16_t offset); bltuc(Register rs,Register rt,Label * L)440 inline void bltuc(Register rs, Register rt, Label* L) { 441 bltuc(rs, rt, shifted_branch_offset(L)); 442 } 443 void bltc(Register rs, Register rt, int16_t offset); bltc(Register rs,Register rt,Label * L)444 inline void bltc(Register rs, Register rt, Label* L) { 445 bltc(rs, rt, shifted_branch_offset(L)); 446 } 447 void bltzal(Register rs, int16_t offset); nal()448 void nal() { bltzal(zero_reg, 0); } 449 void blezalc(Register rt, int16_t offset); blezalc(Register rt,Label * L)450 inline void blezalc(Register rt, Label* L) { 451 blezalc(rt, shifted_branch_offset(L)); 452 } 453 void bltzalc(Register rt, int16_t offset); bltzalc(Register rt,Label * L)454 inline void bltzalc(Register rt, Label* L) { 455 bltzalc(rt, shifted_branch_offset(L)); 456 } 457 void bgtzalc(Register rt, int16_t offset); bgtzalc(Register rt,Label * L)458 inline void bgtzalc(Register rt, Label* L) { 459 bgtzalc(rt, shifted_branch_offset(L)); 460 } 461 void beqzalc(Register rt, int16_t offset); beqzalc(Register rt,Label * L)462 inline void beqzalc(Register rt, Label* L) { 463 beqzalc(rt, shifted_branch_offset(L)); 464 } 465 void beqc(Register rs, Register rt, int16_t offset); beqc(Register rs,Register rt,Label * L)466 inline void beqc(Register rs, Register rt, Label* L) { 467 beqc(rs, rt, shifted_branch_offset(L)); 468 } 469 void beqzc(Register rs, int32_t offset); beqzc(Register rs,Label * L)470 inline void beqzc(Register rs, Label* L) { 471 beqzc(rs, shifted_branch_offset21(L)); 472 } 473 void bnezalc(Register rt, int16_t offset); bnezalc(Register rt,Label * L)474 inline void bnezalc(Register rt, Label* L) { 475 bnezalc(rt, shifted_branch_offset(L)); 476 } 477 void bnec(Register rs, Register rt, int16_t offset); bnec(Register rs,Register rt,Label * L)478 inline void bnec(Register rs, Register rt, Label* L) { 479 bnec(rs, rt, shifted_branch_offset(L)); 480 } 481 void bnezc(Register rt, int32_t offset); bnezc(Register rt,Label * L)482 inline void bnezc(Register rt, Label* L) { 483 bnezc(rt, shifted_branch_offset21(L)); 484 } 485 void bne(Register rs, Register rt, int16_t offset); bne(Register rs,Register rt,Label * L)486 inline void bne(Register rs, Register rt, Label* L) { 487 bne(rs, rt, shifted_branch_offset(L)); 488 } 489 void bovc(Register rs, Register rt, int16_t offset); bovc(Register rs,Register rt,Label * L)490 inline void bovc(Register rs, Register rt, Label* L) { 491 bovc(rs, rt, shifted_branch_offset(L)); 492 } 493 void bnvc(Register rs, Register rt, int16_t offset); bnvc(Register rs,Register rt,Label * L)494 inline void bnvc(Register rs, Register rt, Label* L) { 495 bnvc(rs, rt, shifted_branch_offset(L)); 496 } 497 498 // Never use the int16_t b(l)cond version with a branch offset 499 // instead of using the Label* version. 500 501 // Jump targets must be in the current 256 MB-aligned region. i.e. 28 bits. 502 void j(int32_t target); 503 void jal(int32_t target); 504 void jalr(Register rs, Register rd = ra); 505 void jr(Register target); 506 void jic(Register rt, int16_t offset); 507 void jialc(Register rt, int16_t offset); 508 509 // -------Data-processing-instructions--------- 510 511 // Arithmetic. 512 void addu(Register rd, Register rs, Register rt); 513 void subu(Register rd, Register rs, Register rt); 514 void mult(Register rs, Register rt); 515 void multu(Register rs, Register rt); 516 void div(Register rs, Register rt); 517 void divu(Register rs, Register rt); 518 void div(Register rd, Register rs, Register rt); 519 void divu(Register rd, Register rs, Register rt); 520 void mod(Register rd, Register rs, Register rt); 521 void modu(Register rd, Register rs, Register rt); 522 void mul(Register rd, Register rs, Register rt); 523 void muh(Register rd, Register rs, Register rt); 524 void mulu(Register rd, Register rs, Register rt); 525 void muhu(Register rd, Register rs, Register rt); 526 527 void addiu(Register rd, Register rs, int32_t j); 528 529 // Logical. 530 void and_(Register rd, Register rs, Register rt); 531 void or_(Register rd, Register rs, Register rt); 532 void xor_(Register rd, Register rs, Register rt); 533 void nor(Register rd, Register rs, Register rt); 534 535 void andi(Register rd, Register rs, int32_t j); 536 void ori(Register rd, Register rs, int32_t j); 537 void xori(Register rd, Register rs, int32_t j); 538 void lui(Register rd, int32_t j); 539 void aui(Register rs, Register rt, int32_t j); 540 541 // Shifts. 542 // Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop 543 // and may cause problems in normal code. coming_from_nop makes sure this 544 // doesn't happen. 545 void sll(Register rd, Register rt, uint16_t sa, bool coming_from_nop = false); 546 void sllv(Register rd, Register rt, Register rs); 547 void srl(Register rd, Register rt, uint16_t sa); 548 void srlv(Register rd, Register rt, Register rs); 549 void sra(Register rt, Register rd, uint16_t sa); 550 void srav(Register rt, Register rd, Register rs); 551 void rotr(Register rd, Register rt, uint16_t sa); 552 void rotrv(Register rd, Register rt, Register rs); 553 554 // ------------Memory-instructions------------- 555 556 void lb(Register rd, const MemOperand& rs); 557 void lbu(Register rd, const MemOperand& rs); 558 void lh(Register rd, const MemOperand& rs); 559 void lhu(Register rd, const MemOperand& rs); 560 void lw(Register rd, const MemOperand& rs); 561 void lwl(Register rd, const MemOperand& rs); 562 void lwr(Register rd, const MemOperand& rs); 563 void sb(Register rd, const MemOperand& rs); 564 void sh(Register rd, const MemOperand& rs); 565 void sw(Register rd, const MemOperand& rs); 566 void swl(Register rd, const MemOperand& rs); 567 void swr(Register rd, const MemOperand& rs); 568 569 // ----------Atomic instructions-------------- 570 571 void ll(Register rd, const MemOperand& rs); 572 void sc(Register rd, const MemOperand& rs); 573 void llx(Register rd, const MemOperand& rs); 574 void scx(Register rd, const MemOperand& rs); 575 576 // ---------PC-Relative-instructions----------- 577 578 void addiupc(Register rs, int32_t imm19); 579 void lwpc(Register rs, int32_t offset19); 580 void auipc(Register rs, int16_t imm16); 581 void aluipc(Register rs, int16_t imm16); 582 583 // ----------------Prefetch-------------------- 584 585 void pref(int32_t hint, const MemOperand& rs); 586 587 // -------------Misc-instructions-------------- 588 589 // Break / Trap instructions. 590 void break_(uint32_t code, bool break_as_stop = false); 591 void stop(uint32_t code = kMaxStopCode); 592 void tge(Register rs, Register rt, uint16_t code); 593 void tgeu(Register rs, Register rt, uint16_t code); 594 void tlt(Register rs, Register rt, uint16_t code); 595 void tltu(Register rs, Register rt, uint16_t code); 596 void teq(Register rs, Register rt, uint16_t code); 597 void tne(Register rs, Register rt, uint16_t code); 598 599 // Memory barrier instruction. 600 void sync(); 601 602 // Move from HI/LO register. 603 void mfhi(Register rd); 604 void mflo(Register rd); 605 606 // Set on less than. 607 void slt(Register rd, Register rs, Register rt); 608 void sltu(Register rd, Register rs, Register rt); 609 void slti(Register rd, Register rs, int32_t j); 610 void sltiu(Register rd, Register rs, int32_t j); 611 612 // Conditional move. 613 void movz(Register rd, Register rs, Register rt); 614 void movn(Register rd, Register rs, Register rt); 615 void movt(Register rd, Register rs, uint16_t cc = 0); 616 void movf(Register rd, Register rs, uint16_t cc = 0); 617 618 void sel(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 619 void sel_s(FPURegister fd, FPURegister fs, FPURegister ft); 620 void sel_d(FPURegister fd, FPURegister fs, FPURegister ft); 621 void seleqz(Register rd, Register rs, Register rt); 622 void seleqz(SecondaryField fmt, FPURegister fd, FPURegister fs, 623 FPURegister ft); 624 void selnez(Register rd, Register rs, Register rt); 625 void selnez(SecondaryField fmt, FPURegister fd, FPURegister fs, 626 FPURegister ft); 627 void seleqz_d(FPURegister fd, FPURegister fs, FPURegister ft); 628 void seleqz_s(FPURegister fd, FPURegister fs, FPURegister ft); 629 void selnez_d(FPURegister fd, FPURegister fs, FPURegister ft); 630 void selnez_s(FPURegister fd, FPURegister fs, FPURegister ft); 631 632 void movz_s(FPURegister fd, FPURegister fs, Register rt); 633 void movz_d(FPURegister fd, FPURegister fs, Register rt); 634 void movt_s(FPURegister fd, FPURegister fs, uint16_t cc = 0); 635 void movt_d(FPURegister fd, FPURegister fs, uint16_t cc = 0); 636 void movf_s(FPURegister fd, FPURegister fs, uint16_t cc = 0); 637 void movf_d(FPURegister fd, FPURegister fs, uint16_t cc = 0); 638 void movn_s(FPURegister fd, FPURegister fs, Register rt); 639 void movn_d(FPURegister fd, FPURegister fs, Register rt); 640 // Bit twiddling. 641 void clz(Register rd, Register rs); 642 void ins_(Register rt, Register rs, uint16_t pos, uint16_t size); 643 void ext_(Register rt, Register rs, uint16_t pos, uint16_t size); 644 void bitswap(Register rd, Register rt); 645 void align(Register rd, Register rs, Register rt, uint8_t bp); 646 647 void wsbh(Register rd, Register rt); 648 void seh(Register rd, Register rt); 649 void seb(Register rd, Register rt); 650 651 // --------Coprocessor-instructions---------------- 652 653 // Load, store, and move. 654 void lwc1(FPURegister fd, const MemOperand& src); 655 void swc1(FPURegister fs, const MemOperand& dst); 656 657 void mtc1(Register rt, FPURegister fs); 658 void mthc1(Register rt, FPURegister fs); 659 660 void mfc1(Register rt, FPURegister fs); 661 void mfhc1(Register rt, FPURegister fs); 662 663 void ctc1(Register rt, FPUControlRegister fs); 664 void cfc1(Register rt, FPUControlRegister fs); 665 666 // Arithmetic. 667 void add_s(FPURegister fd, FPURegister fs, FPURegister ft); 668 void add_d(FPURegister fd, FPURegister fs, FPURegister ft); 669 void sub_s(FPURegister fd, FPURegister fs, FPURegister ft); 670 void sub_d(FPURegister fd, FPURegister fs, FPURegister ft); 671 void mul_s(FPURegister fd, FPURegister fs, FPURegister ft); 672 void mul_d(FPURegister fd, FPURegister fs, FPURegister ft); 673 void madd_s(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 674 void madd_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 675 void msub_s(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 676 void msub_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 677 void maddf_s(FPURegister fd, FPURegister fs, FPURegister ft); 678 void maddf_d(FPURegister fd, FPURegister fs, FPURegister ft); 679 void msubf_s(FPURegister fd, FPURegister fs, FPURegister ft); 680 void msubf_d(FPURegister fd, FPURegister fs, FPURegister ft); 681 void div_s(FPURegister fd, FPURegister fs, FPURegister ft); 682 void div_d(FPURegister fd, FPURegister fs, FPURegister ft); 683 void abs_s(FPURegister fd, FPURegister fs); 684 void abs_d(FPURegister fd, FPURegister fs); 685 void mov_d(FPURegister fd, FPURegister fs); 686 void mov_s(FPURegister fd, FPURegister fs); 687 void neg_s(FPURegister fd, FPURegister fs); 688 void neg_d(FPURegister fd, FPURegister fs); 689 void sqrt_s(FPURegister fd, FPURegister fs); 690 void sqrt_d(FPURegister fd, FPURegister fs); 691 void rsqrt_s(FPURegister fd, FPURegister fs); 692 void rsqrt_d(FPURegister fd, FPURegister fs); 693 void recip_d(FPURegister fd, FPURegister fs); 694 void recip_s(FPURegister fd, FPURegister fs); 695 696 // Conversion. 697 void cvt_w_s(FPURegister fd, FPURegister fs); 698 void cvt_w_d(FPURegister fd, FPURegister fs); 699 void trunc_w_s(FPURegister fd, FPURegister fs); 700 void trunc_w_d(FPURegister fd, FPURegister fs); 701 void round_w_s(FPURegister fd, FPURegister fs); 702 void round_w_d(FPURegister fd, FPURegister fs); 703 void floor_w_s(FPURegister fd, FPURegister fs); 704 void floor_w_d(FPURegister fd, FPURegister fs); 705 void ceil_w_s(FPURegister fd, FPURegister fs); 706 void ceil_w_d(FPURegister fd, FPURegister fs); 707 void rint_s(FPURegister fd, FPURegister fs); 708 void rint_d(FPURegister fd, FPURegister fs); 709 void rint(SecondaryField fmt, FPURegister fd, FPURegister fs); 710 711 void cvt_l_s(FPURegister fd, FPURegister fs); 712 void cvt_l_d(FPURegister fd, FPURegister fs); 713 void trunc_l_s(FPURegister fd, FPURegister fs); 714 void trunc_l_d(FPURegister fd, FPURegister fs); 715 void round_l_s(FPURegister fd, FPURegister fs); 716 void round_l_d(FPURegister fd, FPURegister fs); 717 void floor_l_s(FPURegister fd, FPURegister fs); 718 void floor_l_d(FPURegister fd, FPURegister fs); 719 void ceil_l_s(FPURegister fd, FPURegister fs); 720 void ceil_l_d(FPURegister fd, FPURegister fs); 721 722 void class_s(FPURegister fd, FPURegister fs); 723 void class_d(FPURegister fd, FPURegister fs); 724 725 void min(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 726 void mina(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 727 void max(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 728 void maxa(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 729 void min_s(FPURegister fd, FPURegister fs, FPURegister ft); 730 void min_d(FPURegister fd, FPURegister fs, FPURegister ft); 731 void max_s(FPURegister fd, FPURegister fs, FPURegister ft); 732 void max_d(FPURegister fd, FPURegister fs, FPURegister ft); 733 void mina_s(FPURegister fd, FPURegister fs, FPURegister ft); 734 void mina_d(FPURegister fd, FPURegister fs, FPURegister ft); 735 void maxa_s(FPURegister fd, FPURegister fs, FPURegister ft); 736 void maxa_d(FPURegister fd, FPURegister fs, FPURegister ft); 737 738 void cvt_s_w(FPURegister fd, FPURegister fs); 739 void cvt_s_l(FPURegister fd, FPURegister fs); 740 void cvt_s_d(FPURegister fd, FPURegister fs); 741 742 void cvt_d_w(FPURegister fd, FPURegister fs); 743 void cvt_d_l(FPURegister fd, FPURegister fs); 744 void cvt_d_s(FPURegister fd, FPURegister fs); 745 746 // Conditions and branches for MIPSr6. 747 void cmp(FPUCondition cond, SecondaryField fmt, FPURegister fd, 748 FPURegister ft, FPURegister fs); 749 void cmp_s(FPUCondition cond, FPURegister fd, FPURegister fs, FPURegister ft); 750 void cmp_d(FPUCondition cond, FPURegister fd, FPURegister fs, FPURegister ft); 751 752 void bc1eqz(int16_t offset, FPURegister ft); bc1eqz(Label * L,FPURegister ft)753 inline void bc1eqz(Label* L, FPURegister ft) { 754 bc1eqz(shifted_branch_offset(L), ft); 755 } 756 void bc1nez(int16_t offset, FPURegister ft); bc1nez(Label * L,FPURegister ft)757 inline void bc1nez(Label* L, FPURegister ft) { 758 bc1nez(shifted_branch_offset(L), ft); 759 } 760 761 // Conditions and branches for non MIPSr6. 762 void c(FPUCondition cond, SecondaryField fmt, FPURegister ft, FPURegister fs, 763 uint16_t cc = 0); 764 void c_s(FPUCondition cond, FPURegister ft, FPURegister fs, uint16_t cc = 0); 765 void c_d(FPUCondition cond, FPURegister ft, FPURegister fs, uint16_t cc = 0); 766 767 void bc1f(int16_t offset, uint16_t cc = 0); 768 inline void bc1f(Label* L, uint16_t cc = 0) { 769 bc1f(shifted_branch_offset(L), cc); 770 } 771 void bc1t(int16_t offset, uint16_t cc = 0); 772 inline void bc1t(Label* L, uint16_t cc = 0) { 773 bc1t(shifted_branch_offset(L), cc); 774 } 775 void fcmp(FPURegister src1, const double src2, FPUCondition cond); 776 777 // MSA instructions 778 void bz_v(MSARegister wt, int16_t offset); bz_v(MSARegister wt,Label * L)779 inline void bz_v(MSARegister wt, Label* L) { 780 bz_v(wt, shifted_branch_offset(L)); 781 } 782 void bz_b(MSARegister wt, int16_t offset); bz_b(MSARegister wt,Label * L)783 inline void bz_b(MSARegister wt, Label* L) { 784 bz_b(wt, shifted_branch_offset(L)); 785 } 786 void bz_h(MSARegister wt, int16_t offset); bz_h(MSARegister wt,Label * L)787 inline void bz_h(MSARegister wt, Label* L) { 788 bz_h(wt, shifted_branch_offset(L)); 789 } 790 void bz_w(MSARegister wt, int16_t offset); bz_w(MSARegister wt,Label * L)791 inline void bz_w(MSARegister wt, Label* L) { 792 bz_w(wt, shifted_branch_offset(L)); 793 } 794 void bz_d(MSARegister wt, int16_t offset); bz_d(MSARegister wt,Label * L)795 inline void bz_d(MSARegister wt, Label* L) { 796 bz_d(wt, shifted_branch_offset(L)); 797 } 798 void bnz_v(MSARegister wt, int16_t offset); bnz_v(MSARegister wt,Label * L)799 inline void bnz_v(MSARegister wt, Label* L) { 800 bnz_v(wt, shifted_branch_offset(L)); 801 } 802 void bnz_b(MSARegister wt, int16_t offset); bnz_b(MSARegister wt,Label * L)803 inline void bnz_b(MSARegister wt, Label* L) { 804 bnz_b(wt, shifted_branch_offset(L)); 805 } 806 void bnz_h(MSARegister wt, int16_t offset); bnz_h(MSARegister wt,Label * L)807 inline void bnz_h(MSARegister wt, Label* L) { 808 bnz_h(wt, shifted_branch_offset(L)); 809 } 810 void bnz_w(MSARegister wt, int16_t offset); bnz_w(MSARegister wt,Label * L)811 inline void bnz_w(MSARegister wt, Label* L) { 812 bnz_w(wt, shifted_branch_offset(L)); 813 } 814 void bnz_d(MSARegister wt, int16_t offset); bnz_d(MSARegister wt,Label * L)815 inline void bnz_d(MSARegister wt, Label* L) { 816 bnz_d(wt, shifted_branch_offset(L)); 817 } 818 819 void ld_b(MSARegister wd, const MemOperand& rs); 820 void ld_h(MSARegister wd, const MemOperand& rs); 821 void ld_w(MSARegister wd, const MemOperand& rs); 822 void ld_d(MSARegister wd, const MemOperand& rs); 823 void st_b(MSARegister wd, const MemOperand& rs); 824 void st_h(MSARegister wd, const MemOperand& rs); 825 void st_w(MSARegister wd, const MemOperand& rs); 826 void st_d(MSARegister wd, const MemOperand& rs); 827 828 void ldi_b(MSARegister wd, int32_t imm10); 829 void ldi_h(MSARegister wd, int32_t imm10); 830 void ldi_w(MSARegister wd, int32_t imm10); 831 void ldi_d(MSARegister wd, int32_t imm10); 832 833 void addvi_b(MSARegister wd, MSARegister ws, uint32_t imm5); 834 void addvi_h(MSARegister wd, MSARegister ws, uint32_t imm5); 835 void addvi_w(MSARegister wd, MSARegister ws, uint32_t imm5); 836 void addvi_d(MSARegister wd, MSARegister ws, uint32_t imm5); 837 void subvi_b(MSARegister wd, MSARegister ws, uint32_t imm5); 838 void subvi_h(MSARegister wd, MSARegister ws, uint32_t imm5); 839 void subvi_w(MSARegister wd, MSARegister ws, uint32_t imm5); 840 void subvi_d(MSARegister wd, MSARegister ws, uint32_t imm5); 841 void maxi_s_b(MSARegister wd, MSARegister ws, uint32_t imm5); 842 void maxi_s_h(MSARegister wd, MSARegister ws, uint32_t imm5); 843 void maxi_s_w(MSARegister wd, MSARegister ws, uint32_t imm5); 844 void maxi_s_d(MSARegister wd, MSARegister ws, uint32_t imm5); 845 void maxi_u_b(MSARegister wd, MSARegister ws, uint32_t imm5); 846 void maxi_u_h(MSARegister wd, MSARegister ws, uint32_t imm5); 847 void maxi_u_w(MSARegister wd, MSARegister ws, uint32_t imm5); 848 void maxi_u_d(MSARegister wd, MSARegister ws, uint32_t imm5); 849 void mini_s_b(MSARegister wd, MSARegister ws, uint32_t imm5); 850 void mini_s_h(MSARegister wd, MSARegister ws, uint32_t imm5); 851 void mini_s_w(MSARegister wd, MSARegister ws, uint32_t imm5); 852 void mini_s_d(MSARegister wd, MSARegister ws, uint32_t imm5); 853 void mini_u_b(MSARegister wd, MSARegister ws, uint32_t imm5); 854 void mini_u_h(MSARegister wd, MSARegister ws, uint32_t imm5); 855 void mini_u_w(MSARegister wd, MSARegister ws, uint32_t imm5); 856 void mini_u_d(MSARegister wd, MSARegister ws, uint32_t imm5); 857 void ceqi_b(MSARegister wd, MSARegister ws, uint32_t imm5); 858 void ceqi_h(MSARegister wd, MSARegister ws, uint32_t imm5); 859 void ceqi_w(MSARegister wd, MSARegister ws, uint32_t imm5); 860 void ceqi_d(MSARegister wd, MSARegister ws, uint32_t imm5); 861 void clti_s_b(MSARegister wd, MSARegister ws, uint32_t imm5); 862 void clti_s_h(MSARegister wd, MSARegister ws, uint32_t imm5); 863 void clti_s_w(MSARegister wd, MSARegister ws, uint32_t imm5); 864 void clti_s_d(MSARegister wd, MSARegister ws, uint32_t imm5); 865 void clti_u_b(MSARegister wd, MSARegister ws, uint32_t imm5); 866 void clti_u_h(MSARegister wd, MSARegister ws, uint32_t imm5); 867 void clti_u_w(MSARegister wd, MSARegister ws, uint32_t imm5); 868 void clti_u_d(MSARegister wd, MSARegister ws, uint32_t imm5); 869 void clei_s_b(MSARegister wd, MSARegister ws, uint32_t imm5); 870 void clei_s_h(MSARegister wd, MSARegister ws, uint32_t imm5); 871 void clei_s_w(MSARegister wd, MSARegister ws, uint32_t imm5); 872 void clei_s_d(MSARegister wd, MSARegister ws, uint32_t imm5); 873 void clei_u_b(MSARegister wd, MSARegister ws, uint32_t imm5); 874 void clei_u_h(MSARegister wd, MSARegister ws, uint32_t imm5); 875 void clei_u_w(MSARegister wd, MSARegister ws, uint32_t imm5); 876 void clei_u_d(MSARegister wd, MSARegister ws, uint32_t imm5); 877 878 void andi_b(MSARegister wd, MSARegister ws, uint32_t imm8); 879 void ori_b(MSARegister wd, MSARegister ws, uint32_t imm8); 880 void nori_b(MSARegister wd, MSARegister ws, uint32_t imm8); 881 void xori_b(MSARegister wd, MSARegister ws, uint32_t imm8); 882 void bmnzi_b(MSARegister wd, MSARegister ws, uint32_t imm8); 883 void bmzi_b(MSARegister wd, MSARegister ws, uint32_t imm8); 884 void bseli_b(MSARegister wd, MSARegister ws, uint32_t imm8); 885 void shf_b(MSARegister wd, MSARegister ws, uint32_t imm8); 886 void shf_h(MSARegister wd, MSARegister ws, uint32_t imm8); 887 void shf_w(MSARegister wd, MSARegister ws, uint32_t imm8); 888 889 void and_v(MSARegister wd, MSARegister ws, MSARegister wt); 890 void or_v(MSARegister wd, MSARegister ws, MSARegister wt); 891 void nor_v(MSARegister wd, MSARegister ws, MSARegister wt); 892 void xor_v(MSARegister wd, MSARegister ws, MSARegister wt); 893 void bmnz_v(MSARegister wd, MSARegister ws, MSARegister wt); 894 void bmz_v(MSARegister wd, MSARegister ws, MSARegister wt); 895 void bsel_v(MSARegister wd, MSARegister ws, MSARegister wt); 896 897 void fill_b(MSARegister wd, Register rs); 898 void fill_h(MSARegister wd, Register rs); 899 void fill_w(MSARegister wd, Register rs); 900 void pcnt_b(MSARegister wd, MSARegister ws); 901 void pcnt_h(MSARegister wd, MSARegister ws); 902 void pcnt_w(MSARegister wd, MSARegister ws); 903 void pcnt_d(MSARegister wd, MSARegister ws); 904 void nloc_b(MSARegister wd, MSARegister ws); 905 void nloc_h(MSARegister wd, MSARegister ws); 906 void nloc_w(MSARegister wd, MSARegister ws); 907 void nloc_d(MSARegister wd, MSARegister ws); 908 void nlzc_b(MSARegister wd, MSARegister ws); 909 void nlzc_h(MSARegister wd, MSARegister ws); 910 void nlzc_w(MSARegister wd, MSARegister ws); 911 void nlzc_d(MSARegister wd, MSARegister ws); 912 913 void fclass_w(MSARegister wd, MSARegister ws); 914 void fclass_d(MSARegister wd, MSARegister ws); 915 void ftrunc_s_w(MSARegister wd, MSARegister ws); 916 void ftrunc_s_d(MSARegister wd, MSARegister ws); 917 void ftrunc_u_w(MSARegister wd, MSARegister ws); 918 void ftrunc_u_d(MSARegister wd, MSARegister ws); 919 void fsqrt_w(MSARegister wd, MSARegister ws); 920 void fsqrt_d(MSARegister wd, MSARegister ws); 921 void frsqrt_w(MSARegister wd, MSARegister ws); 922 void frsqrt_d(MSARegister wd, MSARegister ws); 923 void frcp_w(MSARegister wd, MSARegister ws); 924 void frcp_d(MSARegister wd, MSARegister ws); 925 void frint_w(MSARegister wd, MSARegister ws); 926 void frint_d(MSARegister wd, MSARegister ws); 927 void flog2_w(MSARegister wd, MSARegister ws); 928 void flog2_d(MSARegister wd, MSARegister ws); 929 void fexupl_w(MSARegister wd, MSARegister ws); 930 void fexupl_d(MSARegister wd, MSARegister ws); 931 void fexupr_w(MSARegister wd, MSARegister ws); 932 void fexupr_d(MSARegister wd, MSARegister ws); 933 void ffql_w(MSARegister wd, MSARegister ws); 934 void ffql_d(MSARegister wd, MSARegister ws); 935 void ffqr_w(MSARegister wd, MSARegister ws); 936 void ffqr_d(MSARegister wd, MSARegister ws); 937 void ftint_s_w(MSARegister wd, MSARegister ws); 938 void ftint_s_d(MSARegister wd, MSARegister ws); 939 void ftint_u_w(MSARegister wd, MSARegister ws); 940 void ftint_u_d(MSARegister wd, MSARegister ws); 941 void ffint_s_w(MSARegister wd, MSARegister ws); 942 void ffint_s_d(MSARegister wd, MSARegister ws); 943 void ffint_u_w(MSARegister wd, MSARegister ws); 944 void ffint_u_d(MSARegister wd, MSARegister ws); 945 946 void sll_b(MSARegister wd, MSARegister ws, MSARegister wt); 947 void sll_h(MSARegister wd, MSARegister ws, MSARegister wt); 948 void sll_w(MSARegister wd, MSARegister ws, MSARegister wt); 949 void sll_d(MSARegister wd, MSARegister ws, MSARegister wt); 950 void sra_b(MSARegister wd, MSARegister ws, MSARegister wt); 951 void sra_h(MSARegister wd, MSARegister ws, MSARegister wt); 952 void sra_w(MSARegister wd, MSARegister ws, MSARegister wt); 953 void sra_d(MSARegister wd, MSARegister ws, MSARegister wt); 954 void srl_b(MSARegister wd, MSARegister ws, MSARegister wt); 955 void srl_h(MSARegister wd, MSARegister ws, MSARegister wt); 956 void srl_w(MSARegister wd, MSARegister ws, MSARegister wt); 957 void srl_d(MSARegister wd, MSARegister ws, MSARegister wt); 958 void bclr_b(MSARegister wd, MSARegister ws, MSARegister wt); 959 void bclr_h(MSARegister wd, MSARegister ws, MSARegister wt); 960 void bclr_w(MSARegister wd, MSARegister ws, MSARegister wt); 961 void bclr_d(MSARegister wd, MSARegister ws, MSARegister wt); 962 void bset_b(MSARegister wd, MSARegister ws, MSARegister wt); 963 void bset_h(MSARegister wd, MSARegister ws, MSARegister wt); 964 void bset_w(MSARegister wd, MSARegister ws, MSARegister wt); 965 void bset_d(MSARegister wd, MSARegister ws, MSARegister wt); 966 void bneg_b(MSARegister wd, MSARegister ws, MSARegister wt); 967 void bneg_h(MSARegister wd, MSARegister ws, MSARegister wt); 968 void bneg_w(MSARegister wd, MSARegister ws, MSARegister wt); 969 void bneg_d(MSARegister wd, MSARegister ws, MSARegister wt); 970 void binsl_b(MSARegister wd, MSARegister ws, MSARegister wt); 971 void binsl_h(MSARegister wd, MSARegister ws, MSARegister wt); 972 void binsl_w(MSARegister wd, MSARegister ws, MSARegister wt); 973 void binsl_d(MSARegister wd, MSARegister ws, MSARegister wt); 974 void binsr_b(MSARegister wd, MSARegister ws, MSARegister wt); 975 void binsr_h(MSARegister wd, MSARegister ws, MSARegister wt); 976 void binsr_w(MSARegister wd, MSARegister ws, MSARegister wt); 977 void binsr_d(MSARegister wd, MSARegister ws, MSARegister wt); 978 void addv_b(MSARegister wd, MSARegister ws, MSARegister wt); 979 void addv_h(MSARegister wd, MSARegister ws, MSARegister wt); 980 void addv_w(MSARegister wd, MSARegister ws, MSARegister wt); 981 void addv_d(MSARegister wd, MSARegister ws, MSARegister wt); 982 void subv_b(MSARegister wd, MSARegister ws, MSARegister wt); 983 void subv_h(MSARegister wd, MSARegister ws, MSARegister wt); 984 void subv_w(MSARegister wd, MSARegister ws, MSARegister wt); 985 void subv_d(MSARegister wd, MSARegister ws, MSARegister wt); 986 void max_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 987 void max_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 988 void max_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 989 void max_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 990 void max_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 991 void max_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 992 void max_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 993 void max_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 994 void min_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 995 void min_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 996 void min_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 997 void min_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 998 void min_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 999 void min_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1000 void min_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1001 void min_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1002 void max_a_b(MSARegister wd, MSARegister ws, MSARegister wt); 1003 void max_a_h(MSARegister wd, MSARegister ws, MSARegister wt); 1004 void max_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1005 void max_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1006 void min_a_b(MSARegister wd, MSARegister ws, MSARegister wt); 1007 void min_a_h(MSARegister wd, MSARegister ws, MSARegister wt); 1008 void min_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1009 void min_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1010 void ceq_b(MSARegister wd, MSARegister ws, MSARegister wt); 1011 void ceq_h(MSARegister wd, MSARegister ws, MSARegister wt); 1012 void ceq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1013 void ceq_d(MSARegister wd, MSARegister ws, MSARegister wt); 1014 void clt_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1015 void clt_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1016 void clt_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1017 void clt_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1018 void clt_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1019 void clt_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1020 void clt_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1021 void clt_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1022 void cle_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1023 void cle_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1024 void cle_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1025 void cle_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1026 void cle_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1027 void cle_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1028 void cle_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1029 void cle_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1030 void add_a_b(MSARegister wd, MSARegister ws, MSARegister wt); 1031 void add_a_h(MSARegister wd, MSARegister ws, MSARegister wt); 1032 void add_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1033 void add_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1034 void adds_a_b(MSARegister wd, MSARegister ws, MSARegister wt); 1035 void adds_a_h(MSARegister wd, MSARegister ws, MSARegister wt); 1036 void adds_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1037 void adds_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1038 void adds_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1039 void adds_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1040 void adds_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1041 void adds_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1042 void adds_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1043 void adds_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1044 void adds_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1045 void adds_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1046 void ave_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1047 void ave_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1048 void ave_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1049 void ave_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1050 void ave_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1051 void ave_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1052 void ave_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1053 void ave_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1054 void aver_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1055 void aver_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1056 void aver_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1057 void aver_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1058 void aver_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1059 void aver_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1060 void aver_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1061 void aver_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1062 void subs_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1063 void subs_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1064 void subs_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1065 void subs_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1066 void subs_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1067 void subs_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1068 void subs_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1069 void subs_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1070 void subsus_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1071 void subsus_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1072 void subsus_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1073 void subsus_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1074 void subsus_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1075 void subsus_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1076 void subsus_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1077 void subsus_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1078 void subsuu_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1079 void subsuu_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1080 void subsuu_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1081 void subsuu_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1082 void subsuu_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1083 void subsuu_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1084 void subsuu_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1085 void subsuu_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1086 void asub_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1087 void asub_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1088 void asub_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1089 void asub_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1090 void asub_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1091 void asub_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1092 void asub_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1093 void asub_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1094 void mulv_b(MSARegister wd, MSARegister ws, MSARegister wt); 1095 void mulv_h(MSARegister wd, MSARegister ws, MSARegister wt); 1096 void mulv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1097 void mulv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1098 void maddv_b(MSARegister wd, MSARegister ws, MSARegister wt); 1099 void maddv_h(MSARegister wd, MSARegister ws, MSARegister wt); 1100 void maddv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1101 void maddv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1102 void msubv_b(MSARegister wd, MSARegister ws, MSARegister wt); 1103 void msubv_h(MSARegister wd, MSARegister ws, MSARegister wt); 1104 void msubv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1105 void msubv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1106 void div_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1107 void div_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1108 void div_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1109 void div_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1110 void div_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1111 void div_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1112 void div_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1113 void div_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1114 void mod_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1115 void mod_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1116 void mod_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1117 void mod_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1118 void mod_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1119 void mod_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1120 void mod_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1121 void mod_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1122 void dotp_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1123 void dotp_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1124 void dotp_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1125 void dotp_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1126 void dotp_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1127 void dotp_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1128 void dotp_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1129 void dotp_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1130 void dpadd_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1131 void dpadd_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1132 void dpadd_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1133 void dpadd_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1134 void dpadd_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1135 void dpadd_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1136 void dpadd_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1137 void dpadd_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1138 void dpsub_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1139 void dpsub_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1140 void dpsub_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1141 void dpsub_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1142 void dpsub_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1143 void dpsub_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1144 void dpsub_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1145 void dpsub_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1146 void sld_b(MSARegister wd, MSARegister ws, Register rt); 1147 void sld_h(MSARegister wd, MSARegister ws, Register rt); 1148 void sld_w(MSARegister wd, MSARegister ws, Register rt); 1149 void sld_d(MSARegister wd, MSARegister ws, Register rt); 1150 void splat_b(MSARegister wd, MSARegister ws, Register rt); 1151 void splat_h(MSARegister wd, MSARegister ws, Register rt); 1152 void splat_w(MSARegister wd, MSARegister ws, Register rt); 1153 void splat_d(MSARegister wd, MSARegister ws, Register rt); 1154 void pckev_b(MSARegister wd, MSARegister ws, MSARegister wt); 1155 void pckev_h(MSARegister wd, MSARegister ws, MSARegister wt); 1156 void pckev_w(MSARegister wd, MSARegister ws, MSARegister wt); 1157 void pckev_d(MSARegister wd, MSARegister ws, MSARegister wt); 1158 void pckod_b(MSARegister wd, MSARegister ws, MSARegister wt); 1159 void pckod_h(MSARegister wd, MSARegister ws, MSARegister wt); 1160 void pckod_w(MSARegister wd, MSARegister ws, MSARegister wt); 1161 void pckod_d(MSARegister wd, MSARegister ws, MSARegister wt); 1162 void ilvl_b(MSARegister wd, MSARegister ws, MSARegister wt); 1163 void ilvl_h(MSARegister wd, MSARegister ws, MSARegister wt); 1164 void ilvl_w(MSARegister wd, MSARegister ws, MSARegister wt); 1165 void ilvl_d(MSARegister wd, MSARegister ws, MSARegister wt); 1166 void ilvr_b(MSARegister wd, MSARegister ws, MSARegister wt); 1167 void ilvr_h(MSARegister wd, MSARegister ws, MSARegister wt); 1168 void ilvr_w(MSARegister wd, MSARegister ws, MSARegister wt); 1169 void ilvr_d(MSARegister wd, MSARegister ws, MSARegister wt); 1170 void ilvev_b(MSARegister wd, MSARegister ws, MSARegister wt); 1171 void ilvev_h(MSARegister wd, MSARegister ws, MSARegister wt); 1172 void ilvev_w(MSARegister wd, MSARegister ws, MSARegister wt); 1173 void ilvev_d(MSARegister wd, MSARegister ws, MSARegister wt); 1174 void ilvod_b(MSARegister wd, MSARegister ws, MSARegister wt); 1175 void ilvod_h(MSARegister wd, MSARegister ws, MSARegister wt); 1176 void ilvod_w(MSARegister wd, MSARegister ws, MSARegister wt); 1177 void ilvod_d(MSARegister wd, MSARegister ws, MSARegister wt); 1178 void vshf_b(MSARegister wd, MSARegister ws, MSARegister wt); 1179 void vshf_h(MSARegister wd, MSARegister ws, MSARegister wt); 1180 void vshf_w(MSARegister wd, MSARegister ws, MSARegister wt); 1181 void vshf_d(MSARegister wd, MSARegister ws, MSARegister wt); 1182 void srar_b(MSARegister wd, MSARegister ws, MSARegister wt); 1183 void srar_h(MSARegister wd, MSARegister ws, MSARegister wt); 1184 void srar_w(MSARegister wd, MSARegister ws, MSARegister wt); 1185 void srar_d(MSARegister wd, MSARegister ws, MSARegister wt); 1186 void srlr_b(MSARegister wd, MSARegister ws, MSARegister wt); 1187 void srlr_h(MSARegister wd, MSARegister ws, MSARegister wt); 1188 void srlr_w(MSARegister wd, MSARegister ws, MSARegister wt); 1189 void srlr_d(MSARegister wd, MSARegister ws, MSARegister wt); 1190 void hadd_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1191 void hadd_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1192 void hadd_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1193 void hadd_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1194 void hadd_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1195 void hadd_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1196 void hadd_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1197 void hadd_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1198 void hsub_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1199 void hsub_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1200 void hsub_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1201 void hsub_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1202 void hsub_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1203 void hsub_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1204 void hsub_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1205 void hsub_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1206 1207 void fcaf_w(MSARegister wd, MSARegister ws, MSARegister wt); 1208 void fcaf_d(MSARegister wd, MSARegister ws, MSARegister wt); 1209 void fcun_w(MSARegister wd, MSARegister ws, MSARegister wt); 1210 void fcun_d(MSARegister wd, MSARegister ws, MSARegister wt); 1211 void fceq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1212 void fceq_d(MSARegister wd, MSARegister ws, MSARegister wt); 1213 void fcueq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1214 void fcueq_d(MSARegister wd, MSARegister ws, MSARegister wt); 1215 void fclt_w(MSARegister wd, MSARegister ws, MSARegister wt); 1216 void fclt_d(MSARegister wd, MSARegister ws, MSARegister wt); 1217 void fcult_w(MSARegister wd, MSARegister ws, MSARegister wt); 1218 void fcult_d(MSARegister wd, MSARegister ws, MSARegister wt); 1219 void fcle_w(MSARegister wd, MSARegister ws, MSARegister wt); 1220 void fcle_d(MSARegister wd, MSARegister ws, MSARegister wt); 1221 void fcule_w(MSARegister wd, MSARegister ws, MSARegister wt); 1222 void fcule_d(MSARegister wd, MSARegister ws, MSARegister wt); 1223 void fsaf_w(MSARegister wd, MSARegister ws, MSARegister wt); 1224 void fsaf_d(MSARegister wd, MSARegister ws, MSARegister wt); 1225 void fsun_w(MSARegister wd, MSARegister ws, MSARegister wt); 1226 void fsun_d(MSARegister wd, MSARegister ws, MSARegister wt); 1227 void fseq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1228 void fseq_d(MSARegister wd, MSARegister ws, MSARegister wt); 1229 void fsueq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1230 void fsueq_d(MSARegister wd, MSARegister ws, MSARegister wt); 1231 void fslt_w(MSARegister wd, MSARegister ws, MSARegister wt); 1232 void fslt_d(MSARegister wd, MSARegister ws, MSARegister wt); 1233 void fsult_w(MSARegister wd, MSARegister ws, MSARegister wt); 1234 void fsult_d(MSARegister wd, MSARegister ws, MSARegister wt); 1235 void fsle_w(MSARegister wd, MSARegister ws, MSARegister wt); 1236 void fsle_d(MSARegister wd, MSARegister ws, MSARegister wt); 1237 void fsule_w(MSARegister wd, MSARegister ws, MSARegister wt); 1238 void fsule_d(MSARegister wd, MSARegister ws, MSARegister wt); 1239 void fadd_w(MSARegister wd, MSARegister ws, MSARegister wt); 1240 void fadd_d(MSARegister wd, MSARegister ws, MSARegister wt); 1241 void fsub_w(MSARegister wd, MSARegister ws, MSARegister wt); 1242 void fsub_d(MSARegister wd, MSARegister ws, MSARegister wt); 1243 void fmul_w(MSARegister wd, MSARegister ws, MSARegister wt); 1244 void fmul_d(MSARegister wd, MSARegister ws, MSARegister wt); 1245 void fdiv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1246 void fdiv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1247 void fmadd_w(MSARegister wd, MSARegister ws, MSARegister wt); 1248 void fmadd_d(MSARegister wd, MSARegister ws, MSARegister wt); 1249 void fmsub_w(MSARegister wd, MSARegister ws, MSARegister wt); 1250 void fmsub_d(MSARegister wd, MSARegister ws, MSARegister wt); 1251 void fexp2_w(MSARegister wd, MSARegister ws, MSARegister wt); 1252 void fexp2_d(MSARegister wd, MSARegister ws, MSARegister wt); 1253 void fexdo_h(MSARegister wd, MSARegister ws, MSARegister wt); 1254 void fexdo_w(MSARegister wd, MSARegister ws, MSARegister wt); 1255 void ftq_h(MSARegister wd, MSARegister ws, MSARegister wt); 1256 void ftq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1257 void fmin_w(MSARegister wd, MSARegister ws, MSARegister wt); 1258 void fmin_d(MSARegister wd, MSARegister ws, MSARegister wt); 1259 void fmin_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1260 void fmin_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1261 void fmax_w(MSARegister wd, MSARegister ws, MSARegister wt); 1262 void fmax_d(MSARegister wd, MSARegister ws, MSARegister wt); 1263 void fmax_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1264 void fmax_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1265 void fcor_w(MSARegister wd, MSARegister ws, MSARegister wt); 1266 void fcor_d(MSARegister wd, MSARegister ws, MSARegister wt); 1267 void fcune_w(MSARegister wd, MSARegister ws, MSARegister wt); 1268 void fcune_d(MSARegister wd, MSARegister ws, MSARegister wt); 1269 void fcne_w(MSARegister wd, MSARegister ws, MSARegister wt); 1270 void fcne_d(MSARegister wd, MSARegister ws, MSARegister wt); 1271 void mul_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1272 void mul_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1273 void madd_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1274 void madd_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1275 void msub_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1276 void msub_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1277 void fsor_w(MSARegister wd, MSARegister ws, MSARegister wt); 1278 void fsor_d(MSARegister wd, MSARegister ws, MSARegister wt); 1279 void fsune_w(MSARegister wd, MSARegister ws, MSARegister wt); 1280 void fsune_d(MSARegister wd, MSARegister ws, MSARegister wt); 1281 void fsne_w(MSARegister wd, MSARegister ws, MSARegister wt); 1282 void fsne_d(MSARegister wd, MSARegister ws, MSARegister wt); 1283 void mulr_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1284 void mulr_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1285 void maddr_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1286 void maddr_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1287 void msubr_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1288 void msubr_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1289 1290 void sldi_b(MSARegister wd, MSARegister ws, uint32_t n); 1291 void sldi_h(MSARegister wd, MSARegister ws, uint32_t n); 1292 void sldi_w(MSARegister wd, MSARegister ws, uint32_t n); 1293 void sldi_d(MSARegister wd, MSARegister ws, uint32_t n); 1294 void splati_b(MSARegister wd, MSARegister ws, uint32_t n); 1295 void splati_h(MSARegister wd, MSARegister ws, uint32_t n); 1296 void splati_w(MSARegister wd, MSARegister ws, uint32_t n); 1297 void splati_d(MSARegister wd, MSARegister ws, uint32_t n); 1298 void copy_s_b(Register rd, MSARegister ws, uint32_t n); 1299 void copy_s_h(Register rd, MSARegister ws, uint32_t n); 1300 void copy_s_w(Register rd, MSARegister ws, uint32_t n); 1301 void copy_u_b(Register rd, MSARegister ws, uint32_t n); 1302 void copy_u_h(Register rd, MSARegister ws, uint32_t n); 1303 void copy_u_w(Register rd, MSARegister ws, uint32_t n); 1304 void insert_b(MSARegister wd, uint32_t n, Register rs); 1305 void insert_h(MSARegister wd, uint32_t n, Register rs); 1306 void insert_w(MSARegister wd, uint32_t n, Register rs); 1307 void insve_b(MSARegister wd, uint32_t n, MSARegister ws); 1308 void insve_h(MSARegister wd, uint32_t n, MSARegister ws); 1309 void insve_w(MSARegister wd, uint32_t n, MSARegister ws); 1310 void insve_d(MSARegister wd, uint32_t n, MSARegister ws); 1311 void move_v(MSARegister wd, MSARegister ws); 1312 void ctcmsa(MSAControlRegister cd, Register rs); 1313 void cfcmsa(Register rd, MSAControlRegister cs); 1314 1315 void slli_b(MSARegister wd, MSARegister ws, uint32_t m); 1316 void slli_h(MSARegister wd, MSARegister ws, uint32_t m); 1317 void slli_w(MSARegister wd, MSARegister ws, uint32_t m); 1318 void slli_d(MSARegister wd, MSARegister ws, uint32_t m); 1319 void srai_b(MSARegister wd, MSARegister ws, uint32_t m); 1320 void srai_h(MSARegister wd, MSARegister ws, uint32_t m); 1321 void srai_w(MSARegister wd, MSARegister ws, uint32_t m); 1322 void srai_d(MSARegister wd, MSARegister ws, uint32_t m); 1323 void srli_b(MSARegister wd, MSARegister ws, uint32_t m); 1324 void srli_h(MSARegister wd, MSARegister ws, uint32_t m); 1325 void srli_w(MSARegister wd, MSARegister ws, uint32_t m); 1326 void srli_d(MSARegister wd, MSARegister ws, uint32_t m); 1327 void bclri_b(MSARegister wd, MSARegister ws, uint32_t m); 1328 void bclri_h(MSARegister wd, MSARegister ws, uint32_t m); 1329 void bclri_w(MSARegister wd, MSARegister ws, uint32_t m); 1330 void bclri_d(MSARegister wd, MSARegister ws, uint32_t m); 1331 void bseti_b(MSARegister wd, MSARegister ws, uint32_t m); 1332 void bseti_h(MSARegister wd, MSARegister ws, uint32_t m); 1333 void bseti_w(MSARegister wd, MSARegister ws, uint32_t m); 1334 void bseti_d(MSARegister wd, MSARegister ws, uint32_t m); 1335 void bnegi_b(MSARegister wd, MSARegister ws, uint32_t m); 1336 void bnegi_h(MSARegister wd, MSARegister ws, uint32_t m); 1337 void bnegi_w(MSARegister wd, MSARegister ws, uint32_t m); 1338 void bnegi_d(MSARegister wd, MSARegister ws, uint32_t m); 1339 void binsli_b(MSARegister wd, MSARegister ws, uint32_t m); 1340 void binsli_h(MSARegister wd, MSARegister ws, uint32_t m); 1341 void binsli_w(MSARegister wd, MSARegister ws, uint32_t m); 1342 void binsli_d(MSARegister wd, MSARegister ws, uint32_t m); 1343 void binsri_b(MSARegister wd, MSARegister ws, uint32_t m); 1344 void binsri_h(MSARegister wd, MSARegister ws, uint32_t m); 1345 void binsri_w(MSARegister wd, MSARegister ws, uint32_t m); 1346 void binsri_d(MSARegister wd, MSARegister ws, uint32_t m); 1347 void sat_s_b(MSARegister wd, MSARegister ws, uint32_t m); 1348 void sat_s_h(MSARegister wd, MSARegister ws, uint32_t m); 1349 void sat_s_w(MSARegister wd, MSARegister ws, uint32_t m); 1350 void sat_s_d(MSARegister wd, MSARegister ws, uint32_t m); 1351 void sat_u_b(MSARegister wd, MSARegister ws, uint32_t m); 1352 void sat_u_h(MSARegister wd, MSARegister ws, uint32_t m); 1353 void sat_u_w(MSARegister wd, MSARegister ws, uint32_t m); 1354 void sat_u_d(MSARegister wd, MSARegister ws, uint32_t m); 1355 void srari_b(MSARegister wd, MSARegister ws, uint32_t m); 1356 void srari_h(MSARegister wd, MSARegister ws, uint32_t m); 1357 void srari_w(MSARegister wd, MSARegister ws, uint32_t m); 1358 void srari_d(MSARegister wd, MSARegister ws, uint32_t m); 1359 void srlri_b(MSARegister wd, MSARegister ws, uint32_t m); 1360 void srlri_h(MSARegister wd, MSARegister ws, uint32_t m); 1361 void srlri_w(MSARegister wd, MSARegister ws, uint32_t m); 1362 void srlri_d(MSARegister wd, MSARegister ws, uint32_t m); 1363 1364 // Check the code size generated from label to here. SizeOfCodeGeneratedSince(Label * label)1365 int SizeOfCodeGeneratedSince(Label* label) { 1366 return pc_offset() - label->pos(); 1367 } 1368 1369 // Check the number of instructions generated from label to here. InstructionsGeneratedSince(Label * label)1370 int InstructionsGeneratedSince(Label* label) { 1371 return SizeOfCodeGeneratedSince(label) / kInstrSize; 1372 } 1373 1374 // Class for scoping postponing the trampoline pool generation. 1375 class BlockTrampolinePoolScope { 1376 public: BlockTrampolinePoolScope(Assembler * assem)1377 explicit BlockTrampolinePoolScope(Assembler* assem) : assem_(assem) { 1378 assem_->StartBlockTrampolinePool(); 1379 } ~BlockTrampolinePoolScope()1380 ~BlockTrampolinePoolScope() { assem_->EndBlockTrampolinePool(); } 1381 1382 private: 1383 Assembler* assem_; 1384 1385 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockTrampolinePoolScope); 1386 }; 1387 1388 // Class for postponing the assembly buffer growth. Typically used for 1389 // sequences of instructions that must be emitted as a unit, before 1390 // buffer growth (and relocation) can occur. 1391 // This blocking scope is not nestable. 1392 class BlockGrowBufferScope { 1393 public: BlockGrowBufferScope(Assembler * assem)1394 explicit BlockGrowBufferScope(Assembler* assem) : assem_(assem) { 1395 assem_->StartBlockGrowBuffer(); 1396 } ~BlockGrowBufferScope()1397 ~BlockGrowBufferScope() { assem_->EndBlockGrowBuffer(); } 1398 1399 private: 1400 Assembler* assem_; 1401 1402 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockGrowBufferScope); 1403 }; 1404 1405 // Record a deoptimization reason that can be used by a log or cpu profiler. 1406 // Use --trace-deopt to enable. 1407 void RecordDeoptReason(DeoptimizeReason reason, SourcePosition position, 1408 int id); 1409 1410 static int RelocateInternalReference(RelocInfo::Mode rmode, Address pc, 1411 intptr_t pc_delta); 1412 1413 static void RelocateRelativeReference(RelocInfo::Mode rmode, Address pc, 1414 intptr_t pc_delta); 1415 1416 // Writes a single byte or word of data in the code stream. Used for 1417 // inline tables, e.g., jump-tables. 1418 void db(uint8_t data); 1419 void dd(uint32_t data); 1420 void dq(uint64_t data); dp(uintptr_t data)1421 void dp(uintptr_t data) { dd(data); } 1422 void dd(Label* label); 1423 1424 // Postpone the generation of the trampoline pool for the specified number of 1425 // instructions. 1426 void BlockTrampolinePoolFor(int instructions); 1427 1428 // Check if there is less than kGap bytes available in the buffer. 1429 // If this is the case, we need to grow the buffer before emitting 1430 // an instruction or relocation information. overflow()1431 inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; } 1432 1433 // Get the number of bytes available in the buffer. available_space()1434 inline int available_space() const { return reloc_info_writer.pos() - pc_; } 1435 1436 // Read/patch instructions. instr_at(Address pc)1437 static Instr instr_at(Address pc) { return *reinterpret_cast<Instr*>(pc); } instr_at_put(Address pc,Instr instr)1438 static void instr_at_put(Address pc, Instr instr) { 1439 *reinterpret_cast<Instr*>(pc) = instr; 1440 } instr_at(int pos)1441 Instr instr_at(int pos) { 1442 return *reinterpret_cast<Instr*>(buffer_start_ + pos); 1443 } instr_at_put(int pos,Instr instr)1444 void instr_at_put(int pos, Instr instr) { 1445 *reinterpret_cast<Instr*>(buffer_start_ + pos) = instr; 1446 } 1447 1448 // Check if an instruction is a branch of some kind. 1449 static bool IsBranch(Instr instr); 1450 static bool IsMsaBranch(Instr instr); 1451 static bool IsBc(Instr instr); 1452 static bool IsNal(Instr instr); 1453 static bool IsBzc(Instr instr); 1454 static bool IsBeq(Instr instr); 1455 static bool IsBne(Instr instr); 1456 static bool IsBeqzc(Instr instr); 1457 static bool IsBnezc(Instr instr); 1458 static bool IsBeqc(Instr instr); 1459 static bool IsBnec(Instr instr); 1460 static bool IsJicOrJialc(Instr instr); 1461 static bool IsMov(Instr instr, Register rd, Register rs); 1462 1463 static bool IsJump(Instr instr); 1464 static bool IsJ(Instr instr); 1465 static bool IsLui(Instr instr); 1466 static bool IsOri(Instr instr); 1467 static bool IsAddu(Instr instr, Register rd, Register rs, Register rt); 1468 1469 static bool IsJal(Instr instr); 1470 static bool IsJr(Instr instr); 1471 static bool IsJalr(Instr instr); 1472 1473 static bool IsNop(Instr instr, unsigned int type); 1474 static bool IsPop(Instr instr); 1475 static bool IsPush(Instr instr); 1476 static bool IsLwRegFpOffset(Instr instr); 1477 static bool IsSwRegFpOffset(Instr instr); 1478 static bool IsLwRegFpNegOffset(Instr instr); 1479 static bool IsSwRegFpNegOffset(Instr instr); 1480 1481 static Register GetRtReg(Instr instr); 1482 static Register GetRsReg(Instr instr); 1483 static Register GetRdReg(Instr instr); 1484 1485 static uint32_t GetRt(Instr instr); 1486 static uint32_t GetRtField(Instr instr); 1487 static uint32_t GetRs(Instr instr); 1488 static uint32_t GetRsField(Instr instr); 1489 static uint32_t GetRd(Instr instr); 1490 static uint32_t GetRdField(Instr instr); 1491 static uint32_t GetSa(Instr instr); 1492 static uint32_t GetSaField(Instr instr); 1493 static uint32_t GetOpcodeField(Instr instr); 1494 static uint32_t GetFunction(Instr instr); 1495 static uint32_t GetFunctionField(Instr instr); 1496 static uint32_t GetImmediate16(Instr instr); 1497 static uint32_t GetLabelConst(Instr instr); 1498 1499 static int32_t GetBranchOffset(Instr instr); 1500 static bool IsLw(Instr instr); 1501 static int16_t GetLwOffset(Instr instr); 1502 static int16_t GetJicOrJialcOffset(Instr instr); 1503 static int16_t GetLuiOffset(Instr instr); 1504 static Instr SetLwOffset(Instr instr, int16_t offset); 1505 1506 static bool IsSw(Instr instr); 1507 static Instr SetSwOffset(Instr instr, int16_t offset); 1508 static bool IsAddImmediate(Instr instr); 1509 static Instr SetAddImmediateOffset(Instr instr, int16_t offset); 1510 static uint32_t CreateTargetAddress(Instr instr_lui, Instr instr_jic); 1511 static void UnpackTargetAddress(uint32_t address, int16_t* lui_offset, 1512 int16_t* jic_offset); 1513 static void UnpackTargetAddressUnsigned(uint32_t address, 1514 uint32_t* lui_offset, 1515 uint32_t* jic_offset); 1516 1517 static bool IsAndImmediate(Instr instr); 1518 static bool IsEmittedConstant(Instr instr); 1519 1520 void CheckTrampolinePool(); 1521 IsPrevInstrCompactBranch()1522 bool IsPrevInstrCompactBranch() { return prev_instr_compact_branch_; } IsCompactBranchSupported()1523 static bool IsCompactBranchSupported() { 1524 return IsMipsArchVariant(kMips32r6); 1525 } 1526 1527 // Get the code target object for a pc-relative call or jump. 1528 V8_INLINE Handle<Code> relative_code_target_object_handle_at( 1529 Address pc_) const; 1530 UnboundLabelsCount()1531 inline int UnboundLabelsCount() { return unbound_labels_count_; } 1532 1533 protected: 1534 // Load Scaled Address instruction. 1535 void lsa(Register rd, Register rt, Register rs, uint8_t sa); 1536 1537 // Readable constants for base and offset adjustment helper, these indicate if 1538 // aside from offset, another value like offset + 4 should fit into int16. 1539 enum class OffsetAccessType : bool { 1540 SINGLE_ACCESS = false, 1541 TWO_ACCESSES = true 1542 }; 1543 1544 // Helper function for memory load/store using base register and offset. 1545 void AdjustBaseAndOffset( 1546 MemOperand* src, 1547 OffsetAccessType access_type = OffsetAccessType::SINGLE_ACCESS, 1548 int second_access_add_to_offset = 4); 1549 buffer_space()1550 int32_t buffer_space() const { return reloc_info_writer.pos() - pc_; } 1551 1552 // Decode branch instruction at pos and return branch target pos. 1553 int target_at(int pos, bool is_internal); 1554 1555 // Patch branch instruction at pos to branch to given branch target pos. 1556 void target_at_put(int pos, int target_pos, bool is_internal); 1557 1558 // Say if we need to relocate with this mode. 1559 bool MustUseReg(RelocInfo::Mode rmode); 1560 1561 // Record reloc info for current pc_. 1562 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); 1563 1564 // Read 32-bit immediate from lui, ori pair that is used to load immediate. 1565 static int32_t GetLuiOriImmediate(Instr instr1, Instr instr2); 1566 1567 // Block the emission of the trampoline pool before pc_offset. BlockTrampolinePoolBefore(int pc_offset)1568 void BlockTrampolinePoolBefore(int pc_offset) { 1569 if (no_trampoline_pool_before_ < pc_offset) 1570 no_trampoline_pool_before_ = pc_offset; 1571 } 1572 StartBlockTrampolinePool()1573 void StartBlockTrampolinePool() { trampoline_pool_blocked_nesting_++; } 1574 EndBlockTrampolinePool()1575 void EndBlockTrampolinePool() { 1576 trampoline_pool_blocked_nesting_--; 1577 if (trampoline_pool_blocked_nesting_ == 0) { 1578 CheckTrampolinePoolQuick(1); 1579 } 1580 } 1581 is_trampoline_pool_blocked()1582 bool is_trampoline_pool_blocked() const { 1583 return trampoline_pool_blocked_nesting_ > 0; 1584 } 1585 has_exception()1586 bool has_exception() const { return internal_trampoline_exception_; } 1587 is_trampoline_emitted()1588 bool is_trampoline_emitted() const { return trampoline_emitted_; } 1589 1590 // Temporarily block automatic assembly buffer growth. StartBlockGrowBuffer()1591 void StartBlockGrowBuffer() { 1592 DCHECK(!block_buffer_growth_); 1593 block_buffer_growth_ = true; 1594 } 1595 EndBlockGrowBuffer()1596 void EndBlockGrowBuffer() { 1597 DCHECK(block_buffer_growth_); 1598 block_buffer_growth_ = false; 1599 } 1600 is_buffer_growth_blocked()1601 bool is_buffer_growth_blocked() const { return block_buffer_growth_; } 1602 EmitForbiddenSlotInstruction()1603 void EmitForbiddenSlotInstruction() { 1604 if (IsPrevInstrCompactBranch()) { 1605 nop(); 1606 } 1607 } 1608 1609 inline void CheckTrampolinePoolQuick(int extra_instructions = 0) { 1610 if (pc_offset() >= next_buffer_check_ - extra_instructions * kInstrSize) { 1611 CheckTrampolinePool(); 1612 } 1613 } 1614 1615 inline void CheckBuffer(); 1616 1617 RegList scratch_register_list_; 1618 1619 // Generate common instruction sequence. 1620 void GenPCRelativeJump(Register tf, Register ts, int32_t imm32, 1621 RelocInfo::Mode rmode, BranchDelaySlot bdslot); 1622 void GenPCRelativeJumpAndLink(Register t, int32_t imm32, 1623 RelocInfo::Mode rmode, BranchDelaySlot bdslot); 1624 set_last_call_pc_(byte * pc)1625 void set_last_call_pc_(byte* pc) { last_call_pc_ = pc; } 1626 1627 private: 1628 // Avoid overflows for displacements etc. 1629 static const int kMaximalBufferSize = 512 * MB; 1630 1631 inline static void set_target_internal_reference_encoded_at(Address pc, 1632 Address target); 1633 1634 // Buffer size and constant pool distance are checked together at regular 1635 // intervals of kBufferCheckInterval emitted bytes. 1636 static constexpr int kBufferCheckInterval = 1 * KB / 2; 1637 1638 // Code generation. 1639 // The relocation writer's position is at least kGap bytes below the end of 1640 // the generated instructions. This is so that multi-instruction sequences do 1641 // not have to check for overflow. The same is true for writes of large 1642 // relocation info entries. 1643 static constexpr int kGap = 32; 1644 STATIC_ASSERT(AssemblerBase::kMinimalBufferSize >= 2 * kGap); 1645 1646 // Repeated checking whether the trampoline pool should be emitted is rather 1647 // expensive. By default we only check again once a number of instructions 1648 // has been generated. 1649 static constexpr int kCheckConstIntervalInst = 32; 1650 static constexpr int kCheckConstInterval = 1651 kCheckConstIntervalInst * kInstrSize; 1652 1653 int next_buffer_check_; // pc offset of next buffer check. 1654 1655 // Emission of the trampoline pool may be blocked in some code sequences. 1656 int trampoline_pool_blocked_nesting_; // Block emission if this is not zero. 1657 int no_trampoline_pool_before_; // Block emission before this pc offset. 1658 1659 // Keep track of the last emitted pool to guarantee a maximal distance. 1660 int last_trampoline_pool_end_; // pc offset of the end of the last pool. 1661 1662 // Automatic growth of the assembly buffer may be blocked for some sequences. 1663 bool block_buffer_growth_; // Block growth when true. 1664 1665 // Relocation information generation. 1666 // Each relocation is encoded as a variable size value. 1667 static constexpr int kMaxRelocSize = RelocInfoWriter::kMaxSize; 1668 RelocInfoWriter reloc_info_writer; 1669 1670 // The bound position, before this we cannot do instruction elimination. 1671 int last_bound_pos_; 1672 1673 // Readable constants for compact branch handling in emit() 1674 enum class CompactBranchType : bool { NO = false, COMPACT_BRANCH = true }; 1675 1676 // Code emission. 1677 void GrowBuffer(); 1678 inline void emit(Instr x, 1679 CompactBranchType is_compact_branch = CompactBranchType::NO); 1680 inline void emit(uint64_t x); 1681 inline void CheckForEmitInForbiddenSlot(); 1682 template <typename T> 1683 inline void EmitHelper(T x); 1684 inline void EmitHelper(Instr x, CompactBranchType is_compact_branch); 1685 1686 // Instruction generation. 1687 // We have 3 different kind of encoding layout on MIPS. 1688 // However due to many different types of objects encoded in the same fields 1689 // we have quite a few aliases for each mode. 1690 // Using the same structure to refer to Register and FPURegister would spare a 1691 // few aliases, but mixing both does not look clean to me. 1692 // Anyway we could surely implement this differently. 1693 1694 void GenInstrRegister(Opcode opcode, Register rs, Register rt, Register rd, 1695 uint16_t sa = 0, SecondaryField func = nullptrSF); 1696 1697 void GenInstrRegister(Opcode opcode, Register rs, Register rt, uint16_t msb, 1698 uint16_t lsb, SecondaryField func); 1699 1700 void GenInstrRegister(Opcode opcode, SecondaryField fmt, FPURegister ft, 1701 FPURegister fs, FPURegister fd, 1702 SecondaryField func = nullptrSF); 1703 1704 void GenInstrRegister(Opcode opcode, FPURegister fr, FPURegister ft, 1705 FPURegister fs, FPURegister fd, 1706 SecondaryField func = nullptrSF); 1707 1708 void GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, 1709 FPURegister fs, FPURegister fd, 1710 SecondaryField func = nullptrSF); 1711 1712 void GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, 1713 FPUControlRegister fs, SecondaryField func = nullptrSF); 1714 1715 void GenInstrImmediate( 1716 Opcode opcode, Register rs, Register rt, int32_t j, 1717 CompactBranchType is_compact_branch = CompactBranchType::NO); 1718 void GenInstrImmediate( 1719 Opcode opcode, Register rs, SecondaryField SF, int32_t j, 1720 CompactBranchType is_compact_branch = CompactBranchType::NO); 1721 void GenInstrImmediate( 1722 Opcode opcode, Register r1, FPURegister r2, int32_t j, 1723 CompactBranchType is_compact_branch = CompactBranchType::NO); 1724 void GenInstrImmediate(Opcode opcode, Register base, Register rt, 1725 int32_t offset9, int bit6, SecondaryField func); 1726 void GenInstrImmediate( 1727 Opcode opcode, Register rs, int32_t offset21, 1728 CompactBranchType is_compact_branch = CompactBranchType::NO); 1729 void GenInstrImmediate(Opcode opcode, Register rs, uint32_t offset21); 1730 void GenInstrImmediate( 1731 Opcode opcode, int32_t offset26, 1732 CompactBranchType is_compact_branch = CompactBranchType::NO); 1733 1734 void GenInstrJump(Opcode opcode, uint32_t address); 1735 1736 // MSA 1737 void GenInstrMsaI8(SecondaryField operation, uint32_t imm8, MSARegister ws, 1738 MSARegister wd); 1739 1740 void GenInstrMsaI5(SecondaryField operation, SecondaryField df, int32_t imm5, 1741 MSARegister ws, MSARegister wd); 1742 1743 void GenInstrMsaBit(SecondaryField operation, SecondaryField df, uint32_t m, 1744 MSARegister ws, MSARegister wd); 1745 1746 void GenInstrMsaI10(SecondaryField operation, SecondaryField df, 1747 int32_t imm10, MSARegister wd); 1748 1749 template <typename RegType> 1750 void GenInstrMsa3R(SecondaryField operation, SecondaryField df, RegType t, 1751 MSARegister ws, MSARegister wd); 1752 1753 template <typename DstType, typename SrcType> 1754 void GenInstrMsaElm(SecondaryField operation, SecondaryField df, uint32_t n, 1755 SrcType src, DstType dst); 1756 1757 void GenInstrMsa3RF(SecondaryField operation, uint32_t df, MSARegister wt, 1758 MSARegister ws, MSARegister wd); 1759 1760 void GenInstrMsaVec(SecondaryField operation, MSARegister wt, MSARegister ws, 1761 MSARegister wd); 1762 1763 void GenInstrMsaMI10(SecondaryField operation, int32_t s10, Register rs, 1764 MSARegister wd); 1765 1766 void GenInstrMsa2R(SecondaryField operation, SecondaryField df, 1767 MSARegister ws, MSARegister wd); 1768 1769 void GenInstrMsa2RF(SecondaryField operation, SecondaryField df, 1770 MSARegister ws, MSARegister wd); 1771 1772 void GenInstrMsaBranch(SecondaryField operation, MSARegister wt, 1773 int32_t offset16); 1774 is_valid_msa_df_m(SecondaryField bit_df,uint32_t m)1775 inline bool is_valid_msa_df_m(SecondaryField bit_df, uint32_t m) { 1776 switch (bit_df) { 1777 case BIT_DF_b: 1778 return is_uint3(m); 1779 case BIT_DF_h: 1780 return is_uint4(m); 1781 case BIT_DF_w: 1782 return is_uint5(m); 1783 case BIT_DF_d: 1784 return is_uint6(m); 1785 default: 1786 return false; 1787 } 1788 } 1789 is_valid_msa_df_n(SecondaryField elm_df,uint32_t n)1790 inline bool is_valid_msa_df_n(SecondaryField elm_df, uint32_t n) { 1791 switch (elm_df) { 1792 case ELM_DF_B: 1793 return is_uint4(n); 1794 case ELM_DF_H: 1795 return is_uint3(n); 1796 case ELM_DF_W: 1797 return is_uint2(n); 1798 case ELM_DF_D: 1799 return is_uint1(n); 1800 default: 1801 return false; 1802 } 1803 } 1804 1805 // Labels. 1806 void print(const Label* L); 1807 void bind_to(Label* L, int pos); 1808 void next(Label* L, bool is_internal); 1809 1810 // Patching lui/ori pair which is commonly used for loading constants. 1811 static void PatchLuiOriImmediate(Address pc, int32_t imm, Instr instr1, 1812 Address offset_lui, Instr instr2, 1813 Address offset_ori); 1814 void PatchLuiOriImmediate(int pc, int32_t imm, Instr instr1, 1815 Address offset_lui, Instr instr2, 1816 Address offset_ori); 1817 1818 // One trampoline consists of: 1819 // - space for trampoline slots, 1820 // - space for labels. 1821 // 1822 // Space for trampoline slots is equal to slot_count * 2 * kInstrSize. 1823 // Space for trampoline slots precedes space for labels. Each label is of one 1824 // instruction size, so total amount for labels is equal to 1825 // label_count * kInstrSize. 1826 class Trampoline { 1827 public: Trampoline()1828 Trampoline() { 1829 start_ = 0; 1830 next_slot_ = 0; 1831 free_slot_count_ = 0; 1832 end_ = 0; 1833 } Trampoline(int start,int slot_count)1834 Trampoline(int start, int slot_count) { 1835 start_ = start; 1836 next_slot_ = start; 1837 free_slot_count_ = slot_count; 1838 end_ = start + slot_count * kTrampolineSlotsSize; 1839 } start()1840 int start() { return start_; } end()1841 int end() { return end_; } take_slot()1842 int take_slot() { 1843 int trampoline_slot = kInvalidSlotPos; 1844 if (free_slot_count_ <= 0) { 1845 // We have run out of space on trampolines. 1846 // Make sure we fail in debug mode, so we become aware of each case 1847 // when this happens. 1848 DCHECK(0); 1849 // Internal exception will be caught. 1850 } else { 1851 trampoline_slot = next_slot_; 1852 free_slot_count_--; 1853 next_slot_ += kTrampolineSlotsSize; 1854 } 1855 return trampoline_slot; 1856 } 1857 1858 private: 1859 int start_; 1860 int end_; 1861 int next_slot_; 1862 int free_slot_count_; 1863 }; 1864 1865 int32_t get_trampoline_entry(int32_t pos); 1866 int unbound_labels_count_; 1867 // If trampoline is emitted, generated code is becoming large. As this is 1868 // already a slow case which can possibly break our code generation for the 1869 // extreme case, we use this information to trigger different mode of 1870 // branch instruction generation, where we use jump instructions rather 1871 // than regular branch instructions. 1872 bool trampoline_emitted_; 1873 static constexpr int kInvalidSlotPos = -1; 1874 1875 // Internal reference positions, required for unbounded internal reference 1876 // labels. 1877 std::set<int> internal_reference_positions_; is_internal_reference(Label * L)1878 bool is_internal_reference(Label* L) { 1879 return internal_reference_positions_.find(L->pos()) != 1880 internal_reference_positions_.end(); 1881 } 1882 EmittedCompactBranchInstruction()1883 void EmittedCompactBranchInstruction() { prev_instr_compact_branch_ = true; } ClearCompactBranchState()1884 void ClearCompactBranchState() { prev_instr_compact_branch_ = false; } 1885 bool prev_instr_compact_branch_ = false; 1886 1887 Trampoline trampoline_; 1888 bool internal_trampoline_exception_; 1889 1890 // Keep track of the last Call's position to ensure that safepoint can get the 1891 // correct information even if there is a trampoline immediately after the 1892 // Call. 1893 byte* last_call_pc_; 1894 1895 private: 1896 void AllocateAndInstallRequestedHeapObjects(Isolate* isolate); 1897 1898 int WriteCodeComments(); 1899 1900 friend class RegExpMacroAssemblerMIPS; 1901 friend class RelocInfo; 1902 friend class BlockTrampolinePoolScope; 1903 friend class EnsureSpace; 1904 }; 1905 1906 class EnsureSpace { 1907 public: 1908 explicit inline EnsureSpace(Assembler* assembler); 1909 }; 1910 1911 class V8_EXPORT_PRIVATE UseScratchRegisterScope { 1912 public: 1913 explicit UseScratchRegisterScope(Assembler* assembler); 1914 ~UseScratchRegisterScope(); 1915 1916 Register Acquire(); 1917 bool hasAvailable() const; 1918 1919 private: 1920 RegList* available_; 1921 RegList old_available_; 1922 }; 1923 1924 } // namespace internal 1925 } // namespace v8 1926 1927 #endif // V8_CODEGEN_MIPS_ASSEMBLER_MIPS_H_ 1928