1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 2 // All Rights Reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are 6 // met: 7 // 8 // - Redistributions of source code must retain the above copyright notice, 9 // this list of conditions and the following disclaimer. 10 // 11 // - Redistribution in binary form must reproduce the above copyright 12 // notice, this list of conditions and the following disclaimer in the 13 // documentation and/or other materials provided with the distribution. 14 // 15 // - Neither the name of Sun Microsystems or the names of contributors may 16 // be used to endorse or promote products derived from this software without 17 // specific prior written permission. 18 // 19 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 20 // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 23 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 26 // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 27 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 31 // The original source code covered by the above license above has been 32 // modified significantly by Google Inc. 33 // Copyright 2012 the V8 project authors. All rights reserved. 34 35 #ifndef V8_CODEGEN_MIPS64_ASSEMBLER_MIPS64_H_ 36 #define V8_CODEGEN_MIPS64_ASSEMBLER_MIPS64_H_ 37 38 #include <stdio.h> 39 #include <memory> 40 #include <set> 41 42 #include "src/codegen/assembler.h" 43 #include "src/codegen/external-reference.h" 44 #include "src/codegen/label.h" 45 #include "src/codegen/mips64/constants-mips64.h" 46 #include "src/codegen/mips64/register-mips64.h" 47 #include "src/objects/contexts.h" 48 #include "src/objects/smi.h" 49 50 namespace v8 { 51 namespace internal { 52 53 class SafepointTableBuilder; 54 55 // ----------------------------------------------------------------------------- 56 // Machine instruction Operands. 57 constexpr int kSmiShift = kSmiTagSize + kSmiShiftSize; 58 constexpr uint64_t kSmiShiftMask = (1UL << kSmiShift) - 1; 59 // Class Operand represents a shifter operand in data processing instructions. 60 class Operand { 61 public: 62 // Immediate. 63 V8_INLINE explicit Operand(int64_t immediate, 64 RelocInfo::Mode rmode = RelocInfo::NONE) rm_(no_reg)65 : rm_(no_reg), rmode_(rmode) { 66 value_.immediate = immediate; 67 } Operand(const ExternalReference & f)68 V8_INLINE explicit Operand(const ExternalReference& f) 69 : rm_(no_reg), rmode_(RelocInfo::EXTERNAL_REFERENCE) { 70 value_.immediate = static_cast<int64_t>(f.address()); 71 } 72 V8_INLINE explicit Operand(const char* s); 73 explicit Operand(Handle<HeapObject> handle); Operand(Smi value)74 V8_INLINE explicit Operand(Smi value) : rm_(no_reg), rmode_(RelocInfo::NONE) { 75 value_.immediate = static_cast<intptr_t>(value.ptr()); 76 } 77 78 static Operand EmbeddedNumber(double number); // Smi or HeapNumber. 79 static Operand EmbeddedStringConstant(const StringConstantBase* str); 80 81 // Register. Operand(Register rm)82 V8_INLINE explicit Operand(Register rm) : rm_(rm) {} 83 84 // Return true if this is a register operand. 85 V8_INLINE bool is_reg() const; 86 87 inline int64_t immediate() const; 88 IsImmediate()89 bool IsImmediate() const { return !rm_.is_valid(); } 90 heap_object_request()91 HeapObjectRequest heap_object_request() const { 92 DCHECK(IsHeapObjectRequest()); 93 return value_.heap_object_request; 94 } 95 IsHeapObjectRequest()96 bool IsHeapObjectRequest() const { 97 DCHECK_IMPLIES(is_heap_object_request_, IsImmediate()); 98 DCHECK_IMPLIES(is_heap_object_request_, 99 rmode_ == RelocInfo::FULL_EMBEDDED_OBJECT || 100 rmode_ == RelocInfo::CODE_TARGET); 101 return is_heap_object_request_; 102 } 103 rm()104 Register rm() const { return rm_; } 105 rmode()106 RelocInfo::Mode rmode() const { return rmode_; } 107 108 private: 109 Register rm_; 110 union Value { Value()111 Value() {} 112 HeapObjectRequest heap_object_request; // if is_heap_object_request_ 113 int64_t immediate; // otherwise 114 } value_; // valid if rm_ == no_reg 115 bool is_heap_object_request_ = false; 116 RelocInfo::Mode rmode_; 117 118 friend class Assembler; 119 friend class MacroAssembler; 120 }; 121 122 // On MIPS we have only one addressing mode with base_reg + offset. 123 // Class MemOperand represents a memory operand in load and store instructions. 124 class V8_EXPORT_PRIVATE MemOperand : public Operand { 125 public: 126 // Immediate value attached to offset. 127 enum OffsetAddend { offset_minus_one = -1, offset_zero = 0 }; 128 129 explicit MemOperand(Register rn, int32_t offset = 0); 130 explicit MemOperand(Register rn, int32_t unit, int32_t multiplier, 131 OffsetAddend offset_addend = offset_zero); offset()132 int32_t offset() const { return offset_; } 133 OffsetIsInt16Encodable()134 bool OffsetIsInt16Encodable() const { return is_int16(offset_); } 135 136 private: 137 int32_t offset_; 138 139 friend class Assembler; 140 }; 141 142 class V8_EXPORT_PRIVATE Assembler : public AssemblerBase { 143 public: 144 // Create an assembler. Instructions and relocation information are emitted 145 // into a buffer, with the instructions starting from the beginning and the 146 // relocation information starting from the end of the buffer. See CodeDesc 147 // for a detailed comment on the layout (globals.h). 148 // 149 // If the provided buffer is nullptr, the assembler allocates and grows its 150 // own buffer. Otherwise it takes ownership of the provided buffer. 151 explicit Assembler(const AssemblerOptions&, 152 std::unique_ptr<AssemblerBuffer> = {}); 153 ~Assembler()154 virtual ~Assembler() {} 155 156 // GetCode emits any pending (non-emitted) code and fills the descriptor desc. 157 static constexpr int kNoHandlerTable = 0; 158 static constexpr SafepointTableBuilder* kNoSafepointTable = nullptr; 159 void GetCode(Isolate* isolate, CodeDesc* desc, 160 SafepointTableBuilder* safepoint_table_builder, 161 int handler_table_offset); 162 163 // Convenience wrapper for code without safepoint or handler tables. GetCode(Isolate * isolate,CodeDesc * desc)164 void GetCode(Isolate* isolate, CodeDesc* desc) { 165 GetCode(isolate, desc, kNoSafepointTable, kNoHandlerTable); 166 } 167 168 // Unused on this architecture. MaybeEmitOutOfLineConstantPool()169 void MaybeEmitOutOfLineConstantPool() {} 170 171 // Mips uses BlockTrampolinePool to prevent generating trampoline inside a 172 // continuous instruction block. For Call instruction, it prevents generating 173 // trampoline between jalr and delay slot instruction. In the destructor of 174 // BlockTrampolinePool, it must check if it needs to generate trampoline 175 // immediately, if it does not do this, the branch range will go beyond the 176 // max branch offset, that means the pc_offset after call CheckTrampolinePool 177 // may be not the Call instruction's location. So we use last_call_pc here for 178 // safepoint record. pc_offset_for_safepoint()179 int pc_offset_for_safepoint() { 180 #ifdef DEBUG 181 Instr instr1 = 182 instr_at(static_cast<int>(last_call_pc_ - buffer_start_ - kInstrSize)); 183 Instr instr2 = instr_at( 184 static_cast<int>(last_call_pc_ - buffer_start_ - kInstrSize * 2)); 185 if (GetOpcodeField(instr1) != SPECIAL) { // instr1 == jialc. 186 DCHECK((kArchVariant == kMips64r6) && GetOpcodeField(instr1) == POP76 && 187 GetRs(instr1) == 0); 188 } else { 189 if (GetFunctionField(instr1) == SLL) { // instr1 == nop, instr2 == jalr. 190 DCHECK(GetOpcodeField(instr2) == SPECIAL && 191 GetFunctionField(instr2) == JALR); 192 } else { // instr1 == jalr. 193 DCHECK(GetFunctionField(instr1) == JALR); 194 } 195 } 196 #endif 197 return static_cast<int>(last_call_pc_ - buffer_start_); 198 } 199 200 // Label operations & relative jumps (PPUM Appendix D). 201 // 202 // Takes a branch opcode (cc) and a label (L) and generates 203 // either a backward branch or a forward branch and links it 204 // to the label fixup chain. Usage: 205 // 206 // Label L; // unbound label 207 // j(cc, &L); // forward branch to unbound label 208 // bind(&L); // bind label to the current pc 209 // j(cc, &L); // backward branch to bound label 210 // bind(&L); // illegal: a label may be bound only once 211 // 212 // Note: The same Label can be used for forward and backward branches 213 // but it may be bound only once. 214 void bind(Label* L); // Binds an unbound label L to current code position. 215 216 enum OffsetSize : int { kOffset26 = 26, kOffset21 = 21, kOffset16 = 16 }; 217 218 // Determines if Label is bound and near enough so that branch instruction 219 // can be used to reach it, instead of jump instruction. 220 bool is_near(Label* L); 221 bool is_near(Label* L, OffsetSize bits); 222 bool is_near_branch(Label* L); is_near_pre_r6(Label * L)223 inline bool is_near_pre_r6(Label* L) { 224 DCHECK(!(kArchVariant == kMips64r6)); 225 return pc_offset() - L->pos() < kMaxBranchOffset - 4 * kInstrSize; 226 } is_near_r6(Label * L)227 inline bool is_near_r6(Label* L) { 228 DCHECK_EQ(kArchVariant, kMips64r6); 229 return pc_offset() - L->pos() < kMaxCompactBranchOffset - 4 * kInstrSize; 230 } 231 232 int BranchOffset(Instr instr); 233 234 // Returns the branch offset to the given label from the current code 235 // position. Links the label to the current position if it is still unbound. 236 // Manages the jump elimination optimization if the second parameter is true. 237 int32_t branch_offset_helper(Label* L, OffsetSize bits); branch_offset(Label * L)238 inline int32_t branch_offset(Label* L) { 239 return branch_offset_helper(L, OffsetSize::kOffset16); 240 } branch_offset21(Label * L)241 inline int32_t branch_offset21(Label* L) { 242 return branch_offset_helper(L, OffsetSize::kOffset21); 243 } branch_offset26(Label * L)244 inline int32_t branch_offset26(Label* L) { 245 return branch_offset_helper(L, OffsetSize::kOffset26); 246 } shifted_branch_offset(Label * L)247 inline int32_t shifted_branch_offset(Label* L) { 248 return branch_offset(L) >> 2; 249 } shifted_branch_offset21(Label * L)250 inline int32_t shifted_branch_offset21(Label* L) { 251 return branch_offset21(L) >> 2; 252 } shifted_branch_offset26(Label * L)253 inline int32_t shifted_branch_offset26(Label* L) { 254 return branch_offset26(L) >> 2; 255 } 256 uint64_t jump_address(Label* L); 257 uint64_t jump_offset(Label* L); 258 uint64_t branch_long_offset(Label* L); 259 260 // Puts a labels target address at the given position. 261 // The high 8 bits are set to zero. 262 void label_at_put(Label* L, int at_offset); 263 264 // Read/Modify the code target address in the branch/call instruction at pc. 265 // The isolate argument is unused (and may be nullptr) when skipping flushing. 266 static Address target_address_at(Address pc); 267 V8_INLINE static void set_target_address_at( 268 Address pc, Address target, 269 ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED) { 270 set_target_value_at(pc, target, icache_flush_mode); 271 } 272 // On MIPS there is no Constant Pool so we skip that parameter. target_address_at(Address pc,Address constant_pool)273 V8_INLINE static Address target_address_at(Address pc, 274 Address constant_pool) { 275 return target_address_at(pc); 276 } 277 V8_INLINE static void set_target_address_at( 278 Address pc, Address constant_pool, Address target, 279 ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED) { 280 set_target_address_at(pc, target, icache_flush_mode); 281 } 282 283 static void set_target_value_at( 284 Address pc, uint64_t target, 285 ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED); 286 287 static void JumpLabelToJumpRegister(Address pc); 288 289 // This sets the branch destination (which gets loaded at the call address). 290 // This is for calls and branches within generated code. The serializer 291 // has already deserialized the lui/ori instructions etc. 292 inline static void deserialization_set_special_target_at( 293 Address instruction_payload, Code code, Address target); 294 295 // Get the size of the special target encoded at 'instruction_payload'. 296 inline static int deserialization_special_target_size( 297 Address instruction_payload); 298 299 // This sets the internal reference at the pc. 300 inline static void deserialization_set_target_internal_reference_at( 301 Address pc, Address target, 302 RelocInfo::Mode mode = RelocInfo::INTERNAL_REFERENCE); 303 304 // Difference between address of current opcode and target address offset. 305 static constexpr int kBranchPCOffset = kInstrSize; 306 307 // Difference between address of current opcode and target address offset, 308 // when we are generatinga sequence of instructions for long relative PC 309 // branches 310 static constexpr int kLongBranchPCOffset = 3 * kInstrSize; 311 312 // Adjust ra register in branch delay slot of bal instruction so to skip 313 // instructions not needed after optimization of PIC in 314 // TurboAssembler::BranchAndLink method. 315 316 static constexpr int kOptimizedBranchAndLinkLongReturnOffset = 4 * kInstrSize; 317 318 // Here we are patching the address in the LUI/ORI instruction pair. 319 // These values are used in the serialization process and must be zero for 320 // MIPS platform, as Code, Embedded Object or External-reference pointers 321 // are split across two consecutive instructions and don't exist separately 322 // in the code, so the serializer should not step forwards in memory after 323 // a target is resolved and written. 324 static constexpr int kSpecialTargetSize = 0; 325 326 // Number of consecutive instructions used to store 32bit/64bit constant. 327 // This constant was used in RelocInfo::target_address_address() function 328 // to tell serializer address of the instruction that follows 329 // LUI/ORI instruction pair. 330 static constexpr int kInstructionsFor32BitConstant = 2; 331 static constexpr int kInstructionsFor64BitConstant = 4; 332 333 // Difference between address of current opcode and value read from pc 334 // register. 335 static constexpr int kPcLoadDelta = 4; 336 337 // Max offset for instructions with 16-bit offset field 338 static constexpr int kMaxBranchOffset = (1 << (18 - 1)) - 1; 339 340 // Max offset for compact branch instructions with 26-bit offset field 341 static constexpr int kMaxCompactBranchOffset = (1 << (28 - 1)) - 1; 342 343 static constexpr int kTrampolineSlotsSize = 344 kArchVariant == kMips64r6 ? 2 * kInstrSize : 7 * kInstrSize; 345 GetScratchRegisterList()346 RegList* GetScratchRegisterList() { return &scratch_register_list_; } 347 348 // --------------------------------------------------------------------------- 349 // Code generation. 350 351 // Insert the smallest number of nop instructions 352 // possible to align the pc offset to a multiple 353 // of m. m must be a power of 2 (>= 4). 354 void Align(int m); 355 // Insert the smallest number of zero bytes possible to align the pc offset 356 // to a mulitple of m. m must be a power of 2 (>= 2). 357 void DataAlign(int m); 358 // Aligns code to something that's optimal for a jump target for the platform. 359 void CodeTargetAlign(); 360 361 // Different nop operations are used by the code generator to detect certain 362 // states of the generated code. 363 enum NopMarkerTypes { 364 NON_MARKING_NOP = 0, 365 DEBUG_BREAK_NOP, 366 // IC markers. 367 PROPERTY_ACCESS_INLINED, 368 PROPERTY_ACCESS_INLINED_CONTEXT, 369 PROPERTY_ACCESS_INLINED_CONTEXT_DONT_DELETE, 370 // Helper values. 371 LAST_CODE_MARKER, 372 FIRST_IC_MARKER = PROPERTY_ACCESS_INLINED, 373 }; 374 375 // Type == 0 is the default non-marking nop. For mips this is a 376 // sll(zero_reg, zero_reg, 0). We use rt_reg == at for non-zero 377 // marking, to avoid conflict with ssnop and ehb instructions. 378 void nop(unsigned int type = 0) { 379 DCHECK_LT(type, 32); 380 Register nop_rt_reg = (type == 0) ? zero_reg : at; 381 sll(zero_reg, nop_rt_reg, type, true); 382 } 383 384 // --------Branch-and-jump-instructions---------- 385 // We don't use likely variant of instructions. 386 void b(int16_t offset); b(Label * L)387 inline void b(Label* L) { b(shifted_branch_offset(L)); } 388 void bal(int16_t offset); bal(Label * L)389 inline void bal(Label* L) { bal(shifted_branch_offset(L)); } 390 void bc(int32_t offset); bc(Label * L)391 inline void bc(Label* L) { bc(shifted_branch_offset26(L)); } 392 void balc(int32_t offset); balc(Label * L)393 inline void balc(Label* L) { balc(shifted_branch_offset26(L)); } 394 395 void beq(Register rs, Register rt, int16_t offset); beq(Register rs,Register rt,Label * L)396 inline void beq(Register rs, Register rt, Label* L) { 397 beq(rs, rt, shifted_branch_offset(L)); 398 } 399 void bgez(Register rs, int16_t offset); 400 void bgezc(Register rt, int16_t offset); bgezc(Register rt,Label * L)401 inline void bgezc(Register rt, Label* L) { 402 bgezc(rt, shifted_branch_offset(L)); 403 } 404 void bgeuc(Register rs, Register rt, int16_t offset); bgeuc(Register rs,Register rt,Label * L)405 inline void bgeuc(Register rs, Register rt, Label* L) { 406 bgeuc(rs, rt, shifted_branch_offset(L)); 407 } 408 void bgec(Register rs, Register rt, int16_t offset); bgec(Register rs,Register rt,Label * L)409 inline void bgec(Register rs, Register rt, Label* L) { 410 bgec(rs, rt, shifted_branch_offset(L)); 411 } 412 void bgezal(Register rs, int16_t offset); 413 void bgezalc(Register rt, int16_t offset); bgezalc(Register rt,Label * L)414 inline void bgezalc(Register rt, Label* L) { 415 bgezalc(rt, shifted_branch_offset(L)); 416 } 417 void bgezall(Register rs, int16_t offset); bgezall(Register rs,Label * L)418 inline void bgezall(Register rs, Label* L) { 419 bgezall(rs, branch_offset(L) >> 2); 420 } 421 void bgtz(Register rs, int16_t offset); 422 void bgtzc(Register rt, int16_t offset); bgtzc(Register rt,Label * L)423 inline void bgtzc(Register rt, Label* L) { 424 bgtzc(rt, shifted_branch_offset(L)); 425 } 426 void blez(Register rs, int16_t offset); 427 void blezc(Register rt, int16_t offset); blezc(Register rt,Label * L)428 inline void blezc(Register rt, Label* L) { 429 blezc(rt, shifted_branch_offset(L)); 430 } 431 void bltz(Register rs, int16_t offset); 432 void bltzc(Register rt, int16_t offset); bltzc(Register rt,Label * L)433 inline void bltzc(Register rt, Label* L) { 434 bltzc(rt, shifted_branch_offset(L)); 435 } 436 void bltuc(Register rs, Register rt, int16_t offset); bltuc(Register rs,Register rt,Label * L)437 inline void bltuc(Register rs, Register rt, Label* L) { 438 bltuc(rs, rt, shifted_branch_offset(L)); 439 } 440 void bltc(Register rs, Register rt, int16_t offset); bltc(Register rs,Register rt,Label * L)441 inline void bltc(Register rs, Register rt, Label* L) { 442 bltc(rs, rt, shifted_branch_offset(L)); 443 } 444 void bltzal(Register rs, int16_t offset); nal()445 void nal() { bltzal(zero_reg, 0); } 446 void blezalc(Register rt, int16_t offset); blezalc(Register rt,Label * L)447 inline void blezalc(Register rt, Label* L) { 448 blezalc(rt, shifted_branch_offset(L)); 449 } 450 void bltzalc(Register rt, int16_t offset); bltzalc(Register rt,Label * L)451 inline void bltzalc(Register rt, Label* L) { 452 bltzalc(rt, shifted_branch_offset(L)); 453 } 454 void bgtzalc(Register rt, int16_t offset); bgtzalc(Register rt,Label * L)455 inline void bgtzalc(Register rt, Label* L) { 456 bgtzalc(rt, shifted_branch_offset(L)); 457 } 458 void beqzalc(Register rt, int16_t offset); beqzalc(Register rt,Label * L)459 inline void beqzalc(Register rt, Label* L) { 460 beqzalc(rt, shifted_branch_offset(L)); 461 } 462 void beqc(Register rs, Register rt, int16_t offset); beqc(Register rs,Register rt,Label * L)463 inline void beqc(Register rs, Register rt, Label* L) { 464 beqc(rs, rt, shifted_branch_offset(L)); 465 } 466 void beqzc(Register rs, int32_t offset); beqzc(Register rs,Label * L)467 inline void beqzc(Register rs, Label* L) { 468 beqzc(rs, shifted_branch_offset21(L)); 469 } 470 void bnezalc(Register rt, int16_t offset); bnezalc(Register rt,Label * L)471 inline void bnezalc(Register rt, Label* L) { 472 bnezalc(rt, shifted_branch_offset(L)); 473 } 474 void bnec(Register rs, Register rt, int16_t offset); bnec(Register rs,Register rt,Label * L)475 inline void bnec(Register rs, Register rt, Label* L) { 476 bnec(rs, rt, shifted_branch_offset(L)); 477 } 478 void bnezc(Register rt, int32_t offset); bnezc(Register rt,Label * L)479 inline void bnezc(Register rt, Label* L) { 480 bnezc(rt, shifted_branch_offset21(L)); 481 } 482 void bne(Register rs, Register rt, int16_t offset); bne(Register rs,Register rt,Label * L)483 inline void bne(Register rs, Register rt, Label* L) { 484 bne(rs, rt, shifted_branch_offset(L)); 485 } 486 void bovc(Register rs, Register rt, int16_t offset); bovc(Register rs,Register rt,Label * L)487 inline void bovc(Register rs, Register rt, Label* L) { 488 bovc(rs, rt, shifted_branch_offset(L)); 489 } 490 void bnvc(Register rs, Register rt, int16_t offset); bnvc(Register rs,Register rt,Label * L)491 inline void bnvc(Register rs, Register rt, Label* L) { 492 bnvc(rs, rt, shifted_branch_offset(L)); 493 } 494 495 // Never use the int16_t b(l)cond version with a branch offset 496 // instead of using the Label* version. 497 498 void jalr(Register rs, Register rd = ra); 499 void jr(Register target); 500 void jic(Register rt, int16_t offset); 501 void jialc(Register rt, int16_t offset); 502 503 // Following instructions are deprecated and require 256 MB 504 // code alignment. Use PC-relative instructions instead. 505 void j(int64_t target); 506 void jal(int64_t target); 507 void j(Label* target); 508 void jal(Label* target); 509 510 // -------Data-processing-instructions--------- 511 512 // Arithmetic. 513 void addu(Register rd, Register rs, Register rt); 514 void subu(Register rd, Register rs, Register rt); 515 516 void div(Register rs, Register rt); 517 void divu(Register rs, Register rt); 518 void ddiv(Register rs, Register rt); 519 void ddivu(Register rs, Register rt); 520 void div(Register rd, Register rs, Register rt); 521 void divu(Register rd, Register rs, Register rt); 522 void ddiv(Register rd, Register rs, Register rt); 523 void ddivu(Register rd, Register rs, Register rt); 524 void mod(Register rd, Register rs, Register rt); 525 void modu(Register rd, Register rs, Register rt); 526 void dmod(Register rd, Register rs, Register rt); 527 void dmodu(Register rd, Register rs, Register rt); 528 529 void mul(Register rd, Register rs, Register rt); 530 void muh(Register rd, Register rs, Register rt); 531 void mulu(Register rd, Register rs, Register rt); 532 void muhu(Register rd, Register rs, Register rt); 533 void mult(Register rs, Register rt); 534 void multu(Register rs, Register rt); 535 void dmul(Register rd, Register rs, Register rt); 536 void dmuh(Register rd, Register rs, Register rt); 537 void dmulu(Register rd, Register rs, Register rt); 538 void dmuhu(Register rd, Register rs, Register rt); 539 void daddu(Register rd, Register rs, Register rt); 540 void dsubu(Register rd, Register rs, Register rt); 541 void dmult(Register rs, Register rt); 542 void dmultu(Register rs, Register rt); 543 544 void addiu(Register rd, Register rs, int32_t j); 545 void daddiu(Register rd, Register rs, int32_t j); 546 547 // Logical. 548 void and_(Register rd, Register rs, Register rt); 549 void or_(Register rd, Register rs, Register rt); 550 void xor_(Register rd, Register rs, Register rt); 551 void nor(Register rd, Register rs, Register rt); 552 553 void andi(Register rd, Register rs, int32_t j); 554 void ori(Register rd, Register rs, int32_t j); 555 void xori(Register rd, Register rs, int32_t j); 556 void lui(Register rd, int32_t j); 557 void aui(Register rt, Register rs, int32_t j); 558 void daui(Register rt, Register rs, int32_t j); 559 void dahi(Register rs, int32_t j); 560 void dati(Register rs, int32_t j); 561 562 // Shifts. 563 // Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop 564 // and may cause problems in normal code. coming_from_nop makes sure this 565 // doesn't happen. 566 void sll(Register rd, Register rt, uint16_t sa, bool coming_from_nop = false); 567 void sllv(Register rd, Register rt, Register rs); 568 void srl(Register rd, Register rt, uint16_t sa); 569 void srlv(Register rd, Register rt, Register rs); 570 void sra(Register rt, Register rd, uint16_t sa); 571 void srav(Register rt, Register rd, Register rs); 572 void rotr(Register rd, Register rt, uint16_t sa); 573 void rotrv(Register rd, Register rt, Register rs); 574 void dsll(Register rd, Register rt, uint16_t sa); 575 void dsllv(Register rd, Register rt, Register rs); 576 void dsrl(Register rd, Register rt, uint16_t sa); 577 void dsrlv(Register rd, Register rt, Register rs); 578 void drotr(Register rd, Register rt, uint16_t sa); 579 void drotr32(Register rd, Register rt, uint16_t sa); 580 void drotrv(Register rd, Register rt, Register rs); 581 void dsra(Register rt, Register rd, uint16_t sa); 582 void dsrav(Register rd, Register rt, Register rs); 583 void dsll32(Register rt, Register rd, uint16_t sa); 584 void dsrl32(Register rt, Register rd, uint16_t sa); 585 void dsra32(Register rt, Register rd, uint16_t sa); 586 587 // ------------Memory-instructions------------- 588 589 void lb(Register rd, const MemOperand& rs); 590 void lbu(Register rd, const MemOperand& rs); 591 void lh(Register rd, const MemOperand& rs); 592 void lhu(Register rd, const MemOperand& rs); 593 void lw(Register rd, const MemOperand& rs); 594 void lwu(Register rd, const MemOperand& rs); 595 void lwl(Register rd, const MemOperand& rs); 596 void lwr(Register rd, const MemOperand& rs); 597 void sb(Register rd, const MemOperand& rs); 598 void sh(Register rd, const MemOperand& rs); 599 void sw(Register rd, const MemOperand& rs); 600 void swl(Register rd, const MemOperand& rs); 601 void swr(Register rd, const MemOperand& rs); 602 void ldl(Register rd, const MemOperand& rs); 603 void ldr(Register rd, const MemOperand& rs); 604 void sdl(Register rd, const MemOperand& rs); 605 void sdr(Register rd, const MemOperand& rs); 606 void ld(Register rd, const MemOperand& rs); 607 void sd(Register rd, const MemOperand& rs); 608 609 // ----------Atomic instructions-------------- 610 611 void ll(Register rd, const MemOperand& rs); 612 void sc(Register rd, const MemOperand& rs); 613 void lld(Register rd, const MemOperand& rs); 614 void scd(Register rd, const MemOperand& rs); 615 616 // ---------PC-Relative-instructions----------- 617 618 void addiupc(Register rs, int32_t imm19); 619 void lwpc(Register rs, int32_t offset19); 620 void lwupc(Register rs, int32_t offset19); 621 void ldpc(Register rs, int32_t offset18); 622 void auipc(Register rs, int16_t imm16); 623 void aluipc(Register rs, int16_t imm16); 624 625 // ----------------Prefetch-------------------- 626 627 void pref(int32_t hint, const MemOperand& rs); 628 629 // -------------Misc-instructions-------------- 630 631 // Break / Trap instructions. 632 void break_(uint32_t code, bool break_as_stop = false); 633 void stop(uint32_t code = kMaxStopCode); 634 void tge(Register rs, Register rt, uint16_t code); 635 void tgeu(Register rs, Register rt, uint16_t code); 636 void tlt(Register rs, Register rt, uint16_t code); 637 void tltu(Register rs, Register rt, uint16_t code); 638 void teq(Register rs, Register rt, uint16_t code); 639 void tne(Register rs, Register rt, uint16_t code); 640 641 // Memory barrier instruction. 642 void sync(); 643 644 // Move from HI/LO register. 645 void mfhi(Register rd); 646 void mflo(Register rd); 647 648 // Set on less than. 649 void slt(Register rd, Register rs, Register rt); 650 void sltu(Register rd, Register rs, Register rt); 651 void slti(Register rd, Register rs, int32_t j); 652 void sltiu(Register rd, Register rs, int32_t j); 653 654 // Conditional move. 655 void movz(Register rd, Register rs, Register rt); 656 void movn(Register rd, Register rs, Register rt); 657 void movt(Register rd, Register rs, uint16_t cc = 0); 658 void movf(Register rd, Register rs, uint16_t cc = 0); 659 660 void sel(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 661 void sel_s(FPURegister fd, FPURegister fs, FPURegister ft); 662 void sel_d(FPURegister fd, FPURegister fs, FPURegister ft); 663 void seleqz(Register rd, Register rs, Register rt); 664 void seleqz(SecondaryField fmt, FPURegister fd, FPURegister fs, 665 FPURegister ft); 666 void selnez(Register rs, Register rt, Register rd); 667 void selnez(SecondaryField fmt, FPURegister fd, FPURegister fs, 668 FPURegister ft); 669 void seleqz_d(FPURegister fd, FPURegister fs, FPURegister ft); 670 void seleqz_s(FPURegister fd, FPURegister fs, FPURegister ft); 671 void selnez_d(FPURegister fd, FPURegister fs, FPURegister ft); 672 void selnez_s(FPURegister fd, FPURegister fs, FPURegister ft); 673 674 void movz_s(FPURegister fd, FPURegister fs, Register rt); 675 void movz_d(FPURegister fd, FPURegister fs, Register rt); 676 void movt_s(FPURegister fd, FPURegister fs, uint16_t cc = 0); 677 void movt_d(FPURegister fd, FPURegister fs, uint16_t cc = 0); 678 void movf_s(FPURegister fd, FPURegister fs, uint16_t cc = 0); 679 void movf_d(FPURegister fd, FPURegister fs, uint16_t cc = 0); 680 void movn_s(FPURegister fd, FPURegister fs, Register rt); 681 void movn_d(FPURegister fd, FPURegister fs, Register rt); 682 // Bit twiddling. 683 void clz(Register rd, Register rs); 684 void dclz(Register rd, Register rs); 685 void ins_(Register rt, Register rs, uint16_t pos, uint16_t size); 686 void ext_(Register rt, Register rs, uint16_t pos, uint16_t size); 687 void dext_(Register rt, Register rs, uint16_t pos, uint16_t size); 688 void dextm_(Register rt, Register rs, uint16_t pos, uint16_t size); 689 void dextu_(Register rt, Register rs, uint16_t pos, uint16_t size); 690 void dins_(Register rt, Register rs, uint16_t pos, uint16_t size); 691 void dinsm_(Register rt, Register rs, uint16_t pos, uint16_t size); 692 void dinsu_(Register rt, Register rs, uint16_t pos, uint16_t size); 693 void bitswap(Register rd, Register rt); 694 void dbitswap(Register rd, Register rt); 695 void align(Register rd, Register rs, Register rt, uint8_t bp); 696 void dalign(Register rd, Register rs, Register rt, uint8_t bp); 697 698 void wsbh(Register rd, Register rt); 699 void dsbh(Register rd, Register rt); 700 void dshd(Register rd, Register rt); 701 void seh(Register rd, Register rt); 702 void seb(Register rd, Register rt); 703 704 // --------Coprocessor-instructions---------------- 705 706 // Load, store, and move. 707 void lwc1(FPURegister fd, const MemOperand& src); 708 void ldc1(FPURegister fd, const MemOperand& src); 709 710 void swc1(FPURegister fs, const MemOperand& dst); 711 void sdc1(FPURegister fs, const MemOperand& dst); 712 713 void mtc1(Register rt, FPURegister fs); 714 void mthc1(Register rt, FPURegister fs); 715 void dmtc1(Register rt, FPURegister fs); 716 717 void mfc1(Register rt, FPURegister fs); 718 void mfhc1(Register rt, FPURegister fs); 719 void dmfc1(Register rt, FPURegister fs); 720 721 void ctc1(Register rt, FPUControlRegister fs); 722 void cfc1(Register rt, FPUControlRegister fs); 723 724 // Arithmetic. 725 void add_s(FPURegister fd, FPURegister fs, FPURegister ft); 726 void add_d(FPURegister fd, FPURegister fs, FPURegister ft); 727 void sub_s(FPURegister fd, FPURegister fs, FPURegister ft); 728 void sub_d(FPURegister fd, FPURegister fs, FPURegister ft); 729 void mul_s(FPURegister fd, FPURegister fs, FPURegister ft); 730 void mul_d(FPURegister fd, FPURegister fs, FPURegister ft); 731 void madd_s(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 732 void madd_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 733 void msub_s(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 734 void msub_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); 735 void maddf_s(FPURegister fd, FPURegister fs, FPURegister ft); 736 void maddf_d(FPURegister fd, FPURegister fs, FPURegister ft); 737 void msubf_s(FPURegister fd, FPURegister fs, FPURegister ft); 738 void msubf_d(FPURegister fd, FPURegister fs, FPURegister ft); 739 void div_s(FPURegister fd, FPURegister fs, FPURegister ft); 740 void div_d(FPURegister fd, FPURegister fs, FPURegister ft); 741 void abs_s(FPURegister fd, FPURegister fs); 742 void abs_d(FPURegister fd, FPURegister fs); 743 void mov_d(FPURegister fd, FPURegister fs); 744 void mov_s(FPURegister fd, FPURegister fs); 745 void neg_s(FPURegister fd, FPURegister fs); 746 void neg_d(FPURegister fd, FPURegister fs); 747 void sqrt_s(FPURegister fd, FPURegister fs); 748 void sqrt_d(FPURegister fd, FPURegister fs); 749 void rsqrt_s(FPURegister fd, FPURegister fs); 750 void rsqrt_d(FPURegister fd, FPURegister fs); 751 void recip_d(FPURegister fd, FPURegister fs); 752 void recip_s(FPURegister fd, FPURegister fs); 753 754 // Conversion. 755 void cvt_w_s(FPURegister fd, FPURegister fs); 756 void cvt_w_d(FPURegister fd, FPURegister fs); 757 void trunc_w_s(FPURegister fd, FPURegister fs); 758 void trunc_w_d(FPURegister fd, FPURegister fs); 759 void round_w_s(FPURegister fd, FPURegister fs); 760 void round_w_d(FPURegister fd, FPURegister fs); 761 void floor_w_s(FPURegister fd, FPURegister fs); 762 void floor_w_d(FPURegister fd, FPURegister fs); 763 void ceil_w_s(FPURegister fd, FPURegister fs); 764 void ceil_w_d(FPURegister fd, FPURegister fs); 765 void rint_s(FPURegister fd, FPURegister fs); 766 void rint_d(FPURegister fd, FPURegister fs); 767 void rint(SecondaryField fmt, FPURegister fd, FPURegister fs); 768 769 void cvt_l_s(FPURegister fd, FPURegister fs); 770 void cvt_l_d(FPURegister fd, FPURegister fs); 771 void trunc_l_s(FPURegister fd, FPURegister fs); 772 void trunc_l_d(FPURegister fd, FPURegister fs); 773 void round_l_s(FPURegister fd, FPURegister fs); 774 void round_l_d(FPURegister fd, FPURegister fs); 775 void floor_l_s(FPURegister fd, FPURegister fs); 776 void floor_l_d(FPURegister fd, FPURegister fs); 777 void ceil_l_s(FPURegister fd, FPURegister fs); 778 void ceil_l_d(FPURegister fd, FPURegister fs); 779 780 void class_s(FPURegister fd, FPURegister fs); 781 void class_d(FPURegister fd, FPURegister fs); 782 783 void min(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 784 void mina(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 785 void max(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 786 void maxa(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft); 787 void min_s(FPURegister fd, FPURegister fs, FPURegister ft); 788 void min_d(FPURegister fd, FPURegister fs, FPURegister ft); 789 void max_s(FPURegister fd, FPURegister fs, FPURegister ft); 790 void max_d(FPURegister fd, FPURegister fs, FPURegister ft); 791 void mina_s(FPURegister fd, FPURegister fs, FPURegister ft); 792 void mina_d(FPURegister fd, FPURegister fs, FPURegister ft); 793 void maxa_s(FPURegister fd, FPURegister fs, FPURegister ft); 794 void maxa_d(FPURegister fd, FPURegister fs, FPURegister ft); 795 796 void cvt_s_w(FPURegister fd, FPURegister fs); 797 void cvt_s_l(FPURegister fd, FPURegister fs); 798 void cvt_s_d(FPURegister fd, FPURegister fs); 799 800 void cvt_d_w(FPURegister fd, FPURegister fs); 801 void cvt_d_l(FPURegister fd, FPURegister fs); 802 void cvt_d_s(FPURegister fd, FPURegister fs); 803 804 // Conditions and branches for MIPSr6. 805 void cmp(FPUCondition cond, SecondaryField fmt, FPURegister fd, 806 FPURegister ft, FPURegister fs); 807 void cmp_s(FPUCondition cond, FPURegister fd, FPURegister fs, FPURegister ft); 808 void cmp_d(FPUCondition cond, FPURegister fd, FPURegister fs, FPURegister ft); 809 810 void bc1eqz(int16_t offset, FPURegister ft); bc1eqz(Label * L,FPURegister ft)811 inline void bc1eqz(Label* L, FPURegister ft) { 812 bc1eqz(shifted_branch_offset(L), ft); 813 } 814 void bc1nez(int16_t offset, FPURegister ft); bc1nez(Label * L,FPURegister ft)815 inline void bc1nez(Label* L, FPURegister ft) { 816 bc1nez(shifted_branch_offset(L), ft); 817 } 818 819 // Conditions and branches for non MIPSr6. 820 void c(FPUCondition cond, SecondaryField fmt, FPURegister ft, FPURegister fs, 821 uint16_t cc = 0); 822 void c_s(FPUCondition cond, FPURegister ft, FPURegister fs, uint16_t cc = 0); 823 void c_d(FPUCondition cond, FPURegister ft, FPURegister fs, uint16_t cc = 0); 824 825 void bc1f(int16_t offset, uint16_t cc = 0); 826 inline void bc1f(Label* L, uint16_t cc = 0) { 827 bc1f(shifted_branch_offset(L), cc); 828 } 829 void bc1t(int16_t offset, uint16_t cc = 0); 830 inline void bc1t(Label* L, uint16_t cc = 0) { 831 bc1t(shifted_branch_offset(L), cc); 832 } 833 void fcmp(FPURegister src1, const double src2, FPUCondition cond); 834 835 // MSA instructions 836 void bz_v(MSARegister wt, int16_t offset); bz_v(MSARegister wt,Label * L)837 inline void bz_v(MSARegister wt, Label* L) { 838 bz_v(wt, shifted_branch_offset(L)); 839 } 840 void bz_b(MSARegister wt, int16_t offset); bz_b(MSARegister wt,Label * L)841 inline void bz_b(MSARegister wt, Label* L) { 842 bz_b(wt, shifted_branch_offset(L)); 843 } 844 void bz_h(MSARegister wt, int16_t offset); bz_h(MSARegister wt,Label * L)845 inline void bz_h(MSARegister wt, Label* L) { 846 bz_h(wt, shifted_branch_offset(L)); 847 } 848 void bz_w(MSARegister wt, int16_t offset); bz_w(MSARegister wt,Label * L)849 inline void bz_w(MSARegister wt, Label* L) { 850 bz_w(wt, shifted_branch_offset(L)); 851 } 852 void bz_d(MSARegister wt, int16_t offset); bz_d(MSARegister wt,Label * L)853 inline void bz_d(MSARegister wt, Label* L) { 854 bz_d(wt, shifted_branch_offset(L)); 855 } 856 void bnz_v(MSARegister wt, int16_t offset); bnz_v(MSARegister wt,Label * L)857 inline void bnz_v(MSARegister wt, Label* L) { 858 bnz_v(wt, shifted_branch_offset(L)); 859 } 860 void bnz_b(MSARegister wt, int16_t offset); bnz_b(MSARegister wt,Label * L)861 inline void bnz_b(MSARegister wt, Label* L) { 862 bnz_b(wt, shifted_branch_offset(L)); 863 } 864 void bnz_h(MSARegister wt, int16_t offset); bnz_h(MSARegister wt,Label * L)865 inline void bnz_h(MSARegister wt, Label* L) { 866 bnz_h(wt, shifted_branch_offset(L)); 867 } 868 void bnz_w(MSARegister wt, int16_t offset); bnz_w(MSARegister wt,Label * L)869 inline void bnz_w(MSARegister wt, Label* L) { 870 bnz_w(wt, shifted_branch_offset(L)); 871 } 872 void bnz_d(MSARegister wt, int16_t offset); bnz_d(MSARegister wt,Label * L)873 inline void bnz_d(MSARegister wt, Label* L) { 874 bnz_d(wt, shifted_branch_offset(L)); 875 } 876 877 void ld_b(MSARegister wd, const MemOperand& rs); 878 void ld_h(MSARegister wd, const MemOperand& rs); 879 void ld_w(MSARegister wd, const MemOperand& rs); 880 void ld_d(MSARegister wd, const MemOperand& rs); 881 void st_b(MSARegister wd, const MemOperand& rs); 882 void st_h(MSARegister wd, const MemOperand& rs); 883 void st_w(MSARegister wd, const MemOperand& rs); 884 void st_d(MSARegister wd, const MemOperand& rs); 885 886 void ldi_b(MSARegister wd, int32_t imm10); 887 void ldi_h(MSARegister wd, int32_t imm10); 888 void ldi_w(MSARegister wd, int32_t imm10); 889 void ldi_d(MSARegister wd, int32_t imm10); 890 891 void addvi_b(MSARegister wd, MSARegister ws, uint32_t imm5); 892 void addvi_h(MSARegister wd, MSARegister ws, uint32_t imm5); 893 void addvi_w(MSARegister wd, MSARegister ws, uint32_t imm5); 894 void addvi_d(MSARegister wd, MSARegister ws, uint32_t imm5); 895 void subvi_b(MSARegister wd, MSARegister ws, uint32_t imm5); 896 void subvi_h(MSARegister wd, MSARegister ws, uint32_t imm5); 897 void subvi_w(MSARegister wd, MSARegister ws, uint32_t imm5); 898 void subvi_d(MSARegister wd, MSARegister ws, uint32_t imm5); 899 void maxi_s_b(MSARegister wd, MSARegister ws, uint32_t imm5); 900 void maxi_s_h(MSARegister wd, MSARegister ws, uint32_t imm5); 901 void maxi_s_w(MSARegister wd, MSARegister ws, uint32_t imm5); 902 void maxi_s_d(MSARegister wd, MSARegister ws, uint32_t imm5); 903 void maxi_u_b(MSARegister wd, MSARegister ws, uint32_t imm5); 904 void maxi_u_h(MSARegister wd, MSARegister ws, uint32_t imm5); 905 void maxi_u_w(MSARegister wd, MSARegister ws, uint32_t imm5); 906 void maxi_u_d(MSARegister wd, MSARegister ws, uint32_t imm5); 907 void mini_s_b(MSARegister wd, MSARegister ws, uint32_t imm5); 908 void mini_s_h(MSARegister wd, MSARegister ws, uint32_t imm5); 909 void mini_s_w(MSARegister wd, MSARegister ws, uint32_t imm5); 910 void mini_s_d(MSARegister wd, MSARegister ws, uint32_t imm5); 911 void mini_u_b(MSARegister wd, MSARegister ws, uint32_t imm5); 912 void mini_u_h(MSARegister wd, MSARegister ws, uint32_t imm5); 913 void mini_u_w(MSARegister wd, MSARegister ws, uint32_t imm5); 914 void mini_u_d(MSARegister wd, MSARegister ws, uint32_t imm5); 915 void ceqi_b(MSARegister wd, MSARegister ws, uint32_t imm5); 916 void ceqi_h(MSARegister wd, MSARegister ws, uint32_t imm5); 917 void ceqi_w(MSARegister wd, MSARegister ws, uint32_t imm5); 918 void ceqi_d(MSARegister wd, MSARegister ws, uint32_t imm5); 919 void clti_s_b(MSARegister wd, MSARegister ws, uint32_t imm5); 920 void clti_s_h(MSARegister wd, MSARegister ws, uint32_t imm5); 921 void clti_s_w(MSARegister wd, MSARegister ws, uint32_t imm5); 922 void clti_s_d(MSARegister wd, MSARegister ws, uint32_t imm5); 923 void clti_u_b(MSARegister wd, MSARegister ws, uint32_t imm5); 924 void clti_u_h(MSARegister wd, MSARegister ws, uint32_t imm5); 925 void clti_u_w(MSARegister wd, MSARegister ws, uint32_t imm5); 926 void clti_u_d(MSARegister wd, MSARegister ws, uint32_t imm5); 927 void clei_s_b(MSARegister wd, MSARegister ws, uint32_t imm5); 928 void clei_s_h(MSARegister wd, MSARegister ws, uint32_t imm5); 929 void clei_s_w(MSARegister wd, MSARegister ws, uint32_t imm5); 930 void clei_s_d(MSARegister wd, MSARegister ws, uint32_t imm5); 931 void clei_u_b(MSARegister wd, MSARegister ws, uint32_t imm5); 932 void clei_u_h(MSARegister wd, MSARegister ws, uint32_t imm5); 933 void clei_u_w(MSARegister wd, MSARegister ws, uint32_t imm5); 934 void clei_u_d(MSARegister wd, MSARegister ws, uint32_t imm5); 935 936 void andi_b(MSARegister wd, MSARegister ws, uint32_t imm8); 937 void ori_b(MSARegister wd, MSARegister ws, uint32_t imm8); 938 void nori_b(MSARegister wd, MSARegister ws, uint32_t imm8); 939 void xori_b(MSARegister wd, MSARegister ws, uint32_t imm8); 940 void bmnzi_b(MSARegister wd, MSARegister ws, uint32_t imm8); 941 void bmzi_b(MSARegister wd, MSARegister ws, uint32_t imm8); 942 void bseli_b(MSARegister wd, MSARegister ws, uint32_t imm8); 943 void shf_b(MSARegister wd, MSARegister ws, uint32_t imm8); 944 void shf_h(MSARegister wd, MSARegister ws, uint32_t imm8); 945 void shf_w(MSARegister wd, MSARegister ws, uint32_t imm8); 946 947 void and_v(MSARegister wd, MSARegister ws, MSARegister wt); 948 void or_v(MSARegister wd, MSARegister ws, MSARegister wt); 949 void nor_v(MSARegister wd, MSARegister ws, MSARegister wt); 950 void xor_v(MSARegister wd, MSARegister ws, MSARegister wt); 951 void bmnz_v(MSARegister wd, MSARegister ws, MSARegister wt); 952 void bmz_v(MSARegister wd, MSARegister ws, MSARegister wt); 953 void bsel_v(MSARegister wd, MSARegister ws, MSARegister wt); 954 955 void fill_b(MSARegister wd, Register rs); 956 void fill_h(MSARegister wd, Register rs); 957 void fill_w(MSARegister wd, Register rs); 958 void fill_d(MSARegister wd, Register rs); 959 void pcnt_b(MSARegister wd, MSARegister ws); 960 void pcnt_h(MSARegister wd, MSARegister ws); 961 void pcnt_w(MSARegister wd, MSARegister ws); 962 void pcnt_d(MSARegister wd, MSARegister ws); 963 void nloc_b(MSARegister wd, MSARegister ws); 964 void nloc_h(MSARegister wd, MSARegister ws); 965 void nloc_w(MSARegister wd, MSARegister ws); 966 void nloc_d(MSARegister wd, MSARegister ws); 967 void nlzc_b(MSARegister wd, MSARegister ws); 968 void nlzc_h(MSARegister wd, MSARegister ws); 969 void nlzc_w(MSARegister wd, MSARegister ws); 970 void nlzc_d(MSARegister wd, MSARegister ws); 971 972 void fclass_w(MSARegister wd, MSARegister ws); 973 void fclass_d(MSARegister wd, MSARegister ws); 974 void ftrunc_s_w(MSARegister wd, MSARegister ws); 975 void ftrunc_s_d(MSARegister wd, MSARegister ws); 976 void ftrunc_u_w(MSARegister wd, MSARegister ws); 977 void ftrunc_u_d(MSARegister wd, MSARegister ws); 978 void fsqrt_w(MSARegister wd, MSARegister ws); 979 void fsqrt_d(MSARegister wd, MSARegister ws); 980 void frsqrt_w(MSARegister wd, MSARegister ws); 981 void frsqrt_d(MSARegister wd, MSARegister ws); 982 void frcp_w(MSARegister wd, MSARegister ws); 983 void frcp_d(MSARegister wd, MSARegister ws); 984 void frint_w(MSARegister wd, MSARegister ws); 985 void frint_d(MSARegister wd, MSARegister ws); 986 void flog2_w(MSARegister wd, MSARegister ws); 987 void flog2_d(MSARegister wd, MSARegister ws); 988 void fexupl_w(MSARegister wd, MSARegister ws); 989 void fexupl_d(MSARegister wd, MSARegister ws); 990 void fexupr_w(MSARegister wd, MSARegister ws); 991 void fexupr_d(MSARegister wd, MSARegister ws); 992 void ffql_w(MSARegister wd, MSARegister ws); 993 void ffql_d(MSARegister wd, MSARegister ws); 994 void ffqr_w(MSARegister wd, MSARegister ws); 995 void ffqr_d(MSARegister wd, MSARegister ws); 996 void ftint_s_w(MSARegister wd, MSARegister ws); 997 void ftint_s_d(MSARegister wd, MSARegister ws); 998 void ftint_u_w(MSARegister wd, MSARegister ws); 999 void ftint_u_d(MSARegister wd, MSARegister ws); 1000 void ffint_s_w(MSARegister wd, MSARegister ws); 1001 void ffint_s_d(MSARegister wd, MSARegister ws); 1002 void ffint_u_w(MSARegister wd, MSARegister ws); 1003 void ffint_u_d(MSARegister wd, MSARegister ws); 1004 1005 void sll_b(MSARegister wd, MSARegister ws, MSARegister wt); 1006 void sll_h(MSARegister wd, MSARegister ws, MSARegister wt); 1007 void sll_w(MSARegister wd, MSARegister ws, MSARegister wt); 1008 void sll_d(MSARegister wd, MSARegister ws, MSARegister wt); 1009 void sra_b(MSARegister wd, MSARegister ws, MSARegister wt); 1010 void sra_h(MSARegister wd, MSARegister ws, MSARegister wt); 1011 void sra_w(MSARegister wd, MSARegister ws, MSARegister wt); 1012 void sra_d(MSARegister wd, MSARegister ws, MSARegister wt); 1013 void srl_b(MSARegister wd, MSARegister ws, MSARegister wt); 1014 void srl_h(MSARegister wd, MSARegister ws, MSARegister wt); 1015 void srl_w(MSARegister wd, MSARegister ws, MSARegister wt); 1016 void srl_d(MSARegister wd, MSARegister ws, MSARegister wt); 1017 void bclr_b(MSARegister wd, MSARegister ws, MSARegister wt); 1018 void bclr_h(MSARegister wd, MSARegister ws, MSARegister wt); 1019 void bclr_w(MSARegister wd, MSARegister ws, MSARegister wt); 1020 void bclr_d(MSARegister wd, MSARegister ws, MSARegister wt); 1021 void bset_b(MSARegister wd, MSARegister ws, MSARegister wt); 1022 void bset_h(MSARegister wd, MSARegister ws, MSARegister wt); 1023 void bset_w(MSARegister wd, MSARegister ws, MSARegister wt); 1024 void bset_d(MSARegister wd, MSARegister ws, MSARegister wt); 1025 void bneg_b(MSARegister wd, MSARegister ws, MSARegister wt); 1026 void bneg_h(MSARegister wd, MSARegister ws, MSARegister wt); 1027 void bneg_w(MSARegister wd, MSARegister ws, MSARegister wt); 1028 void bneg_d(MSARegister wd, MSARegister ws, MSARegister wt); 1029 void binsl_b(MSARegister wd, MSARegister ws, MSARegister wt); 1030 void binsl_h(MSARegister wd, MSARegister ws, MSARegister wt); 1031 void binsl_w(MSARegister wd, MSARegister ws, MSARegister wt); 1032 void binsl_d(MSARegister wd, MSARegister ws, MSARegister wt); 1033 void binsr_b(MSARegister wd, MSARegister ws, MSARegister wt); 1034 void binsr_h(MSARegister wd, MSARegister ws, MSARegister wt); 1035 void binsr_w(MSARegister wd, MSARegister ws, MSARegister wt); 1036 void binsr_d(MSARegister wd, MSARegister ws, MSARegister wt); 1037 void addv_b(MSARegister wd, MSARegister ws, MSARegister wt); 1038 void addv_h(MSARegister wd, MSARegister ws, MSARegister wt); 1039 void addv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1040 void addv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1041 void subv_b(MSARegister wd, MSARegister ws, MSARegister wt); 1042 void subv_h(MSARegister wd, MSARegister ws, MSARegister wt); 1043 void subv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1044 void subv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1045 void max_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1046 void max_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1047 void max_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1048 void max_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1049 void max_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1050 void max_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1051 void max_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1052 void max_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1053 void min_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1054 void min_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1055 void min_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1056 void min_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1057 void min_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1058 void min_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1059 void min_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1060 void min_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1061 void max_a_b(MSARegister wd, MSARegister ws, MSARegister wt); 1062 void max_a_h(MSARegister wd, MSARegister ws, MSARegister wt); 1063 void max_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1064 void max_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1065 void min_a_b(MSARegister wd, MSARegister ws, MSARegister wt); 1066 void min_a_h(MSARegister wd, MSARegister ws, MSARegister wt); 1067 void min_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1068 void min_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1069 void ceq_b(MSARegister wd, MSARegister ws, MSARegister wt); 1070 void ceq_h(MSARegister wd, MSARegister ws, MSARegister wt); 1071 void ceq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1072 void ceq_d(MSARegister wd, MSARegister ws, MSARegister wt); 1073 void clt_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1074 void clt_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1075 void clt_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1076 void clt_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1077 void clt_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1078 void clt_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1079 void clt_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1080 void clt_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1081 void cle_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1082 void cle_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1083 void cle_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1084 void cle_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1085 void cle_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1086 void cle_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1087 void cle_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1088 void cle_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1089 void add_a_b(MSARegister wd, MSARegister ws, MSARegister wt); 1090 void add_a_h(MSARegister wd, MSARegister ws, MSARegister wt); 1091 void add_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1092 void add_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1093 void adds_a_b(MSARegister wd, MSARegister ws, MSARegister wt); 1094 void adds_a_h(MSARegister wd, MSARegister ws, MSARegister wt); 1095 void adds_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1096 void adds_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1097 void adds_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1098 void adds_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1099 void adds_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1100 void adds_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1101 void adds_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1102 void adds_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1103 void adds_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1104 void adds_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1105 void ave_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1106 void ave_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1107 void ave_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1108 void ave_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1109 void ave_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1110 void ave_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1111 void ave_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1112 void ave_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1113 void aver_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1114 void aver_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1115 void aver_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1116 void aver_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1117 void aver_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1118 void aver_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1119 void aver_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1120 void aver_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1121 void subs_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1122 void subs_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1123 void subs_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1124 void subs_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1125 void subs_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1126 void subs_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1127 void subs_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1128 void subs_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1129 void subsus_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1130 void subsus_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1131 void subsus_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1132 void subsus_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1133 void subsus_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1134 void subsus_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1135 void subsus_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1136 void subsus_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1137 void subsuu_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1138 void subsuu_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1139 void subsuu_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1140 void subsuu_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1141 void subsuu_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1142 void subsuu_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1143 void subsuu_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1144 void subsuu_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1145 void asub_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1146 void asub_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1147 void asub_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1148 void asub_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1149 void asub_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1150 void asub_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1151 void asub_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1152 void asub_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1153 void mulv_b(MSARegister wd, MSARegister ws, MSARegister wt); 1154 void mulv_h(MSARegister wd, MSARegister ws, MSARegister wt); 1155 void mulv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1156 void mulv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1157 void maddv_b(MSARegister wd, MSARegister ws, MSARegister wt); 1158 void maddv_h(MSARegister wd, MSARegister ws, MSARegister wt); 1159 void maddv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1160 void maddv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1161 void msubv_b(MSARegister wd, MSARegister ws, MSARegister wt); 1162 void msubv_h(MSARegister wd, MSARegister ws, MSARegister wt); 1163 void msubv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1164 void msubv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1165 void div_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1166 void div_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1167 void div_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1168 void div_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1169 void div_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1170 void div_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1171 void div_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1172 void div_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1173 void mod_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1174 void mod_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1175 void mod_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1176 void mod_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1177 void mod_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1178 void mod_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1179 void mod_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1180 void mod_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1181 void dotp_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1182 void dotp_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1183 void dotp_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1184 void dotp_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1185 void dotp_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1186 void dotp_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1187 void dotp_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1188 void dotp_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1189 void dpadd_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1190 void dpadd_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1191 void dpadd_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1192 void dpadd_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1193 void dpadd_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1194 void dpadd_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1195 void dpadd_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1196 void dpadd_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1197 void dpsub_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1198 void dpsub_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1199 void dpsub_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1200 void dpsub_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1201 void dpsub_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1202 void dpsub_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1203 void dpsub_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1204 void dpsub_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1205 void sld_b(MSARegister wd, MSARegister ws, Register rt); 1206 void sld_h(MSARegister wd, MSARegister ws, Register rt); 1207 void sld_w(MSARegister wd, MSARegister ws, Register rt); 1208 void sld_d(MSARegister wd, MSARegister ws, Register rt); 1209 void splat_b(MSARegister wd, MSARegister ws, Register rt); 1210 void splat_h(MSARegister wd, MSARegister ws, Register rt); 1211 void splat_w(MSARegister wd, MSARegister ws, Register rt); 1212 void splat_d(MSARegister wd, MSARegister ws, Register rt); 1213 void pckev_b(MSARegister wd, MSARegister ws, MSARegister wt); 1214 void pckev_h(MSARegister wd, MSARegister ws, MSARegister wt); 1215 void pckev_w(MSARegister wd, MSARegister ws, MSARegister wt); 1216 void pckev_d(MSARegister wd, MSARegister ws, MSARegister wt); 1217 void pckod_b(MSARegister wd, MSARegister ws, MSARegister wt); 1218 void pckod_h(MSARegister wd, MSARegister ws, MSARegister wt); 1219 void pckod_w(MSARegister wd, MSARegister ws, MSARegister wt); 1220 void pckod_d(MSARegister wd, MSARegister ws, MSARegister wt); 1221 void ilvl_b(MSARegister wd, MSARegister ws, MSARegister wt); 1222 void ilvl_h(MSARegister wd, MSARegister ws, MSARegister wt); 1223 void ilvl_w(MSARegister wd, MSARegister ws, MSARegister wt); 1224 void ilvl_d(MSARegister wd, MSARegister ws, MSARegister wt); 1225 void ilvr_b(MSARegister wd, MSARegister ws, MSARegister wt); 1226 void ilvr_h(MSARegister wd, MSARegister ws, MSARegister wt); 1227 void ilvr_w(MSARegister wd, MSARegister ws, MSARegister wt); 1228 void ilvr_d(MSARegister wd, MSARegister ws, MSARegister wt); 1229 void ilvev_b(MSARegister wd, MSARegister ws, MSARegister wt); 1230 void ilvev_h(MSARegister wd, MSARegister ws, MSARegister wt); 1231 void ilvev_w(MSARegister wd, MSARegister ws, MSARegister wt); 1232 void ilvev_d(MSARegister wd, MSARegister ws, MSARegister wt); 1233 void ilvod_b(MSARegister wd, MSARegister ws, MSARegister wt); 1234 void ilvod_h(MSARegister wd, MSARegister ws, MSARegister wt); 1235 void ilvod_w(MSARegister wd, MSARegister ws, MSARegister wt); 1236 void ilvod_d(MSARegister wd, MSARegister ws, MSARegister wt); 1237 void vshf_b(MSARegister wd, MSARegister ws, MSARegister wt); 1238 void vshf_h(MSARegister wd, MSARegister ws, MSARegister wt); 1239 void vshf_w(MSARegister wd, MSARegister ws, MSARegister wt); 1240 void vshf_d(MSARegister wd, MSARegister ws, MSARegister wt); 1241 void srar_b(MSARegister wd, MSARegister ws, MSARegister wt); 1242 void srar_h(MSARegister wd, MSARegister ws, MSARegister wt); 1243 void srar_w(MSARegister wd, MSARegister ws, MSARegister wt); 1244 void srar_d(MSARegister wd, MSARegister ws, MSARegister wt); 1245 void srlr_b(MSARegister wd, MSARegister ws, MSARegister wt); 1246 void srlr_h(MSARegister wd, MSARegister ws, MSARegister wt); 1247 void srlr_w(MSARegister wd, MSARegister ws, MSARegister wt); 1248 void srlr_d(MSARegister wd, MSARegister ws, MSARegister wt); 1249 void hadd_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1250 void hadd_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1251 void hadd_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1252 void hadd_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1253 void hadd_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1254 void hadd_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1255 void hadd_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1256 void hadd_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1257 void hsub_s_b(MSARegister wd, MSARegister ws, MSARegister wt); 1258 void hsub_s_h(MSARegister wd, MSARegister ws, MSARegister wt); 1259 void hsub_s_w(MSARegister wd, MSARegister ws, MSARegister wt); 1260 void hsub_s_d(MSARegister wd, MSARegister ws, MSARegister wt); 1261 void hsub_u_b(MSARegister wd, MSARegister ws, MSARegister wt); 1262 void hsub_u_h(MSARegister wd, MSARegister ws, MSARegister wt); 1263 void hsub_u_w(MSARegister wd, MSARegister ws, MSARegister wt); 1264 void hsub_u_d(MSARegister wd, MSARegister ws, MSARegister wt); 1265 1266 void fcaf_w(MSARegister wd, MSARegister ws, MSARegister wt); 1267 void fcaf_d(MSARegister wd, MSARegister ws, MSARegister wt); 1268 void fcun_w(MSARegister wd, MSARegister ws, MSARegister wt); 1269 void fcun_d(MSARegister wd, MSARegister ws, MSARegister wt); 1270 void fceq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1271 void fceq_d(MSARegister wd, MSARegister ws, MSARegister wt); 1272 void fcueq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1273 void fcueq_d(MSARegister wd, MSARegister ws, MSARegister wt); 1274 void fclt_w(MSARegister wd, MSARegister ws, MSARegister wt); 1275 void fclt_d(MSARegister wd, MSARegister ws, MSARegister wt); 1276 void fcult_w(MSARegister wd, MSARegister ws, MSARegister wt); 1277 void fcult_d(MSARegister wd, MSARegister ws, MSARegister wt); 1278 void fcle_w(MSARegister wd, MSARegister ws, MSARegister wt); 1279 void fcle_d(MSARegister wd, MSARegister ws, MSARegister wt); 1280 void fcule_w(MSARegister wd, MSARegister ws, MSARegister wt); 1281 void fcule_d(MSARegister wd, MSARegister ws, MSARegister wt); 1282 void fsaf_w(MSARegister wd, MSARegister ws, MSARegister wt); 1283 void fsaf_d(MSARegister wd, MSARegister ws, MSARegister wt); 1284 void fsun_w(MSARegister wd, MSARegister ws, MSARegister wt); 1285 void fsun_d(MSARegister wd, MSARegister ws, MSARegister wt); 1286 void fseq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1287 void fseq_d(MSARegister wd, MSARegister ws, MSARegister wt); 1288 void fsueq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1289 void fsueq_d(MSARegister wd, MSARegister ws, MSARegister wt); 1290 void fslt_w(MSARegister wd, MSARegister ws, MSARegister wt); 1291 void fslt_d(MSARegister wd, MSARegister ws, MSARegister wt); 1292 void fsult_w(MSARegister wd, MSARegister ws, MSARegister wt); 1293 void fsult_d(MSARegister wd, MSARegister ws, MSARegister wt); 1294 void fsle_w(MSARegister wd, MSARegister ws, MSARegister wt); 1295 void fsle_d(MSARegister wd, MSARegister ws, MSARegister wt); 1296 void fsule_w(MSARegister wd, MSARegister ws, MSARegister wt); 1297 void fsule_d(MSARegister wd, MSARegister ws, MSARegister wt); 1298 void fadd_w(MSARegister wd, MSARegister ws, MSARegister wt); 1299 void fadd_d(MSARegister wd, MSARegister ws, MSARegister wt); 1300 void fsub_w(MSARegister wd, MSARegister ws, MSARegister wt); 1301 void fsub_d(MSARegister wd, MSARegister ws, MSARegister wt); 1302 void fmul_w(MSARegister wd, MSARegister ws, MSARegister wt); 1303 void fmul_d(MSARegister wd, MSARegister ws, MSARegister wt); 1304 void fdiv_w(MSARegister wd, MSARegister ws, MSARegister wt); 1305 void fdiv_d(MSARegister wd, MSARegister ws, MSARegister wt); 1306 void fmadd_w(MSARegister wd, MSARegister ws, MSARegister wt); 1307 void fmadd_d(MSARegister wd, MSARegister ws, MSARegister wt); 1308 void fmsub_w(MSARegister wd, MSARegister ws, MSARegister wt); 1309 void fmsub_d(MSARegister wd, MSARegister ws, MSARegister wt); 1310 void fexp2_w(MSARegister wd, MSARegister ws, MSARegister wt); 1311 void fexp2_d(MSARegister wd, MSARegister ws, MSARegister wt); 1312 void fexdo_h(MSARegister wd, MSARegister ws, MSARegister wt); 1313 void fexdo_w(MSARegister wd, MSARegister ws, MSARegister wt); 1314 void ftq_h(MSARegister wd, MSARegister ws, MSARegister wt); 1315 void ftq_w(MSARegister wd, MSARegister ws, MSARegister wt); 1316 void fmin_w(MSARegister wd, MSARegister ws, MSARegister wt); 1317 void fmin_d(MSARegister wd, MSARegister ws, MSARegister wt); 1318 void fmin_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1319 void fmin_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1320 void fmax_w(MSARegister wd, MSARegister ws, MSARegister wt); 1321 void fmax_d(MSARegister wd, MSARegister ws, MSARegister wt); 1322 void fmax_a_w(MSARegister wd, MSARegister ws, MSARegister wt); 1323 void fmax_a_d(MSARegister wd, MSARegister ws, MSARegister wt); 1324 void fcor_w(MSARegister wd, MSARegister ws, MSARegister wt); 1325 void fcor_d(MSARegister wd, MSARegister ws, MSARegister wt); 1326 void fcune_w(MSARegister wd, MSARegister ws, MSARegister wt); 1327 void fcune_d(MSARegister wd, MSARegister ws, MSARegister wt); 1328 void fcne_w(MSARegister wd, MSARegister ws, MSARegister wt); 1329 void fcne_d(MSARegister wd, MSARegister ws, MSARegister wt); 1330 void mul_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1331 void mul_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1332 void madd_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1333 void madd_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1334 void msub_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1335 void msub_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1336 void fsor_w(MSARegister wd, MSARegister ws, MSARegister wt); 1337 void fsor_d(MSARegister wd, MSARegister ws, MSARegister wt); 1338 void fsune_w(MSARegister wd, MSARegister ws, MSARegister wt); 1339 void fsune_d(MSARegister wd, MSARegister ws, MSARegister wt); 1340 void fsne_w(MSARegister wd, MSARegister ws, MSARegister wt); 1341 void fsne_d(MSARegister wd, MSARegister ws, MSARegister wt); 1342 void mulr_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1343 void mulr_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1344 void maddr_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1345 void maddr_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1346 void msubr_q_h(MSARegister wd, MSARegister ws, MSARegister wt); 1347 void msubr_q_w(MSARegister wd, MSARegister ws, MSARegister wt); 1348 1349 void sldi_b(MSARegister wd, MSARegister ws, uint32_t n); 1350 void sldi_h(MSARegister wd, MSARegister ws, uint32_t n); 1351 void sldi_w(MSARegister wd, MSARegister ws, uint32_t n); 1352 void sldi_d(MSARegister wd, MSARegister ws, uint32_t n); 1353 void splati_b(MSARegister wd, MSARegister ws, uint32_t n); 1354 void splati_h(MSARegister wd, MSARegister ws, uint32_t n); 1355 void splati_w(MSARegister wd, MSARegister ws, uint32_t n); 1356 void splati_d(MSARegister wd, MSARegister ws, uint32_t n); 1357 void copy_s_b(Register rd, MSARegister ws, uint32_t n); 1358 void copy_s_h(Register rd, MSARegister ws, uint32_t n); 1359 void copy_s_w(Register rd, MSARegister ws, uint32_t n); 1360 void copy_s_d(Register rd, MSARegister ws, uint32_t n); 1361 void copy_u_b(Register rd, MSARegister ws, uint32_t n); 1362 void copy_u_h(Register rd, MSARegister ws, uint32_t n); 1363 void copy_u_w(Register rd, MSARegister ws, uint32_t n); 1364 void insert_b(MSARegister wd, uint32_t n, Register rs); 1365 void insert_h(MSARegister wd, uint32_t n, Register rs); 1366 void insert_w(MSARegister wd, uint32_t n, Register rs); 1367 void insert_d(MSARegister wd, uint32_t n, Register rs); 1368 void insve_b(MSARegister wd, uint32_t n, MSARegister ws); 1369 void insve_h(MSARegister wd, uint32_t n, MSARegister ws); 1370 void insve_w(MSARegister wd, uint32_t n, MSARegister ws); 1371 void insve_d(MSARegister wd, uint32_t n, MSARegister ws); 1372 void move_v(MSARegister wd, MSARegister ws); 1373 void ctcmsa(MSAControlRegister cd, Register rs); 1374 void cfcmsa(Register rd, MSAControlRegister cs); 1375 1376 void slli_b(MSARegister wd, MSARegister ws, uint32_t m); 1377 void slli_h(MSARegister wd, MSARegister ws, uint32_t m); 1378 void slli_w(MSARegister wd, MSARegister ws, uint32_t m); 1379 void slli_d(MSARegister wd, MSARegister ws, uint32_t m); 1380 void srai_b(MSARegister wd, MSARegister ws, uint32_t m); 1381 void srai_h(MSARegister wd, MSARegister ws, uint32_t m); 1382 void srai_w(MSARegister wd, MSARegister ws, uint32_t m); 1383 void srai_d(MSARegister wd, MSARegister ws, uint32_t m); 1384 void srli_b(MSARegister wd, MSARegister ws, uint32_t m); 1385 void srli_h(MSARegister wd, MSARegister ws, uint32_t m); 1386 void srli_w(MSARegister wd, MSARegister ws, uint32_t m); 1387 void srli_d(MSARegister wd, MSARegister ws, uint32_t m); 1388 void bclri_b(MSARegister wd, MSARegister ws, uint32_t m); 1389 void bclri_h(MSARegister wd, MSARegister ws, uint32_t m); 1390 void bclri_w(MSARegister wd, MSARegister ws, uint32_t m); 1391 void bclri_d(MSARegister wd, MSARegister ws, uint32_t m); 1392 void bseti_b(MSARegister wd, MSARegister ws, uint32_t m); 1393 void bseti_h(MSARegister wd, MSARegister ws, uint32_t m); 1394 void bseti_w(MSARegister wd, MSARegister ws, uint32_t m); 1395 void bseti_d(MSARegister wd, MSARegister ws, uint32_t m); 1396 void bnegi_b(MSARegister wd, MSARegister ws, uint32_t m); 1397 void bnegi_h(MSARegister wd, MSARegister ws, uint32_t m); 1398 void bnegi_w(MSARegister wd, MSARegister ws, uint32_t m); 1399 void bnegi_d(MSARegister wd, MSARegister ws, uint32_t m); 1400 void binsli_b(MSARegister wd, MSARegister ws, uint32_t m); 1401 void binsli_h(MSARegister wd, MSARegister ws, uint32_t m); 1402 void binsli_w(MSARegister wd, MSARegister ws, uint32_t m); 1403 void binsli_d(MSARegister wd, MSARegister ws, uint32_t m); 1404 void binsri_b(MSARegister wd, MSARegister ws, uint32_t m); 1405 void binsri_h(MSARegister wd, MSARegister ws, uint32_t m); 1406 void binsri_w(MSARegister wd, MSARegister ws, uint32_t m); 1407 void binsri_d(MSARegister wd, MSARegister ws, uint32_t m); 1408 void sat_s_b(MSARegister wd, MSARegister ws, uint32_t m); 1409 void sat_s_h(MSARegister wd, MSARegister ws, uint32_t m); 1410 void sat_s_w(MSARegister wd, MSARegister ws, uint32_t m); 1411 void sat_s_d(MSARegister wd, MSARegister ws, uint32_t m); 1412 void sat_u_b(MSARegister wd, MSARegister ws, uint32_t m); 1413 void sat_u_h(MSARegister wd, MSARegister ws, uint32_t m); 1414 void sat_u_w(MSARegister wd, MSARegister ws, uint32_t m); 1415 void sat_u_d(MSARegister wd, MSARegister ws, uint32_t m); 1416 void srari_b(MSARegister wd, MSARegister ws, uint32_t m); 1417 void srari_h(MSARegister wd, MSARegister ws, uint32_t m); 1418 void srari_w(MSARegister wd, MSARegister ws, uint32_t m); 1419 void srari_d(MSARegister wd, MSARegister ws, uint32_t m); 1420 void srlri_b(MSARegister wd, MSARegister ws, uint32_t m); 1421 void srlri_h(MSARegister wd, MSARegister ws, uint32_t m); 1422 void srlri_w(MSARegister wd, MSARegister ws, uint32_t m); 1423 void srlri_d(MSARegister wd, MSARegister ws, uint32_t m); 1424 1425 // Check the code size generated from label to here. SizeOfCodeGeneratedSince(Label * label)1426 int SizeOfCodeGeneratedSince(Label* label) { 1427 return pc_offset() - label->pos(); 1428 } 1429 1430 // Check the number of instructions generated from label to here. InstructionsGeneratedSince(Label * label)1431 int InstructionsGeneratedSince(Label* label) { 1432 return SizeOfCodeGeneratedSince(label) / kInstrSize; 1433 } 1434 1435 // Class for scoping postponing the trampoline pool generation. 1436 class BlockTrampolinePoolScope { 1437 public: BlockTrampolinePoolScope(Assembler * assem)1438 explicit BlockTrampolinePoolScope(Assembler* assem) : assem_(assem) { 1439 assem_->StartBlockTrampolinePool(); 1440 } ~BlockTrampolinePoolScope()1441 ~BlockTrampolinePoolScope() { assem_->EndBlockTrampolinePool(); } 1442 1443 private: 1444 Assembler* assem_; 1445 1446 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockTrampolinePoolScope); 1447 }; 1448 1449 // Class for postponing the assembly buffer growth. Typically used for 1450 // sequences of instructions that must be emitted as a unit, before 1451 // buffer growth (and relocation) can occur. 1452 // This blocking scope is not nestable. 1453 class BlockGrowBufferScope { 1454 public: BlockGrowBufferScope(Assembler * assem)1455 explicit BlockGrowBufferScope(Assembler* assem) : assem_(assem) { 1456 assem_->StartBlockGrowBuffer(); 1457 } ~BlockGrowBufferScope()1458 ~BlockGrowBufferScope() { assem_->EndBlockGrowBuffer(); } 1459 1460 private: 1461 Assembler* assem_; 1462 1463 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockGrowBufferScope); 1464 }; 1465 1466 // Record a deoptimization reason that can be used by a log or cpu profiler. 1467 // Use --trace-deopt to enable. 1468 void RecordDeoptReason(DeoptimizeReason reason, SourcePosition position, 1469 int id); 1470 1471 static int RelocateInternalReference(RelocInfo::Mode rmode, Address pc, 1472 intptr_t pc_delta); 1473 1474 // Writes a single byte or word of data in the code stream. Used for 1475 // inline tables, e.g., jump-tables. 1476 void db(uint8_t data); 1477 void dd(uint32_t data); 1478 void dq(uint64_t data); dp(uintptr_t data)1479 void dp(uintptr_t data) { dq(data); } 1480 void dd(Label* label); 1481 1482 // Postpone the generation of the trampoline pool for the specified number of 1483 // instructions. 1484 void BlockTrampolinePoolFor(int instructions); 1485 1486 // Check if there is less than kGap bytes available in the buffer. 1487 // If this is the case, we need to grow the buffer before emitting 1488 // an instruction or relocation information. overflow()1489 inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; } 1490 1491 // Get the number of bytes available in the buffer. available_space()1492 inline intptr_t available_space() const { 1493 return reloc_info_writer.pos() - pc_; 1494 } 1495 1496 // Read/patch instructions. instr_at(Address pc)1497 static Instr instr_at(Address pc) { return *reinterpret_cast<Instr*>(pc); } instr_at_put(Address pc,Instr instr)1498 static void instr_at_put(Address pc, Instr instr) { 1499 *reinterpret_cast<Instr*>(pc) = instr; 1500 } instr_at(int pos)1501 Instr instr_at(int pos) { 1502 return *reinterpret_cast<Instr*>(buffer_start_ + pos); 1503 } instr_at_put(int pos,Instr instr)1504 void instr_at_put(int pos, Instr instr) { 1505 *reinterpret_cast<Instr*>(buffer_start_ + pos) = instr; 1506 } 1507 1508 // Check if an instruction is a branch of some kind. 1509 static bool IsBranch(Instr instr); 1510 static bool IsMsaBranch(Instr instr); 1511 static bool IsBc(Instr instr); 1512 static bool IsNal(Instr instr); 1513 static bool IsBzc(Instr instr); 1514 1515 static bool IsBeq(Instr instr); 1516 static bool IsBne(Instr instr); 1517 static bool IsBeqzc(Instr instr); 1518 static bool IsBnezc(Instr instr); 1519 static bool IsBeqc(Instr instr); 1520 static bool IsBnec(Instr instr); 1521 1522 static bool IsJump(Instr instr); 1523 static bool IsJ(Instr instr); 1524 static bool IsLui(Instr instr); 1525 static bool IsOri(Instr instr); 1526 static bool IsMov(Instr instr, Register rd, Register rs); 1527 1528 static bool IsJal(Instr instr); 1529 static bool IsJr(Instr instr); 1530 static bool IsJalr(Instr instr); 1531 1532 static bool IsNop(Instr instr, unsigned int type); 1533 static bool IsPop(Instr instr); 1534 static bool IsPush(Instr instr); 1535 static bool IsLwRegFpOffset(Instr instr); 1536 static bool IsSwRegFpOffset(Instr instr); 1537 static bool IsLwRegFpNegOffset(Instr instr); 1538 static bool IsSwRegFpNegOffset(Instr instr); 1539 1540 static Register GetRtReg(Instr instr); 1541 static Register GetRsReg(Instr instr); 1542 static Register GetRdReg(Instr instr); 1543 1544 static uint32_t GetRt(Instr instr); 1545 static uint32_t GetRtField(Instr instr); 1546 static uint32_t GetRs(Instr instr); 1547 static uint32_t GetRsField(Instr instr); 1548 static uint32_t GetRd(Instr instr); 1549 static uint32_t GetRdField(Instr instr); 1550 static uint32_t GetSa(Instr instr); 1551 static uint32_t GetSaField(Instr instr); 1552 static uint32_t GetOpcodeField(Instr instr); 1553 static uint32_t GetFunction(Instr instr); 1554 static uint32_t GetFunctionField(Instr instr); 1555 static uint32_t GetImmediate16(Instr instr); 1556 static uint32_t GetLabelConst(Instr instr); 1557 1558 static int32_t GetBranchOffset(Instr instr); 1559 static bool IsLw(Instr instr); 1560 static int16_t GetLwOffset(Instr instr); 1561 static Instr SetLwOffset(Instr instr, int16_t offset); 1562 1563 static bool IsSw(Instr instr); 1564 static Instr SetSwOffset(Instr instr, int16_t offset); 1565 static bool IsAddImmediate(Instr instr); 1566 static Instr SetAddImmediateOffset(Instr instr, int16_t offset); 1567 1568 static bool IsAndImmediate(Instr instr); 1569 static bool IsEmittedConstant(Instr instr); 1570 1571 void CheckTrampolinePool(); 1572 IsPrevInstrCompactBranch()1573 bool IsPrevInstrCompactBranch() { return prev_instr_compact_branch_; } IsCompactBranchSupported()1574 static bool IsCompactBranchSupported() { return kArchVariant == kMips64r6; } 1575 UnboundLabelsCount()1576 inline int UnboundLabelsCount() { return unbound_labels_count_; } 1577 1578 protected: 1579 // Load Scaled Address instructions. 1580 void lsa(Register rd, Register rt, Register rs, uint8_t sa); 1581 void dlsa(Register rd, Register rt, Register rs, uint8_t sa); 1582 1583 // Readable constants for base and offset adjustment helper, these indicate if 1584 // aside from offset, another value like offset + 4 should fit into int16. 1585 enum class OffsetAccessType : bool { 1586 SINGLE_ACCESS = false, 1587 TWO_ACCESSES = true 1588 }; 1589 1590 // Helper function for memory load/store using base register and offset. 1591 void AdjustBaseAndOffset( 1592 MemOperand* src, 1593 OffsetAccessType access_type = OffsetAccessType::SINGLE_ACCESS, 1594 int second_access_add_to_offset = 4); 1595 1596 inline static void set_target_internal_reference_encoded_at(Address pc, 1597 Address target); 1598 buffer_space()1599 int64_t buffer_space() const { return reloc_info_writer.pos() - pc_; } 1600 1601 // Decode branch instruction at pos and return branch target pos. 1602 int target_at(int pos, bool is_internal); 1603 1604 // Patch branch instruction at pos to branch to given branch target pos. 1605 void target_at_put(int pos, int target_pos, bool is_internal); 1606 1607 // Say if we need to relocate with this mode. 1608 bool MustUseReg(RelocInfo::Mode rmode); 1609 1610 // Record reloc info for current pc_. 1611 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); 1612 1613 // Block the emission of the trampoline pool before pc_offset. BlockTrampolinePoolBefore(int pc_offset)1614 void BlockTrampolinePoolBefore(int pc_offset) { 1615 if (no_trampoline_pool_before_ < pc_offset) 1616 no_trampoline_pool_before_ = pc_offset; 1617 } 1618 StartBlockTrampolinePool()1619 void StartBlockTrampolinePool() { trampoline_pool_blocked_nesting_++; } 1620 EndBlockTrampolinePool()1621 void EndBlockTrampolinePool() { 1622 trampoline_pool_blocked_nesting_--; 1623 if (trampoline_pool_blocked_nesting_ == 0) { 1624 CheckTrampolinePoolQuick(1); 1625 } 1626 } 1627 is_trampoline_pool_blocked()1628 bool is_trampoline_pool_blocked() const { 1629 return trampoline_pool_blocked_nesting_ > 0; 1630 } 1631 has_exception()1632 bool has_exception() const { return internal_trampoline_exception_; } 1633 is_trampoline_emitted()1634 bool is_trampoline_emitted() const { return trampoline_emitted_; } 1635 1636 // Temporarily block automatic assembly buffer growth. StartBlockGrowBuffer()1637 void StartBlockGrowBuffer() { 1638 DCHECK(!block_buffer_growth_); 1639 block_buffer_growth_ = true; 1640 } 1641 EndBlockGrowBuffer()1642 void EndBlockGrowBuffer() { 1643 DCHECK(block_buffer_growth_); 1644 block_buffer_growth_ = false; 1645 } 1646 is_buffer_growth_blocked()1647 bool is_buffer_growth_blocked() const { return block_buffer_growth_; } 1648 EmitForbiddenSlotInstruction()1649 void EmitForbiddenSlotInstruction() { 1650 if (IsPrevInstrCompactBranch()) { 1651 nop(); 1652 } 1653 } 1654 1655 void CheckTrampolinePoolQuick(int extra_instructions = 0) { 1656 if (pc_offset() >= next_buffer_check_ - extra_instructions * kInstrSize) { 1657 CheckTrampolinePool(); 1658 } 1659 } 1660 set_last_call_pc_(byte * pc)1661 void set_last_call_pc_(byte* pc) { last_call_pc_ = pc; } 1662 1663 private: 1664 // Avoid overflows for displacements etc. 1665 static const int kMaximalBufferSize = 512 * MB; 1666 1667 // Buffer size and constant pool distance are checked together at regular 1668 // intervals of kBufferCheckInterval emitted bytes. 1669 static constexpr int kBufferCheckInterval = 1 * KB / 2; 1670 1671 // Code generation. 1672 // The relocation writer's position is at least kGap bytes below the end of 1673 // the generated instructions. This is so that multi-instruction sequences do 1674 // not have to check for overflow. The same is true for writes of large 1675 // relocation info entries. 1676 static constexpr int kGap = 64; 1677 STATIC_ASSERT(AssemblerBase::kMinimalBufferSize >= 2 * kGap); 1678 1679 // Repeated checking whether the trampoline pool should be emitted is rather 1680 // expensive. By default we only check again once a number of instructions 1681 // has been generated. 1682 static constexpr int kCheckConstIntervalInst = 32; 1683 static constexpr int kCheckConstInterval = 1684 kCheckConstIntervalInst * kInstrSize; 1685 1686 int next_buffer_check_; // pc offset of next buffer check. 1687 1688 // Emission of the trampoline pool may be blocked in some code sequences. 1689 int trampoline_pool_blocked_nesting_; // Block emission if this is not zero. 1690 int no_trampoline_pool_before_; // Block emission before this pc offset. 1691 1692 // Keep track of the last emitted pool to guarantee a maximal distance. 1693 int last_trampoline_pool_end_; // pc offset of the end of the last pool. 1694 1695 // Automatic growth of the assembly buffer may be blocked for some sequences. 1696 bool block_buffer_growth_; // Block growth when true. 1697 1698 // Relocation information generation. 1699 // Each relocation is encoded as a variable size value. 1700 static constexpr int kMaxRelocSize = RelocInfoWriter::kMaxSize; 1701 RelocInfoWriter reloc_info_writer; 1702 1703 // The bound position, before this we cannot do instruction elimination. 1704 int last_bound_pos_; 1705 1706 // Readable constants for compact branch handling in emit() 1707 enum class CompactBranchType : bool { NO = false, COMPACT_BRANCH = true }; 1708 1709 // Code emission. 1710 inline void CheckBuffer(); 1711 void GrowBuffer(); 1712 inline void emit(Instr x, 1713 CompactBranchType is_compact_branch = CompactBranchType::NO); 1714 inline void emit(uint64_t x); 1715 inline void CheckForEmitInForbiddenSlot(); 1716 template <typename T> 1717 inline void EmitHelper(T x); 1718 inline void EmitHelper(Instr x, CompactBranchType is_compact_branch); 1719 1720 // Instruction generation. 1721 // We have 3 different kind of encoding layout on MIPS. 1722 // However due to many different types of objects encoded in the same fields 1723 // we have quite a few aliases for each mode. 1724 // Using the same structure to refer to Register and FPURegister would spare a 1725 // few aliases, but mixing both does not look clean to me. 1726 // Anyway we could surely implement this differently. 1727 1728 void GenInstrRegister(Opcode opcode, Register rs, Register rt, Register rd, 1729 uint16_t sa = 0, SecondaryField func = nullptrSF); 1730 1731 void GenInstrRegister(Opcode opcode, Register rs, Register rt, uint16_t msb, 1732 uint16_t lsb, SecondaryField func); 1733 1734 void GenInstrRegister(Opcode opcode, SecondaryField fmt, FPURegister ft, 1735 FPURegister fs, FPURegister fd, 1736 SecondaryField func = nullptrSF); 1737 1738 void GenInstrRegister(Opcode opcode, FPURegister fr, FPURegister ft, 1739 FPURegister fs, FPURegister fd, 1740 SecondaryField func = nullptrSF); 1741 1742 void GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, 1743 FPURegister fs, FPURegister fd, 1744 SecondaryField func = nullptrSF); 1745 1746 void GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, 1747 FPUControlRegister fs, SecondaryField func = nullptrSF); 1748 1749 void GenInstrImmediate( 1750 Opcode opcode, Register rs, Register rt, int32_t j, 1751 CompactBranchType is_compact_branch = CompactBranchType::NO); 1752 void GenInstrImmediate( 1753 Opcode opcode, Register rs, SecondaryField SF, int32_t j, 1754 CompactBranchType is_compact_branch = CompactBranchType::NO); 1755 void GenInstrImmediate( 1756 Opcode opcode, Register r1, FPURegister r2, int32_t j, 1757 CompactBranchType is_compact_branch = CompactBranchType::NO); 1758 void GenInstrImmediate(Opcode opcode, Register base, Register rt, 1759 int32_t offset9, int bit6, SecondaryField func); 1760 void GenInstrImmediate( 1761 Opcode opcode, Register rs, int32_t offset21, 1762 CompactBranchType is_compact_branch = CompactBranchType::NO); 1763 void GenInstrImmediate(Opcode opcode, Register rs, uint32_t offset21); 1764 void GenInstrImmediate( 1765 Opcode opcode, int32_t offset26, 1766 CompactBranchType is_compact_branch = CompactBranchType::NO); 1767 1768 void GenInstrJump(Opcode opcode, uint32_t address); 1769 1770 // MSA 1771 void GenInstrMsaI8(SecondaryField operation, uint32_t imm8, MSARegister ws, 1772 MSARegister wd); 1773 1774 void GenInstrMsaI5(SecondaryField operation, SecondaryField df, int32_t imm5, 1775 MSARegister ws, MSARegister wd); 1776 1777 void GenInstrMsaBit(SecondaryField operation, SecondaryField df, uint32_t m, 1778 MSARegister ws, MSARegister wd); 1779 1780 void GenInstrMsaI10(SecondaryField operation, SecondaryField df, 1781 int32_t imm10, MSARegister wd); 1782 1783 template <typename RegType> 1784 void GenInstrMsa3R(SecondaryField operation, SecondaryField df, RegType t, 1785 MSARegister ws, MSARegister wd); 1786 1787 template <typename DstType, typename SrcType> 1788 void GenInstrMsaElm(SecondaryField operation, SecondaryField df, uint32_t n, 1789 SrcType src, DstType dst); 1790 1791 void GenInstrMsa3RF(SecondaryField operation, uint32_t df, MSARegister wt, 1792 MSARegister ws, MSARegister wd); 1793 1794 void GenInstrMsaVec(SecondaryField operation, MSARegister wt, MSARegister ws, 1795 MSARegister wd); 1796 1797 void GenInstrMsaMI10(SecondaryField operation, int32_t s10, Register rs, 1798 MSARegister wd); 1799 1800 void GenInstrMsa2R(SecondaryField operation, SecondaryField df, 1801 MSARegister ws, MSARegister wd); 1802 1803 void GenInstrMsa2RF(SecondaryField operation, SecondaryField df, 1804 MSARegister ws, MSARegister wd); 1805 1806 void GenInstrMsaBranch(SecondaryField operation, MSARegister wt, 1807 int32_t offset16); 1808 is_valid_msa_df_m(SecondaryField bit_df,uint32_t m)1809 inline bool is_valid_msa_df_m(SecondaryField bit_df, uint32_t m) { 1810 switch (bit_df) { 1811 case BIT_DF_b: 1812 return is_uint3(m); 1813 case BIT_DF_h: 1814 return is_uint4(m); 1815 case BIT_DF_w: 1816 return is_uint5(m); 1817 case BIT_DF_d: 1818 return is_uint6(m); 1819 default: 1820 return false; 1821 } 1822 } 1823 is_valid_msa_df_n(SecondaryField elm_df,uint32_t n)1824 inline bool is_valid_msa_df_n(SecondaryField elm_df, uint32_t n) { 1825 switch (elm_df) { 1826 case ELM_DF_B: 1827 return is_uint4(n); 1828 case ELM_DF_H: 1829 return is_uint3(n); 1830 case ELM_DF_W: 1831 return is_uint2(n); 1832 case ELM_DF_D: 1833 return is_uint1(n); 1834 default: 1835 return false; 1836 } 1837 } 1838 1839 // Labels. 1840 void print(const Label* L); 1841 void bind_to(Label* L, int pos); 1842 void next(Label* L, bool is_internal); 1843 1844 // One trampoline consists of: 1845 // - space for trampoline slots, 1846 // - space for labels. 1847 // 1848 // Space for trampoline slots is equal to slot_count * 2 * kInstrSize. 1849 // Space for trampoline slots precedes space for labels. Each label is of one 1850 // instruction size, so total amount for labels is equal to 1851 // label_count * kInstrSize. 1852 class Trampoline { 1853 public: Trampoline()1854 Trampoline() { 1855 start_ = 0; 1856 next_slot_ = 0; 1857 free_slot_count_ = 0; 1858 end_ = 0; 1859 } Trampoline(int start,int slot_count)1860 Trampoline(int start, int slot_count) { 1861 start_ = start; 1862 next_slot_ = start; 1863 free_slot_count_ = slot_count; 1864 end_ = start + slot_count * kTrampolineSlotsSize; 1865 } start()1866 int start() { return start_; } end()1867 int end() { return end_; } take_slot()1868 int take_slot() { 1869 int trampoline_slot = kInvalidSlotPos; 1870 if (free_slot_count_ <= 0) { 1871 // We have run out of space on trampolines. 1872 // Make sure we fail in debug mode, so we become aware of each case 1873 // when this happens. 1874 DCHECK(0); 1875 // Internal exception will be caught. 1876 } else { 1877 trampoline_slot = next_slot_; 1878 free_slot_count_--; 1879 next_slot_ += kTrampolineSlotsSize; 1880 } 1881 return trampoline_slot; 1882 } 1883 1884 private: 1885 int start_; 1886 int end_; 1887 int next_slot_; 1888 int free_slot_count_; 1889 }; 1890 1891 int32_t get_trampoline_entry(int32_t pos); 1892 int unbound_labels_count_; 1893 // After trampoline is emitted, long branches are used in generated code for 1894 // the forward branches whose target offsets could be beyond reach of branch 1895 // instruction. We use this information to trigger different mode of 1896 // branch instruction generation, where we use jump instructions rather 1897 // than regular branch instructions. 1898 bool trampoline_emitted_; 1899 static constexpr int kInvalidSlotPos = -1; 1900 1901 // Internal reference positions, required for unbounded internal reference 1902 // labels. 1903 std::set<int64_t> internal_reference_positions_; is_internal_reference(Label * L)1904 bool is_internal_reference(Label* L) { 1905 return internal_reference_positions_.find(L->pos()) != 1906 internal_reference_positions_.end(); 1907 } 1908 EmittedCompactBranchInstruction()1909 void EmittedCompactBranchInstruction() { prev_instr_compact_branch_ = true; } ClearCompactBranchState()1910 void ClearCompactBranchState() { prev_instr_compact_branch_ = false; } 1911 bool prev_instr_compact_branch_ = false; 1912 1913 Trampoline trampoline_; 1914 bool internal_trampoline_exception_; 1915 1916 // Keep track of the last Call's position to ensure that safepoint can get the 1917 // correct information even if there is a trampoline immediately after the 1918 // Call. 1919 byte* last_call_pc_; 1920 1921 RegList scratch_register_list_; 1922 1923 private: 1924 void AllocateAndInstallRequestedHeapObjects(Isolate* isolate); 1925 1926 int WriteCodeComments(); 1927 1928 friend class RegExpMacroAssemblerMIPS; 1929 friend class RelocInfo; 1930 friend class BlockTrampolinePoolScope; 1931 friend class EnsureSpace; 1932 }; 1933 1934 class EnsureSpace { 1935 public: 1936 explicit inline EnsureSpace(Assembler* assembler); 1937 }; 1938 1939 class V8_EXPORT_PRIVATE UseScratchRegisterScope { 1940 public: 1941 explicit UseScratchRegisterScope(Assembler* assembler); 1942 ~UseScratchRegisterScope(); 1943 1944 Register Acquire(); 1945 bool hasAvailable() const; 1946 1947 private: 1948 RegList* available_; 1949 RegList old_available_; 1950 }; 1951 1952 } // namespace internal 1953 } // namespace v8 1954 1955 #endif // V8_CODEGEN_MIPS64_ASSEMBLER_MIPS64_H_ 1956