1 // Copyright 2014 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_COMPILER_BACKEND_IA32_INSTRUCTION_CODES_IA32_H_ 6 #define V8_COMPILER_BACKEND_IA32_INSTRUCTION_CODES_IA32_H_ 7 8 namespace v8 { 9 namespace internal { 10 namespace compiler { 11 12 // IA32-specific opcodes that specify which assembly sequence to emit. 13 // Most opcodes specify a single instruction. 14 #define TARGET_ARCH_OPCODE_LIST(V) \ 15 V(IA32Add) \ 16 V(IA32And) \ 17 V(IA32Cmp) \ 18 V(IA32Cmp16) \ 19 V(IA32Cmp8) \ 20 V(IA32Test) \ 21 V(IA32Test16) \ 22 V(IA32Test8) \ 23 V(IA32Or) \ 24 V(IA32Xor) \ 25 V(IA32Sub) \ 26 V(IA32Imul) \ 27 V(IA32ImulHigh) \ 28 V(IA32UmulHigh) \ 29 V(IA32Idiv) \ 30 V(IA32Udiv) \ 31 V(IA32Not) \ 32 V(IA32Neg) \ 33 V(IA32Shl) \ 34 V(IA32Shr) \ 35 V(IA32Sar) \ 36 V(IA32AddPair) \ 37 V(IA32SubPair) \ 38 V(IA32MulPair) \ 39 V(IA32ShlPair) \ 40 V(IA32ShrPair) \ 41 V(IA32SarPair) \ 42 V(IA32Rol) \ 43 V(IA32Ror) \ 44 V(IA32Lzcnt) \ 45 V(IA32Tzcnt) \ 46 V(IA32Popcnt) \ 47 V(IA32Bswap) \ 48 V(IA32MFence) \ 49 V(IA32LFence) \ 50 V(SSEFloat32Cmp) \ 51 V(SSEFloat32Add) \ 52 V(SSEFloat32Sub) \ 53 V(SSEFloat32Mul) \ 54 V(SSEFloat32Div) \ 55 V(SSEFloat32Abs) \ 56 V(SSEFloat32Neg) \ 57 V(SSEFloat32Sqrt) \ 58 V(SSEFloat32Round) \ 59 V(SSEFloat64Cmp) \ 60 V(SSEFloat64Add) \ 61 V(SSEFloat64Sub) \ 62 V(SSEFloat64Mul) \ 63 V(SSEFloat64Div) \ 64 V(SSEFloat64Mod) \ 65 V(SSEFloat32Max) \ 66 V(SSEFloat64Max) \ 67 V(SSEFloat32Min) \ 68 V(SSEFloat64Min) \ 69 V(SSEFloat64Abs) \ 70 V(SSEFloat64Neg) \ 71 V(SSEFloat64Sqrt) \ 72 V(SSEFloat64Round) \ 73 V(SSEFloat32ToFloat64) \ 74 V(SSEFloat64ToFloat32) \ 75 V(SSEFloat32ToInt32) \ 76 V(SSEFloat32ToUint32) \ 77 V(SSEFloat64ToInt32) \ 78 V(SSEFloat64ToUint32) \ 79 V(SSEInt32ToFloat32) \ 80 V(SSEUint32ToFloat32) \ 81 V(SSEInt32ToFloat64) \ 82 V(SSEUint32ToFloat64) \ 83 V(SSEFloat64ExtractLowWord32) \ 84 V(SSEFloat64ExtractHighWord32) \ 85 V(SSEFloat64InsertLowWord32) \ 86 V(SSEFloat64InsertHighWord32) \ 87 V(SSEFloat64LoadLowWord32) \ 88 V(SSEFloat64SilenceNaN) \ 89 V(AVXFloat32Add) \ 90 V(AVXFloat32Sub) \ 91 V(AVXFloat32Mul) \ 92 V(AVXFloat32Div) \ 93 V(AVXFloat64Add) \ 94 V(AVXFloat64Sub) \ 95 V(AVXFloat64Mul) \ 96 V(AVXFloat64Div) \ 97 V(AVXFloat64Abs) \ 98 V(AVXFloat64Neg) \ 99 V(AVXFloat32Abs) \ 100 V(AVXFloat32Neg) \ 101 V(IA32Movsxbl) \ 102 V(IA32Movzxbl) \ 103 V(IA32Movb) \ 104 V(IA32Movsxwl) \ 105 V(IA32Movzxwl) \ 106 V(IA32Movw) \ 107 V(IA32Movl) \ 108 V(IA32Movss) \ 109 V(IA32Movsd) \ 110 V(IA32Movdqu) \ 111 V(IA32BitcastFI) \ 112 V(IA32BitcastIF) \ 113 V(IA32Lea) \ 114 V(IA32Push) \ 115 V(IA32PushFloat32) \ 116 V(IA32PushFloat64) \ 117 V(IA32PushSimd128) \ 118 V(IA32Poke) \ 119 V(IA32Peek) \ 120 V(SSEF64x2Splat) \ 121 V(AVXF64x2Splat) \ 122 V(SSEF64x2ExtractLane) \ 123 V(AVXF64x2ExtractLane) \ 124 V(SSEF64x2ReplaceLane) \ 125 V(AVXF64x2ReplaceLane) \ 126 V(IA32F64x2Sqrt) \ 127 V(IA32F64x2Add) \ 128 V(IA32F64x2Sub) \ 129 V(IA32F64x2Mul) \ 130 V(IA32F64x2Div) \ 131 V(IA32F64x2Min) \ 132 V(IA32F64x2Max) \ 133 V(IA32F64x2Eq) \ 134 V(IA32F64x2Ne) \ 135 V(IA32F64x2Lt) \ 136 V(IA32F64x2Le) \ 137 V(IA32F64x2Pmin) \ 138 V(IA32F64x2Pmax) \ 139 V(IA32F64x2Round) \ 140 V(IA32I64x2SplatI32Pair) \ 141 V(IA32I64x2ReplaceLaneI32Pair) \ 142 V(IA32I64x2Neg) \ 143 V(IA32I64x2Shl) \ 144 V(IA32I64x2ShrS) \ 145 V(IA32I64x2Add) \ 146 V(IA32I64x2Sub) \ 147 V(IA32I64x2Mul) \ 148 V(IA32I64x2ShrU) \ 149 V(SSEF32x4Splat) \ 150 V(AVXF32x4Splat) \ 151 V(SSEF32x4ExtractLane) \ 152 V(AVXF32x4ExtractLane) \ 153 V(SSEF32x4ReplaceLane) \ 154 V(AVXF32x4ReplaceLane) \ 155 V(IA32F32x4SConvertI32x4) \ 156 V(SSEF32x4UConvertI32x4) \ 157 V(AVXF32x4UConvertI32x4) \ 158 V(SSEF32x4Abs) \ 159 V(AVXF32x4Abs) \ 160 V(SSEF32x4Neg) \ 161 V(AVXF32x4Neg) \ 162 V(SSEF32x4Sqrt) \ 163 V(AVXF32x4Sqrt) \ 164 V(IA32F32x4RecipApprox) \ 165 V(IA32F32x4RecipSqrtApprox) \ 166 V(SSEF32x4Add) \ 167 V(AVXF32x4Add) \ 168 V(SSEF32x4AddHoriz) \ 169 V(AVXF32x4AddHoriz) \ 170 V(SSEF32x4Sub) \ 171 V(AVXF32x4Sub) \ 172 V(SSEF32x4Mul) \ 173 V(AVXF32x4Mul) \ 174 V(SSEF32x4Div) \ 175 V(AVXF32x4Div) \ 176 V(SSEF32x4Min) \ 177 V(AVXF32x4Min) \ 178 V(SSEF32x4Max) \ 179 V(AVXF32x4Max) \ 180 V(SSEF32x4Eq) \ 181 V(AVXF32x4Eq) \ 182 V(SSEF32x4Ne) \ 183 V(AVXF32x4Ne) \ 184 V(SSEF32x4Lt) \ 185 V(AVXF32x4Lt) \ 186 V(SSEF32x4Le) \ 187 V(AVXF32x4Le) \ 188 V(IA32F32x4Pmin) \ 189 V(IA32F32x4Pmax) \ 190 V(IA32F32x4Round) \ 191 V(IA32I32x4Splat) \ 192 V(IA32I32x4ExtractLane) \ 193 V(SSEI32x4ReplaceLane) \ 194 V(AVXI32x4ReplaceLane) \ 195 V(SSEI32x4SConvertF32x4) \ 196 V(AVXI32x4SConvertF32x4) \ 197 V(IA32I32x4SConvertI16x8Low) \ 198 V(IA32I32x4SConvertI16x8High) \ 199 V(IA32I32x4Neg) \ 200 V(IA32I32x4Shl) \ 201 V(IA32I32x4ShrS) \ 202 V(SSEI32x4Add) \ 203 V(AVXI32x4Add) \ 204 V(SSEI32x4AddHoriz) \ 205 V(AVXI32x4AddHoriz) \ 206 V(SSEI32x4Sub) \ 207 V(AVXI32x4Sub) \ 208 V(SSEI32x4Mul) \ 209 V(AVXI32x4Mul) \ 210 V(SSEI32x4MinS) \ 211 V(AVXI32x4MinS) \ 212 V(SSEI32x4MaxS) \ 213 V(AVXI32x4MaxS) \ 214 V(SSEI32x4Eq) \ 215 V(AVXI32x4Eq) \ 216 V(SSEI32x4Ne) \ 217 V(AVXI32x4Ne) \ 218 V(SSEI32x4GtS) \ 219 V(AVXI32x4GtS) \ 220 V(SSEI32x4GeS) \ 221 V(AVXI32x4GeS) \ 222 V(SSEI32x4UConvertF32x4) \ 223 V(AVXI32x4UConvertF32x4) \ 224 V(IA32I32x4UConvertI16x8Low) \ 225 V(IA32I32x4UConvertI16x8High) \ 226 V(IA32I32x4ShrU) \ 227 V(SSEI32x4MinU) \ 228 V(AVXI32x4MinU) \ 229 V(SSEI32x4MaxU) \ 230 V(AVXI32x4MaxU) \ 231 V(SSEI32x4GtU) \ 232 V(AVXI32x4GtU) \ 233 V(SSEI32x4GeU) \ 234 V(AVXI32x4GeU) \ 235 V(IA32I32x4Abs) \ 236 V(IA32I32x4BitMask) \ 237 V(IA32I32x4DotI16x8S) \ 238 V(IA32I16x8Splat) \ 239 V(IA32I16x8ExtractLaneU) \ 240 V(IA32I16x8ExtractLaneS) \ 241 V(SSEI16x8ReplaceLane) \ 242 V(AVXI16x8ReplaceLane) \ 243 V(IA32I16x8SConvertI8x16Low) \ 244 V(IA32I16x8SConvertI8x16High) \ 245 V(IA32I16x8Neg) \ 246 V(IA32I16x8Shl) \ 247 V(IA32I16x8ShrS) \ 248 V(SSEI16x8SConvertI32x4) \ 249 V(AVXI16x8SConvertI32x4) \ 250 V(SSEI16x8Add) \ 251 V(AVXI16x8Add) \ 252 V(SSEI16x8AddSatS) \ 253 V(AVXI16x8AddSatS) \ 254 V(SSEI16x8AddHoriz) \ 255 V(AVXI16x8AddHoriz) \ 256 V(SSEI16x8Sub) \ 257 V(AVXI16x8Sub) \ 258 V(SSEI16x8SubSatS) \ 259 V(AVXI16x8SubSatS) \ 260 V(SSEI16x8Mul) \ 261 V(AVXI16x8Mul) \ 262 V(SSEI16x8MinS) \ 263 V(AVXI16x8MinS) \ 264 V(SSEI16x8MaxS) \ 265 V(AVXI16x8MaxS) \ 266 V(SSEI16x8Eq) \ 267 V(AVXI16x8Eq) \ 268 V(SSEI16x8Ne) \ 269 V(AVXI16x8Ne) \ 270 V(SSEI16x8GtS) \ 271 V(AVXI16x8GtS) \ 272 V(SSEI16x8GeS) \ 273 V(AVXI16x8GeS) \ 274 V(IA32I16x8UConvertI8x16Low) \ 275 V(IA32I16x8UConvertI8x16High) \ 276 V(IA32I16x8ShrU) \ 277 V(SSEI16x8UConvertI32x4) \ 278 V(AVXI16x8UConvertI32x4) \ 279 V(SSEI16x8AddSatU) \ 280 V(AVXI16x8AddSatU) \ 281 V(SSEI16x8SubSatU) \ 282 V(AVXI16x8SubSatU) \ 283 V(SSEI16x8MinU) \ 284 V(AVXI16x8MinU) \ 285 V(SSEI16x8MaxU) \ 286 V(AVXI16x8MaxU) \ 287 V(SSEI16x8GtU) \ 288 V(AVXI16x8GtU) \ 289 V(SSEI16x8GeU) \ 290 V(AVXI16x8GeU) \ 291 V(IA32I16x8RoundingAverageU) \ 292 V(IA32I16x8Abs) \ 293 V(IA32I16x8BitMask) \ 294 V(IA32I8x16Splat) \ 295 V(IA32I8x16ExtractLaneU) \ 296 V(IA32I8x16ExtractLaneS) \ 297 V(SSEI8x16ReplaceLane) \ 298 V(AVXI8x16ReplaceLane) \ 299 V(SSEI8x16SConvertI16x8) \ 300 V(AVXI8x16SConvertI16x8) \ 301 V(IA32I8x16Neg) \ 302 V(IA32I8x16Shl) \ 303 V(IA32I8x16ShrS) \ 304 V(SSEI8x16Add) \ 305 V(AVXI8x16Add) \ 306 V(SSEI8x16AddSatS) \ 307 V(AVXI8x16AddSatS) \ 308 V(SSEI8x16Sub) \ 309 V(AVXI8x16Sub) \ 310 V(SSEI8x16SubSatS) \ 311 V(AVXI8x16SubSatS) \ 312 V(SSEI8x16Mul) \ 313 V(AVXI8x16Mul) \ 314 V(SSEI8x16MinS) \ 315 V(AVXI8x16MinS) \ 316 V(SSEI8x16MaxS) \ 317 V(AVXI8x16MaxS) \ 318 V(SSEI8x16Eq) \ 319 V(AVXI8x16Eq) \ 320 V(SSEI8x16Ne) \ 321 V(AVXI8x16Ne) \ 322 V(SSEI8x16GtS) \ 323 V(AVXI8x16GtS) \ 324 V(SSEI8x16GeS) \ 325 V(AVXI8x16GeS) \ 326 V(SSEI8x16UConvertI16x8) \ 327 V(AVXI8x16UConvertI16x8) \ 328 V(SSEI8x16AddSatU) \ 329 V(AVXI8x16AddSatU) \ 330 V(SSEI8x16SubSatU) \ 331 V(AVXI8x16SubSatU) \ 332 V(IA32I8x16ShrU) \ 333 V(SSEI8x16MinU) \ 334 V(AVXI8x16MinU) \ 335 V(SSEI8x16MaxU) \ 336 V(AVXI8x16MaxU) \ 337 V(SSEI8x16GtU) \ 338 V(AVXI8x16GtU) \ 339 V(SSEI8x16GeU) \ 340 V(AVXI8x16GeU) \ 341 V(IA32I8x16RoundingAverageU) \ 342 V(IA32I8x16Abs) \ 343 V(IA32I8x16BitMask) \ 344 V(IA32S128Const) \ 345 V(IA32S128Zero) \ 346 V(IA32S128AllOnes) \ 347 V(SSES128Not) \ 348 V(AVXS128Not) \ 349 V(SSES128And) \ 350 V(AVXS128And) \ 351 V(SSES128Or) \ 352 V(AVXS128Or) \ 353 V(SSES128Xor) \ 354 V(AVXS128Xor) \ 355 V(SSES128Select) \ 356 V(AVXS128Select) \ 357 V(IA32S128AndNot) \ 358 V(IA32I8x16Swizzle) \ 359 V(IA32I8x16Shuffle) \ 360 V(IA32S128Load8Splat) \ 361 V(IA32S128Load16Splat) \ 362 V(IA32S128Load32Splat) \ 363 V(IA32S128Load64Splat) \ 364 V(IA32S128Load8x8S) \ 365 V(IA32S128Load8x8U) \ 366 V(IA32S128Load16x4S) \ 367 V(IA32S128Load16x4U) \ 368 V(IA32S128Load32x2S) \ 369 V(IA32S128Load32x2U) \ 370 V(IA32S32x4Swizzle) \ 371 V(IA32S32x4Shuffle) \ 372 V(IA32S16x8Blend) \ 373 V(IA32S16x8HalfShuffle1) \ 374 V(IA32S16x8HalfShuffle2) \ 375 V(IA32S8x16Alignr) \ 376 V(IA32S16x8Dup) \ 377 V(IA32S8x16Dup) \ 378 V(SSES16x8UnzipHigh) \ 379 V(AVXS16x8UnzipHigh) \ 380 V(SSES16x8UnzipLow) \ 381 V(AVXS16x8UnzipLow) \ 382 V(SSES8x16UnzipHigh) \ 383 V(AVXS8x16UnzipHigh) \ 384 V(SSES8x16UnzipLow) \ 385 V(AVXS8x16UnzipLow) \ 386 V(IA32S64x2UnpackHigh) \ 387 V(IA32S32x4UnpackHigh) \ 388 V(IA32S16x8UnpackHigh) \ 389 V(IA32S8x16UnpackHigh) \ 390 V(IA32S64x2UnpackLow) \ 391 V(IA32S32x4UnpackLow) \ 392 V(IA32S16x8UnpackLow) \ 393 V(IA32S8x16UnpackLow) \ 394 V(SSES8x16TransposeLow) \ 395 V(AVXS8x16TransposeLow) \ 396 V(SSES8x16TransposeHigh) \ 397 V(AVXS8x16TransposeHigh) \ 398 V(SSES8x8Reverse) \ 399 V(AVXS8x8Reverse) \ 400 V(SSES8x4Reverse) \ 401 V(AVXS8x4Reverse) \ 402 V(SSES8x2Reverse) \ 403 V(AVXS8x2Reverse) \ 404 V(IA32V32x4AnyTrue) \ 405 V(IA32V32x4AllTrue) \ 406 V(IA32V16x8AnyTrue) \ 407 V(IA32V16x8AllTrue) \ 408 V(IA32V8x16AnyTrue) \ 409 V(IA32V8x16AllTrue) \ 410 V(IA32Word32AtomicPairLoad) \ 411 V(IA32Word32AtomicPairStore) \ 412 V(IA32Word32AtomicPairAdd) \ 413 V(IA32Word32AtomicPairSub) \ 414 V(IA32Word32AtomicPairAnd) \ 415 V(IA32Word32AtomicPairOr) \ 416 V(IA32Word32AtomicPairXor) \ 417 V(IA32Word32AtomicPairExchange) \ 418 V(IA32Word32AtomicPairCompareExchange) 419 420 // Addressing modes represent the "shape" of inputs to an instruction. 421 // Many instructions support multiple addressing modes. Addressing modes 422 // are encoded into the InstructionCode of the instruction and tell the 423 // code generator after register allocation which assembler method to call. 424 // 425 // We use the following local notation for addressing modes: 426 // 427 // M = memory operand 428 // R = base register 429 // N = index register * N for N in {1, 2, 4, 8} 430 // I = immediate displacement (int32_t) 431 432 #define TARGET_ADDRESSING_MODE_LIST(V) \ 433 V(MR) /* [%r1 ] */ \ 434 V(MRI) /* [%r1 + K] */ \ 435 V(MR1) /* [%r1 + %r2*1 ] */ \ 436 V(MR2) /* [%r1 + %r2*2 ] */ \ 437 V(MR4) /* [%r1 + %r2*4 ] */ \ 438 V(MR8) /* [%r1 + %r2*8 ] */ \ 439 V(MR1I) /* [%r1 + %r2*1 + K] */ \ 440 V(MR2I) /* [%r1 + %r2*2 + K] */ \ 441 V(MR4I) /* [%r1 + %r2*3 + K] */ \ 442 V(MR8I) /* [%r1 + %r2*4 + K] */ \ 443 V(M1) /* [ %r2*1 ] */ \ 444 V(M2) /* [ %r2*2 ] */ \ 445 V(M4) /* [ %r2*4 ] */ \ 446 V(M8) /* [ %r2*8 ] */ \ 447 V(M1I) /* [ %r2*1 + K] */ \ 448 V(M2I) /* [ %r2*2 + K] */ \ 449 V(M4I) /* [ %r2*4 + K] */ \ 450 V(M8I) /* [ %r2*8 + K] */ \ 451 V(MI) /* [ K] */ \ 452 V(Root) /* [%root + K] */ 453 454 } // namespace compiler 455 } // namespace internal 456 } // namespace v8 457 458 #endif // V8_COMPILER_BACKEND_IA32_INSTRUCTION_CODES_IA32_H_ 459