1 // Copyright 2014 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_COMPILER_BACKEND_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_BACKEND_MIPS_INSTRUCTION_CODES_MIPS_H_ 7 8 namespace v8 { 9 namespace internal { 10 namespace compiler { 11 12 // MIPS-specific opcodes that specify which assembly sequence to emit. 13 // Most opcodes specify a single instruction. 14 #define TARGET_ARCH_OPCODE_LIST(V) \ 15 V(MipsAdd) \ 16 V(MipsAddOvf) \ 17 V(MipsSub) \ 18 V(MipsSubOvf) \ 19 V(MipsMul) \ 20 V(MipsMulOvf) \ 21 V(MipsMulHigh) \ 22 V(MipsMulHighU) \ 23 V(MipsDiv) \ 24 V(MipsDivU) \ 25 V(MipsMod) \ 26 V(MipsModU) \ 27 V(MipsAnd) \ 28 V(MipsOr) \ 29 V(MipsNor) \ 30 V(MipsXor) \ 31 V(MipsClz) \ 32 V(MipsCtz) \ 33 V(MipsPopcnt) \ 34 V(MipsLsa) \ 35 V(MipsShl) \ 36 V(MipsShr) \ 37 V(MipsSar) \ 38 V(MipsShlPair) \ 39 V(MipsShrPair) \ 40 V(MipsSarPair) \ 41 V(MipsExt) \ 42 V(MipsIns) \ 43 V(MipsRor) \ 44 V(MipsMov) \ 45 V(MipsTst) \ 46 V(MipsCmp) \ 47 V(MipsCmpS) \ 48 V(MipsAddS) \ 49 V(MipsSubS) \ 50 V(MipsMulS) \ 51 V(MipsDivS) \ 52 V(MipsModS) \ 53 V(MipsAbsS) \ 54 V(MipsSqrtS) \ 55 V(MipsMaxS) \ 56 V(MipsMinS) \ 57 V(MipsCmpD) \ 58 V(MipsAddD) \ 59 V(MipsSubD) \ 60 V(MipsMulD) \ 61 V(MipsDivD) \ 62 V(MipsModD) \ 63 V(MipsAbsD) \ 64 V(MipsSqrtD) \ 65 V(MipsMaxD) \ 66 V(MipsMinD) \ 67 V(MipsNegS) \ 68 V(MipsNegD) \ 69 V(MipsAddPair) \ 70 V(MipsSubPair) \ 71 V(MipsMulPair) \ 72 V(MipsMaddS) \ 73 V(MipsMaddD) \ 74 V(MipsMsubS) \ 75 V(MipsMsubD) \ 76 V(MipsFloat32RoundDown) \ 77 V(MipsFloat32RoundTruncate) \ 78 V(MipsFloat32RoundUp) \ 79 V(MipsFloat32RoundTiesEven) \ 80 V(MipsFloat64RoundDown) \ 81 V(MipsFloat64RoundTruncate) \ 82 V(MipsFloat64RoundUp) \ 83 V(MipsFloat64RoundTiesEven) \ 84 V(MipsCvtSD) \ 85 V(MipsCvtDS) \ 86 V(MipsTruncWD) \ 87 V(MipsRoundWD) \ 88 V(MipsFloorWD) \ 89 V(MipsCeilWD) \ 90 V(MipsTruncWS) \ 91 V(MipsRoundWS) \ 92 V(MipsFloorWS) \ 93 V(MipsCeilWS) \ 94 V(MipsTruncUwD) \ 95 V(MipsTruncUwS) \ 96 V(MipsCvtDW) \ 97 V(MipsCvtDUw) \ 98 V(MipsCvtSW) \ 99 V(MipsCvtSUw) \ 100 V(MipsLb) \ 101 V(MipsLbu) \ 102 V(MipsSb) \ 103 V(MipsLh) \ 104 V(MipsUlh) \ 105 V(MipsLhu) \ 106 V(MipsUlhu) \ 107 V(MipsSh) \ 108 V(MipsUsh) \ 109 V(MipsLw) \ 110 V(MipsUlw) \ 111 V(MipsSw) \ 112 V(MipsUsw) \ 113 V(MipsLwc1) \ 114 V(MipsUlwc1) \ 115 V(MipsSwc1) \ 116 V(MipsUswc1) \ 117 V(MipsLdc1) \ 118 V(MipsUldc1) \ 119 V(MipsSdc1) \ 120 V(MipsUsdc1) \ 121 V(MipsFloat64ExtractLowWord32) \ 122 V(MipsFloat64ExtractHighWord32) \ 123 V(MipsFloat64InsertLowWord32) \ 124 V(MipsFloat64InsertHighWord32) \ 125 V(MipsFloat64SilenceNaN) \ 126 V(MipsFloat32Max) \ 127 V(MipsFloat64Max) \ 128 V(MipsFloat32Min) \ 129 V(MipsFloat64Min) \ 130 V(MipsPush) \ 131 V(MipsPeek) \ 132 V(MipsStoreToStackSlot) \ 133 V(MipsByteSwap32) \ 134 V(MipsStackClaim) \ 135 V(MipsSeb) \ 136 V(MipsSeh) \ 137 V(MipsSync) \ 138 V(MipsS128Zero) \ 139 V(MipsI32x4Splat) \ 140 V(MipsI32x4ExtractLane) \ 141 V(MipsI32x4ReplaceLane) \ 142 V(MipsI32x4Add) \ 143 V(MipsI32x4AddHoriz) \ 144 V(MipsI32x4Sub) \ 145 V(MipsF64x2Abs) \ 146 V(MipsF64x2Neg) \ 147 V(MipsF64x2Sqrt) \ 148 V(MipsF64x2Add) \ 149 V(MipsF64x2Sub) \ 150 V(MipsF64x2Mul) \ 151 V(MipsF64x2Div) \ 152 V(MipsF64x2Min) \ 153 V(MipsF64x2Max) \ 154 V(MipsF64x2Eq) \ 155 V(MipsF64x2Ne) \ 156 V(MipsF64x2Lt) \ 157 V(MipsF64x2Le) \ 158 V(MipsF64x2Pmin) \ 159 V(MipsF64x2Pmax) \ 160 V(MipsF64x2Ceil) \ 161 V(MipsF64x2Floor) \ 162 V(MipsF64x2Trunc) \ 163 V(MipsF64x2NearestInt) \ 164 V(MipsI64x2Add) \ 165 V(MipsI64x2Sub) \ 166 V(MipsI64x2Mul) \ 167 V(MipsI64x2Neg) \ 168 V(MipsI64x2Shl) \ 169 V(MipsI64x2ShrS) \ 170 V(MipsI64x2ShrU) \ 171 V(MipsF32x4Splat) \ 172 V(MipsF32x4ExtractLane) \ 173 V(MipsF32x4ReplaceLane) \ 174 V(MipsF32x4SConvertI32x4) \ 175 V(MipsF32x4UConvertI32x4) \ 176 V(MipsI32x4Mul) \ 177 V(MipsI32x4MaxS) \ 178 V(MipsI32x4MinS) \ 179 V(MipsI32x4Eq) \ 180 V(MipsI32x4Ne) \ 181 V(MipsI32x4Shl) \ 182 V(MipsI32x4ShrS) \ 183 V(MipsI32x4ShrU) \ 184 V(MipsI32x4MaxU) \ 185 V(MipsI32x4MinU) \ 186 V(MipsF64x2Splat) \ 187 V(MipsF64x2ExtractLane) \ 188 V(MipsF64x2ReplaceLane) \ 189 V(MipsF32x4Abs) \ 190 V(MipsF32x4Neg) \ 191 V(MipsF32x4Sqrt) \ 192 V(MipsF32x4RecipApprox) \ 193 V(MipsF32x4RecipSqrtApprox) \ 194 V(MipsF32x4Add) \ 195 V(MipsF32x4AddHoriz) \ 196 V(MipsF32x4Sub) \ 197 V(MipsF32x4Mul) \ 198 V(MipsF32x4Div) \ 199 V(MipsF32x4Max) \ 200 V(MipsF32x4Min) \ 201 V(MipsF32x4Eq) \ 202 V(MipsF32x4Ne) \ 203 V(MipsF32x4Lt) \ 204 V(MipsF32x4Le) \ 205 V(MipsF32x4Pmin) \ 206 V(MipsF32x4Pmax) \ 207 V(MipsF32x4Ceil) \ 208 V(MipsF32x4Floor) \ 209 V(MipsF32x4Trunc) \ 210 V(MipsF32x4NearestInt) \ 211 V(MipsI32x4SConvertF32x4) \ 212 V(MipsI32x4UConvertF32x4) \ 213 V(MipsI32x4Neg) \ 214 V(MipsI32x4GtS) \ 215 V(MipsI32x4GeS) \ 216 V(MipsI32x4GtU) \ 217 V(MipsI32x4GeU) \ 218 V(MipsI32x4Abs) \ 219 V(MipsI32x4BitMask) \ 220 V(MipsI32x4DotI16x8S) \ 221 V(MipsI16x8Splat) \ 222 V(MipsI16x8ExtractLaneU) \ 223 V(MipsI16x8ExtractLaneS) \ 224 V(MipsI16x8ReplaceLane) \ 225 V(MipsI16x8Neg) \ 226 V(MipsI16x8Shl) \ 227 V(MipsI16x8ShrS) \ 228 V(MipsI16x8ShrU) \ 229 V(MipsI16x8Add) \ 230 V(MipsI16x8AddSatS) \ 231 V(MipsI16x8AddHoriz) \ 232 V(MipsI16x8Sub) \ 233 V(MipsI16x8SubSatS) \ 234 V(MipsI16x8Mul) \ 235 V(MipsI16x8MaxS) \ 236 V(MipsI16x8MinS) \ 237 V(MipsI16x8Eq) \ 238 V(MipsI16x8Ne) \ 239 V(MipsI16x8GtS) \ 240 V(MipsI16x8GeS) \ 241 V(MipsI16x8AddSatU) \ 242 V(MipsI16x8SubSatU) \ 243 V(MipsI16x8MaxU) \ 244 V(MipsI16x8MinU) \ 245 V(MipsI16x8GtU) \ 246 V(MipsI16x8GeU) \ 247 V(MipsI16x8RoundingAverageU) \ 248 V(MipsI16x8Abs) \ 249 V(MipsI16x8BitMask) \ 250 V(MipsI8x16Splat) \ 251 V(MipsI8x16ExtractLaneU) \ 252 V(MipsI8x16ExtractLaneS) \ 253 V(MipsI8x16ReplaceLane) \ 254 V(MipsI8x16Neg) \ 255 V(MipsI8x16Shl) \ 256 V(MipsI8x16ShrS) \ 257 V(MipsI8x16Add) \ 258 V(MipsI8x16AddSatS) \ 259 V(MipsI8x16Sub) \ 260 V(MipsI8x16SubSatS) \ 261 V(MipsI8x16Mul) \ 262 V(MipsI8x16MaxS) \ 263 V(MipsI8x16MinS) \ 264 V(MipsI8x16Eq) \ 265 V(MipsI8x16Ne) \ 266 V(MipsI8x16GtS) \ 267 V(MipsI8x16GeS) \ 268 V(MipsI8x16ShrU) \ 269 V(MipsI8x16AddSatU) \ 270 V(MipsI8x16SubSatU) \ 271 V(MipsI8x16MaxU) \ 272 V(MipsI8x16MinU) \ 273 V(MipsI8x16GtU) \ 274 V(MipsI8x16GeU) \ 275 V(MipsI8x16RoundingAverageU) \ 276 V(MipsI8x16Abs) \ 277 V(MipsI8x16BitMask) \ 278 V(MipsS128And) \ 279 V(MipsS128Or) \ 280 V(MipsS128Xor) \ 281 V(MipsS128Not) \ 282 V(MipsS128Select) \ 283 V(MipsS128AndNot) \ 284 V(MipsV32x4AnyTrue) \ 285 V(MipsV32x4AllTrue) \ 286 V(MipsV16x8AnyTrue) \ 287 V(MipsV16x8AllTrue) \ 288 V(MipsV8x16AnyTrue) \ 289 V(MipsV8x16AllTrue) \ 290 V(MipsS32x4InterleaveRight) \ 291 V(MipsS32x4InterleaveLeft) \ 292 V(MipsS32x4PackEven) \ 293 V(MipsS32x4PackOdd) \ 294 V(MipsS32x4InterleaveEven) \ 295 V(MipsS32x4InterleaveOdd) \ 296 V(MipsS32x4Shuffle) \ 297 V(MipsS16x8InterleaveRight) \ 298 V(MipsS16x8InterleaveLeft) \ 299 V(MipsS16x8PackEven) \ 300 V(MipsS16x8PackOdd) \ 301 V(MipsS16x8InterleaveEven) \ 302 V(MipsS16x8InterleaveOdd) \ 303 V(MipsS16x4Reverse) \ 304 V(MipsS16x2Reverse) \ 305 V(MipsS8x16InterleaveRight) \ 306 V(MipsS8x16InterleaveLeft) \ 307 V(MipsS8x16PackEven) \ 308 V(MipsS8x16PackOdd) \ 309 V(MipsS8x16InterleaveEven) \ 310 V(MipsS8x16InterleaveOdd) \ 311 V(MipsI8x16Shuffle) \ 312 V(MipsI8x16Swizzle) \ 313 V(MipsS8x16Concat) \ 314 V(MipsS8x8Reverse) \ 315 V(MipsS8x4Reverse) \ 316 V(MipsS8x2Reverse) \ 317 V(MipsS128Load8Splat) \ 318 V(MipsS128Load16Splat) \ 319 V(MipsS128Load32Splat) \ 320 V(MipsS128Load64Splat) \ 321 V(MipsS128Load8x8S) \ 322 V(MipsS128Load8x8U) \ 323 V(MipsS128Load16x4S) \ 324 V(MipsS128Load16x4U) \ 325 V(MipsS128Load32x2S) \ 326 V(MipsS128Load32x2U) \ 327 V(MipsMsaLd) \ 328 V(MipsMsaSt) \ 329 V(MipsI32x4SConvertI16x8Low) \ 330 V(MipsI32x4SConvertI16x8High) \ 331 V(MipsI32x4UConvertI16x8Low) \ 332 V(MipsI32x4UConvertI16x8High) \ 333 V(MipsI16x8SConvertI8x16Low) \ 334 V(MipsI16x8SConvertI8x16High) \ 335 V(MipsI16x8SConvertI32x4) \ 336 V(MipsI16x8UConvertI32x4) \ 337 V(MipsI16x8UConvertI8x16Low) \ 338 V(MipsI16x8UConvertI8x16High) \ 339 V(MipsI8x16SConvertI16x8) \ 340 V(MipsI8x16UConvertI16x8) \ 341 V(MipsWord32AtomicPairLoad) \ 342 V(MipsWord32AtomicPairStore) \ 343 V(MipsWord32AtomicPairAdd) \ 344 V(MipsWord32AtomicPairSub) \ 345 V(MipsWord32AtomicPairAnd) \ 346 V(MipsWord32AtomicPairOr) \ 347 V(MipsWord32AtomicPairXor) \ 348 V(MipsWord32AtomicPairExchange) \ 349 V(MipsWord32AtomicPairCompareExchange) 350 351 // Addressing modes represent the "shape" of inputs to an instruction. 352 // Many instructions support multiple addressing modes. Addressing modes 353 // are encoded into the InstructionCode of the instruction and tell the 354 // code generator after register allocation which assembler method to call. 355 // 356 // We use the following local notation for addressing modes: 357 // 358 // R = register 359 // O = register or stack slot 360 // D = double register 361 // I = immediate (handle, external, int32) 362 // MRI = [register + immediate] 363 // MRR = [register + register] 364 // TODO(plind): Add the new r6 address modes. 365 #define TARGET_ADDRESSING_MODE_LIST(V) \ 366 V(MRI) /* [%r0 + K] */ \ 367 V(MRR) /* [%r0 + %r1] */ 368 369 } // namespace compiler 370 } // namespace internal 371 } // namespace v8 372 373 #endif // V8_COMPILER_BACKEND_MIPS_INSTRUCTION_CODES_MIPS_H_ 374