Searched refs:first_reg (Results 1 – 6 of 6) sorted by relevance
| /art/runtime/gc/space/ |
| D | region_space-inl.h | 410 Region* first_reg = ®ions_[left]; in AllocLargeInRange() local
411 DCHECK(first_reg->IsFree()); in AllocLargeInRange()
412 first_reg->UnfreeLarge(this, time_); in AllocLargeInRange()
421 first_reg->SetTop(first_reg->Begin() + allocated); in AllocLargeInRange()
424 first_reg->SetNewlyAllocated(); in AllocLargeInRange()
445 mirror::Object* large_region = reinterpret_cast<mirror::Object*>(first_reg->Begin()); in AllocLargeInRange()
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| /art/libdexfile/dex/ |
| D | dex_instruction.cc | 429 uint16_t first_reg = VRegC_3rc(); in DumpString() local
439 os << StringPrintf("%s, {v%d .. v%d}, ", opcode, first_reg, last_reg) in DumpString()
447 os << StringPrintf("%s, {v%d .. v%d}, ", opcode, first_reg, last_reg) in DumpString()
455 os << StringPrintf("%s, {v%d .. v%d}, ", opcode, first_reg, last_reg) in DumpString()
461 os << StringPrintf("%s, {v%d .. v%d}, ", opcode, first_reg, last_reg) in DumpString()
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| /art/compiler/optimizing/ |
| D | code_generator_x86_64.cc | 4366 CpuRegister first_reg = locations->InAt(0).AsRegister<CpuRegister>(); in HandleShift() local
4374 __ shll(first_reg, second_reg); in HandleShift()
4376 __ sarl(first_reg, second_reg); in HandleShift()
4378 __ shrl(first_reg, second_reg); in HandleShift()
4383 __ shll(first_reg, imm); in HandleShift()
4385 __ sarl(first_reg, imm); in HandleShift()
4387 __ shrl(first_reg, imm); in HandleShift()
4396 __ shlq(first_reg, second_reg); in HandleShift()
4398 __ sarq(first_reg, second_reg); in HandleShift()
4400 __ shrq(first_reg, second_reg); in HandleShift()
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| D | instruction_builder.h | 134 uint16_t first_reg,
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| D | code_generator_arm_vixl.cc | 5019 vixl32::Register first_reg = InputRegisterAt(op, 0); in HandleShift() local
5025 __ Lsl(out_reg, first_reg, out_reg); in HandleShift()
5027 __ Asr(out_reg, first_reg, out_reg); in HandleShift()
5029 __ Lsr(out_reg, first_reg, out_reg); in HandleShift()
5035 __ Mov(out_reg, first_reg); in HandleShift()
5037 __ Lsl(out_reg, first_reg, shift_value); in HandleShift()
5039 __ Asr(out_reg, first_reg, shift_value); in HandleShift()
5041 __ Lsr(out_reg, first_reg, shift_value); in HandleShift()
8173 vixl32::Register first_reg = RegisterFrom(first); in VisitBitwiseNegatedRight() local
8179 __ Bic(out_reg, first_reg, second_reg); in VisitBitwiseNegatedRight()
[all …]
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| D | code_generator_x86.cc | 4375 Register first_reg = first.AsRegister<Register>(); in HandleShift() local
4380 __ shll(first_reg, second_reg); in HandleShift()
4382 __ sarl(first_reg, second_reg); in HandleShift()
4384 __ shrl(first_reg, second_reg); in HandleShift()
4393 __ shll(first_reg, imm); in HandleShift()
4395 __ sarl(first_reg, imm); in HandleShift()
4397 __ shrl(first_reg, imm); in HandleShift()
4567 Register first_reg = first.AsRegister<Register>(); in VisitRor() local
4570 __ rorl(first_reg, second_reg); in VisitRor()
4573 __ rorl(first_reg, imm); in VisitRor()
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