Searched refs:BIT15 (Results 1 – 25 of 66) sorted by relevance
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43 #define CM_FCLKEN1_CORE_EN_I2C1_MASK BIT1545 #define CM_FCLKEN1_CORE_EN_I2C1_ENABLE BIT1547 #define CM_ICLKEN1_CORE_EN_I2C1_MASK BIT1549 #define CM_ICLKEN1_CORE_EN_I2C1_ENABLE BIT15118 #define CM_FCLKEN_PER_EN_GPIO4_ENABLE BIT15143 #define CM_ICLKEN_PER_EN_GPIO4_ENABLE BIT15
102 #define DMA4_CCR_DST_AMODE_SINGLE_INDEX (BIT15 | 0)103 #define DMA4_CCR_DST_AMODE_DOUBLE_INDEX (BIT15 | BIT14)
47 #define I2C_EN BIT15
46 #define B_PCH_SPI_HSFS_FLOCKDN BIT15 // Flash Configuration Lock-Down62 #define B_PCH_SPI_PR0_RPE BIT15 // Read Protection Enable68 #define B_PCH_SPI_PR1_RPE BIT15 // Read Protection Enable76 #define B_PCH_SPI_OPTYPE7_MASK (BIT15 | BIT14) // Opcode Type 7 Mask
68 #define B_PCH_EHCI_PWR_CNTL_STS_PME_STS BIT15 // PME Status91 #define B_PCH_XHCI_PWR_CNTL_STS_PME_STS BIT15
88 #define B_PCH_LPC_DEV_STS_DPE BIT15 // Detected Parity Error195 #define B_PCH_LPC_FWH_BIOS_DEC_EF8 BIT15 // F8-FF Enable464 #define B_PCH_ACPI_PM1_STS_WAK BIT15 // Wake Status591 #define B_PCH_SMI_STS_ILB BIT15 // ILB SMI Status666 #define B_PCH_PMC_PRSTS_PM_WD_TMR BIT15 // PMC Watchdog Timer Status701 #define B_PCH_PMC_GEN_PMCON_PME_B0_S5_DIS BIT15 // PME B0 S5 Disable762 #define B_PCH_PMC_FUNC_DIS_USH BIT15 // USH (USB3) Disable802 #define B_PCH_PMC_GPI_ROUT_7 (BIT15 | BIT14)855 #define B_PCH_PMC_PSS_PG_STS_OTG_VCCACLK BIT15 // OTG VCCACLK885 #define B_PCH_PMC_D3_STS_0_USH BIT15 // USH[all …]
119 #define B_PCH_LPSS_DMAC_PCS_PMESTS BIT15 // PME Status204 #define B_PCH_LPSS_I2C_PCS_PMESTS BIT15 // PME Status291 #define B_PCH_LPSS_PWM_PCS_PMESTS BIT15 // PME Status378 #define B_PCH_LPSS_HSUART_PCS_PMESTS BIT15 // PME Status470 #define B_PCH_LPSS_SPI_PCS_PMESTS BIT15 // PME Status
80 #define B_PCH_SATA_PCISTS_DPE BIT15 // Detected Parity Error160 #define B_PCH_SATA_PMCS_PMES BIT15 // PME Status186 #define B_PCH_SATA_PCS_OOB_RETRY BIT15 // OOB Retry Mode
50 #define B_PCH_HDA_PCS_PMES BIT15 // PME Status
84 #define TCR_SWFDUP BIT15112 #define RCR_SOFT_RST BIT15132 #define CR_EPH_POWER_EN BIT15173 #define FIFO_REMPTY BIT15180 #define PTR_RCV BIT15210 #define RX_ALGN_ERR BIT15252 #define PHYCR_RESET BIT15 // Do a PHY reset265 #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability
144 #define RXSTATUS_ES BIT15 // Reports any error from b…157 #define TXSTATUS_ES BIT15 // Reports any errors from …184 #define INSTS_RWT BIT15 // Packet > 2048 bytes receiv…226 #define PHYCR_RESET BIT15 // Do a PHY reset239 #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability280 #define MACCR_HO BIT15 // Hash Only Filtering Mode299 #define RXCFG_RX_DUMP BIT15 // Clear Rx data and status FIFOs309 #define TXCFG_TXS_DUMP BIT15 // Clear Tx Status FIFO
32 #undef BIT1568 #define BIT15 0x00008000U macro
62 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19)63 #define B_BOARD_FEATURES_FORM_FACTOR_PBTX BIT15156 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19|BIT20)157 #define B_BOARD_FEATURES_FORM_FACTOR_PBTX BIT15
70 #define ERROR_INVALID_API (BIT31 | BIT17 | BIT16 | BIT15 | 0x0001)71 #define ERROR_INVALID_PARAMETER (BIT31 | BIT17 | BIT16 | BIT15 | 0x0002)
157 #define TS_ENABLE (BIT15)446 #define B_QNC_PM1BLK_PM1S_ALL (BIT15+BIT14+BIT10+BIT5+BIT0)447 #define B_QNC_PM1BLK_PM1S_WAKE (BIT15)658 #define B_QNC_PCIE_LCAP_EL1_MASK (BIT17 | BIT16 | BIT15) //L1 Exit latency mask689 #define B_QNC_PCIE_CCFG_UNRS (BIT15) // Upstream Non-Posted Request Size723 #define B_QNC_RCRB_SPIS_SCL (BIT15) // SPI Configuration Lockdown
36 #define PIIX4_PMBA_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
56 #define VIRTIO_NET_F_MRG_RXBUF BIT15 // guest can merge receive buffers
79 #define ICH9_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
48 #define SP810_SYS_CTRL_TIMER0_TIMCLK BIT15 // 0=REFCLK, 1=TIMCLK
82 PowerManagementCSR |= BIT15; in ResetPowerManagementFeature()
69 PowerManagementCSR |= BIT15; in ResetPowerManagementFeature()
29 #define WR0_WRITE_MODE BIT15
101 #define BIT15 0x00008000
142 #define BYPASS_MODE (BIT15 | BIT16)
61 #define BIT15 0x8000 macro