| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| D | meminit.c | 557 …l_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT20|BIT19|BIT18|BIT17|BIT16)… in ddrphy_init()
565 …RIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)… in ddrphy_init()
566 …RIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)… in ddrphy_init()
572 …RIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)… in ddrphy_init()
573 …RIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)… in ddrphy_init()
577 …_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)… in ddrphy_init()
578 …_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)… in ddrphy_init()
602 …((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)… in ddrphy_init()
603 …BIT31|BIT30|BIT29|BIT28)|(BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)… in ddrphy_init()
604 …BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)… in ddrphy_init()
[all …]
|
| D | general_definitions.h | 36 #undef BIT19
72 #define BIT19 0x00080000U macro
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| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
| D | PchRegsLpss.h | 64 #define B_PCH_LPSS_DMAC_STSCMD_INTRSTS BIT19 // Interrupt Status
149 #define B_PCH_LPSS_I2C_STSCMD_INTRSTS BIT19 // Interrupt Status
236 #define B_PCH_LPSS_PWM_STSCMD_INTRSTS BIT19 // Interrupt Status
323 #define B_PCH_LPSS_HSUART_STSCMD_INTRSTS BIT19 // Interrupt Status
415 #define B_PCH_LPSS_SPI_STSCMD_INTRSTS BIT19 // Interrupt Status
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| D | PchRegsPcie.h | 75 #define B_PCH_PCIE_SLCTL_SLSTS_PDC BIT19 // Presence Detect Changed
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| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/ |
| D | BoardFeatures.h | 62 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19)
67 #define B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX BIT19
156 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19|BIT20)
161 #define B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX BIT19
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| /device/linaro/bootloader/edk2/Omap35xxPkg/PciEmulation/ |
| D | PciEmulation.c | 59 MmioAnd32 (GPIO5_BASE + GPIO_OE, ~BIT19); in ConfigureUSBHost()
60 MmioWrite32 (GPIO5_BASE + GPIO_SETDATAOUT, BIT19); in ConfigureUSBHost()
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| /device/linaro/bootloader/edk2/MdePkg/Library/BaseLib/Ia32/ |
| D | FlushCacheLine.c | 46 test edx, BIT19 in AsmFlushCacheLine()
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| D | FlushCacheLine.asm | 46 test edx, BIT19
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| D | FlushCacheLine.nasm | 44 test edx, BIT19
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| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/ |
| D | SataRegisters.h | 126 #define EFI_AHCI_PORT_CMD_MPSP BIT19
167 #define EFI_AHCI_PORT_SERR_BDE BIT19
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| /device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/ |
| D | SP804Timer.h | 52 #define SP810_SYS_CTRL_TIMER2_TIMCLK BIT19 // 0=REFCLK, 1=TIMCLK
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| /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/ |
| D | Omap3530MMCHS.h | 67 #define CCCE_ENABLE BIT19
130 #define CIE_EN BIT19
145 #define CIE_SIGEN BIT19
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| D | Omap3530Dma.h | 66 #define DMA4_CSDP_DST_ENDIAN_BIG BIT19
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| /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/ |
| D | Virtio095Net.h | 60 #define VIRTIO_NET_F_CTRL_VLAN BIT19 // control channel VLAN filtering
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| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/ |
| D | CommonIncludes.h | 97 #define BIT19 0x00080000
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| /device/linaro/bootloader/edk2/MdePkg/Library/BaseCacheMaintenanceLib/ |
| D | X86Cache.c | 142 if ((RegEdx & BIT19) == 0) { in WriteBackInvalidateDataCacheRange()
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| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/ |
| D | AhciMode.h | 131 #define EFI_AHCI_PORT_CMD_MPSP BIT19
172 #define EFI_AHCI_PORT_SERR_BDE BIT19
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| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
| D | XhciReg.h | 91 #define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
105 #define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
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| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/ |
| D | QuarkNcSocId.h | 149 #define B_WDT_CONTROL_DBL_ECC_BIT_ERR_MASK (BIT19 | BIT18)
232 #define SMI_EN (BIT19) // SMI Global Enable (from Legacy Bridge)
321 #define SOCCLKEN_CONFIG_PHY_I_CMNRESET_L BIT19
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| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/ |
| D | XhciReg.h | 176 #define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change
190 #define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change
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| /device/linaro/bootloader/edk2/SecurityPkg/Tcg/Opal/OpalPasswordSmm/ |
| D | OpalAhciMode.h | 124 #define EFI_AHCI_PORT_CMD_MPSP BIT19
165 #define EFI_AHCI_PORT_SERR_BDE BIT19
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| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/ |
| D | PchRegs.h | 65 #define BIT19 0x00080000 macro
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| /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
| D | Lan9118DxeHw.h | 188 #define INSTS_GPT_INT BIT19 // GP Timer wrapped past 0xFF…
284 #define MACCR_MCPAS BIT19 // Pass all Multicast packets bit
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| /device/linaro/bootloader/edk2/ArmPkg/Include/Chipset/ |
| D | AArch64.h | 65 #define ARM_HCR_TSC BIT19
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| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/ |
| D | Ioh.h | 48 #define BIT19 0x00080000 macro
|