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Searched refs:BIT20 (Results 1 – 25 of 43) sorted by relevance

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/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
Dmeminit.c519 …isbM32m(DDRPHY, (CMDPMCONFIG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ~BIT20, BIT20); // SPID_INIT_CO… in ddrphy_init()
557 …channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT20|BIT19|BIT18|BIT17|… in ddrphy_init()
565 …i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|… in ddrphy_init()
566 …i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|… in ddrphy_init()
572 …i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|… in ddrphy_init()
573 …i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|… in ddrphy_init()
577 …DRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|… in ddrphy_init()
578 …DRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|… in ddrphy_init()
602 …<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|… in ddrphy_init()
603 …)), ((BIT31|BIT30|BIT29|BIT28)|(BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|… in ddrphy_init()
[all …]
Dgeneral_definitions.h37 #undef BIT20
73 #define BIT20 0x00100000U macro
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
DPchRegsLpss.h63 #define B_PCH_LPSS_DMAC_STSCMD_CAPLIST BIT20 // Capability List
148 #define B_PCH_LPSS_I2C_STSCMD_CAPLIST BIT20 // Capability List
235 #define B_PCH_LPSS_PWM_STSCMD_CAPLIST BIT20 // Capability List
322 #define B_PCH_LPSS_HSUART_STSCMD_CAPLIST BIT20 // Capability List
414 #define B_PCH_LPSS_SPI_STSCMD_CAPLIST BIT20 // Capability List
DPchRegsPcu.h586 #define B_PCH_SMI_STS_PCI_EXP BIT20 // PCI Express SMI Status
653 #define B_PCH_TCO_CNT_OS_POLICY (BIT21 | BIT20) // OS Policy
686 #define B_PCH_PMC_PM_STS_PMC_MSG_1_FULL BIT20 // PMC 1 Message Full Status
697 #define B_PCH_PMC_GEN_PMCON_SRS BIT20 // System Reset Status
757 #define B_PCH_PMC_FUNC_DIS_PCI_EX_FUNC0 BIT20 // PCI Express Function 0 Disable
789 #define B_PCH_PMC_PMIR_CF9GR BIT20 // CF9h Global Reset
805 #define B_PCH_PMC_GPI_ROUT_10 (BIT21 | BIT20)
882 #define B_PCH_PMC_D3_STS_0_PCIEF0 BIT20 // PCIe Function 0
919 #define B_PCH_PMC_D3_STDBY_STS_0_PCIEF0 BIT20 // PCIe Function 0
/device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/
DThumbDisassembler.c715 Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0; // S in DisassembleThumbInstruction()
716 Target = SignExtend32 (Target, BIT20); in DisassembleThumbInstruction()
861 if ((OpCode32 & BIT20) == BIT20) { in DisassembleThumbInstruction()
870 if ((OpCode32 & BIT20) == BIT20) { in DisassembleThumbInstruction()
886 if ((OpCode32 & BIT20) == BIT20) { in DisassembleThumbInstruction()
907 if ((OpCode32 & BIT20) == BIT20) { in DisassembleThumbInstruction()
916 if ((OpCode32 & BIT20) == BIT20) { in DisassembleThumbInstruction()
DArmDisassembler.c179 L = (OpCode & BIT20) == BIT20; in DisassembleArmInstruction()
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
DOmap3530MMCHS.h68 #define CICE_ENABLE BIT20
118 #define DTO BIT20
131 #define DTO_EN BIT20
146 #define DTO_SIGEN BIT20
DOmap3530Dma.h69 #define DMA4_CSDP_SRC_ENDIAN_LOCK_LOCK BIT20
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/
DBoardFeatures.h68 #define B_BOARD_FEATURES_MEMORY_TYPE_DDR1 BIT20
156 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19|BIT20)
162 #define B_BOARD_FEATURES_FORM_FACTOR_MINI_ITX BIT20
/device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Drivers/StyxSataPlatformDxe/
DSataRegisters.h127 #define EFI_AHCI_PORT_CMD_CPD BIT20
168 #define EFI_AHCI_PORT_SERR_DE BIT20
/device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/
DSP804Timer.h53 #define SP810_SYS_CTRL_TIMER2_EN BIT20
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
DLan9118DxeHw.h189 #define INSTS_RXD_INT BIT20 // Indicates that amount of d…
204 #define HWCFG_MBO BIT20 // Must Be One bit
285 #define MACCR_FDPX BIT20 // Full Duplex Mode bit
/device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/
DPeImage.h313 #define EFI_IMAGE_SCN_ALIGN_1BYTES BIT20 ///< 0x00100000
315 #define EFI_IMAGE_SCN_ALIGN_4BYTES (BIT20|BIT21) ///< 0x00300000
317 #define EFI_IMAGE_SCN_ALIGN_16BYTES (BIT20|BIT22) ///< 0x00500000
319 #define EFI_IMAGE_SCN_ALIGN_64BYTES (BIT20|BIT21|BIT22) ///< 0x00700000
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/
DCommonIncludes.h96 #define BIT20 0x00100000
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/
DAhciMode.h132 #define EFI_AHCI_PORT_CMD_CPD BIT20
173 #define EFI_AHCI_PORT_SERR_DE BIT20
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/
DXhciReg.h92 #define XHC_PORTSC_OCC BIT20 // Over-Current Change
106 #define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/
DXhciReg.h177 #define XHC_PORTSC_OCC BIT20 // Over-Current Change
191 #define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
/device/linaro/bootloader/edk2/SecurityPkg/Tcg/Opal/OpalPasswordSmm/
DOpalAhciMode.h125 #define EFI_AHCI_PORT_CMD_CPD BIT20
166 #define EFI_AHCI_PORT_SERR_DE BIT20
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/
DPchRegs.h66 #define BIT20 0x00100000 macro
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/
DIoh.h49 #define BIT20 0x00100000 macro
/device/linaro/bootloader/edk2/Omap35xxPkg/Library/OmapDmaLib/
DOmapDmaLib.c93 RegVal = ((RegVal & ~(BIT20 | BIT19)) | DMA4->WriteRequestNumber << 19); in EnableDmaChannel()
/device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/
DPL180Mci.h103 #define MCI_STATUS_CMD_TXDATAAVAILBL BIT20
/device/linaro/bootloader/edk2/BaseTools/Source/C/Include/Common/
DBaseTypes.h241 #define BIT20 0x00100000 macro
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibPei/
DI2CLibPei.h40 #define B_PCH_LPSS_I2C_STSCMD_CAPLIST BIT20 // Capability List
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/
DQuarkNcSocId.h320 #define SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L BIT20
344 #define B_MUXTOP_FLEX1_MASK (BIT22 | BIT21 | BIT20)

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