| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
| D | PchRegsLpss.h | 66 #define B_PCH_LPSS_DMAC_STSCMD_SERREN BIT8 // SERR# Enable
120 #define B_PCH_LPSS_DMAC_PCS_PMEEN BIT8 // PME Enable
151 #define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable
205 #define B_PCH_LPSS_I2C_PCS_PMEEN BIT8 // PME Enable
238 #define B_PCH_LPSS_PWM_STSCMD_SERREN BIT8 // SERR# Enable
292 #define B_PCH_LPSS_PWM_PCS_PMEEN BIT8 // PME Enable
325 #define B_PCH_LPSS_HSUART_STSCMD_SERREN BIT8 // SERR# Enable
379 #define B_PCH_LPSS_HSUART_PCS_PMEEN BIT8 // PME Enable
417 #define B_PCH_LPSS_SPI_STSCMD_SERREN BIT8 // SERR# Enable
471 #define B_PCH_LPSS_SPI_PCS_PMEEN BIT8 // PME Enable
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| D | PchRegsPcu.h | 77 #define B_PCH_LPC_COMMAND_SERR_EN BIT8 // SERR# Enable
94 #define B_PCH_LPC_DEV_STS_MDPED BIT8 // Data Parity Error
202 #define B_PCH_LPC_FWH_BIOS_DEC_EC0 BIT8 // C0-C8 Enable
242 #define B_PCH_LPC_CGC_SBTCG BIT8 // IOSF-SB Trunk Clock Gating (Request) Dis…
297 #define B_PCH_ILB_ULKMC_TRAPBY60R BIT8 // SMI Caused by Port 60 Read
315 #define B_PCH_ILB_BIOS_CNTL_PFE BIT8 // Prefetch Enable
363 #define B_PCH_ILB_DXXIR_ICR_MASK (BIT10 | BIT9 | BIT8) // INTC Mask
365 #define V_PCH_ILB_DXXIR_ICR_PIRQB BIT8 // INTC Mapping to IRQ B
367 #define V_PCH_ILB_DXXIR_ICR_PIRQD (BIT9 | BIT8) // INTC Mapping to IRQ D
369 #define V_PCH_ILB_DXXIR_ICR_PIRQF (BIT10 | BIT8) // INTC Mapping to IRQ F
[all …]
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| D | PchRegsSata.h | 69 #define B_PCH_SATA_COMMAND_SERR_EN BIT8 // SERR# Enable
86 #define B_PCH_SATA_PCISTS_DPED BIT8 // Master Data Parity Error Detected
161 #define B_PCH_SATA_PMCS_PMEE BIT8 // PME Enable
170 #define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) /…
177 #define B_PCH_SATA_PORT0_DISABLED BIT8
193 #define B_PCH_SATA_PCS_PORT0_DET BIT8 // Port 0 Present
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| D | PchRegsUsb.h | 71 #define B_PCH_EHCI_PWR_CNTL_STS_PME_EN BIT8 // Power Enable
94 #define B_PCH_XHCI_PWR_CNTL_STS_PME_EN BIT8
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| D | PchRegsHda.h | 51 #define B_PCH_HDA_PCS_PMEE BIT8 // PME Enable
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| /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
| D | Lan9118DxeHw.h | 153 #define TXSTATUS_ECOLL BIT8 // Tx ended because of Exce…
167 #define IRQCFG_IRQ_EN BIT8 // Enable external interrupt
179 #define INSTS_TSFF BIT8 // Tx Status FIFO full
213 #define MPTCTRL_ED_EN BIT8 // Energy-detect enable
220 #define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode
246 #define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full du…
274 #define MACCR_PADSTR BIT8 // Automatic Pad Stripping bit
323 #define E2P_EPC_MAC_ADDRESS_LOADED BIT8
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| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibDxe/ |
| D | I2CRegs.h | 42 #define B_READ_CMD BIT8 // 1 = read, 0 = write
59 #define I2C_INTR_ACTIVITY BIT8
119 #define I2C_INTR_ACTIVITY BIT8
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| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibPei/ |
| D | I2CLibPei.h | 43 #define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable
95 #define B_READ_CMD BIT8 // 1 = read, 0 = write
112 #define I2C_INTR_ACTIVITY BIT8
176 #define I2C_INTR_ACTIVITY BIT8
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| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/ |
| D | I2cRegs.h | 53 #define B_I2C_REG_TAR (BIT9+BIT8+BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0) //…
55 #define B_I2C_REG_DATA_CMD_RW (BIT8) // Data Buffer and Command Register Read/W…
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| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi6220/Include/ |
| D | Hi6220.h | 30 #define CTRL4_PICO_OGDISABLE BIT8
42 #define CTRL5_PICOPHY_VDATDETENB BIT8
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| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/ |
| D | I2CLib.h | 53 #define B_READ_CMD BIT8 // 1 = read, 0 = write
70 #define I2C_INTR_ACTIVITY BIT8
132 #define I2C_INTR_ACTIVITY BIT8
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| /device/linaro/bootloader/edk2/OptionRomPkg/Bus/Usb/FtdiUsbSerialDxe/ |
| D | FtdiUsbSerialDriver.h | 118 #define SET_PARITY_ODD BIT8 // (0x1 << 8)
120 #define SET_PARITY_MARK BIT9 | BIT8 // (0x3 << 8)
135 #define SET_DTR_HIGH (BIT8 | BIT0)
136 #define SET_DTR_LOW (BIT8)
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| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| D | general_definitions.h | 25 #undef BIT8
61 #define BIT8 0x00000100U macro
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| D | meminit.c | 557 …IT26|BIT25|BIT24)|(BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BI… in ddrphy_init()
565 …mpD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT13|BIT12|BIT11|BIT10|BIT9|BIT8))); // On Duration:… in ddrphy_init()
566 …mpD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT13|BIT12|BIT11|BIT10|BIT9|BIT8))); // On Duration:… in ddrphy_init()
577 …L-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BI… in ddrphy_init()
578 …L-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BI… in ddrphy_init()
585 …+ (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (BIT8), (BIT8)); // WR_LVL mo… in ddrphy_init()
599 …OMPODT + (channel_i * DDRIOCCC_CH_OFFSET)), ((0x03<<5)|(0x03<<0)), ((BIT9|BIT8|BIT7|BIT6|BIT5)|(BI… in ddrphy_init()
602 …|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4… in ddrphy_init()
603 …IT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12)|(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4… in ddrphy_init()
604 …|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BI… in ddrphy_init()
[all …]
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| D | meminit_utils.c | 61 msk = (byte_lane & BIT0) ? (BIT23 | BIT22 | BIT21 | BIT20) : (BIT11 | BIT10 | BIT9 | BIT8); in set_rcvn()
90 msk |= (byte_lane & BIT0) ? (BIT11) : (BIT8); in set_rcvn()
361 msk = (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8); in set_wdq()
453 msk = (BIT11 | BIT10 | BIT9 | BIT8); in set_wcmd()
473 | (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) | (BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0); in set_wcmd()
570 msk = (BIT15 | BIT14 | BIT13 | BIT12) | (BIT11 | BIT10 | BIT9 | BIT8); in set_wclk()
582 … = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16) | (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8); in set_wclk()
608 msk |= (BIT11 | BIT10 | BIT9 | BIT8); // only ??? matters in set_wclk()
839 …DRPHY, (B01PTRCTL1 + (channel_i * DDRIODQ_CH_OFFSET) + ((bl_i >> 1) * DDRIODQ_BL_OFFSET)), ~(BIT8), in clear_pointers()
840 (BIT8)); in clear_pointers()
[all …]
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| /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/ |
| D | PL180Mci.h | 78 #define MCI_CLOCK_ENABLE BIT8
91 #define MCI_STATUS_CMD_DATAEND BIT8
144 #define MCI_CPSM_LONG_INTERRUPT BIT8
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| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/ |
| D | Lan91xDxeHw.h | 79 #define TCR_NOCRC BIT8
108 #define RCR_RXEN BIT8
246 #define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode
273 #define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full du…
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| /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Isp1761UsbDxe/ |
| D | Isp1761UsbDxe.h | 50 #define ISP1761_DC_INTERRUPT_EP0SETUP BIT8
62 #define ISP1761_MODE_DATA_BUS_WIDTH BIT8
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| /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/ |
| D | Omap3530Dma.h | 89 #define DMA4_CCR_SUSPEND_SENSITIVE_IGNORE BIT8
117 #define DMA4_CSR_TRANS_ERR BIT8
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| D | Omap3530.h | 36 #define PBIASLITEVMODE1 BIT8
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| D | Omap3530MMCHS.h | 44 #define WPP BIT8
89 #define SDBP_MASK BIT8
91 #define SDBP_ON BIT8
182 #define CMD8_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0)
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| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Block/DwUfsHcDxe/ |
| D | DwUfsHcDxe.h | 96 #define UFS_HC_IS_ULSS BIT8
109 #define HCS_UPMCRS_MASK (BIT10 | BIT9 | BIT8)
110 #define HCS_PWR_LOCAL BIT8
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| /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/ |
| D | I440FxPiix4.h | 37 BIT10 | BIT9 | BIT8 | BIT7 | BIT6)
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| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/ |
| D | QuarkNcSocId.h | 291 #define B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK (BIT12 | BIT11 | BIT10 | BIT9 | BIT8)
309 #define B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK (BIT9 | BIT8)
565 #define B_QNC_LPC_BIOS_CNTL_PFE (BIT8)
647 #define B_QNC_PCIE_XCAP_SI (BIT8) //slot implemented
650 #define B_QNC_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) // L0 Acceptable exit …
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| /device/linaro/bootloader/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/ |
| D | SmmProfileArch.c | 79 SystemContext.SystemContextIa32->Eflags &= (UINTN) ~BIT8; in ClearTrapFlag()
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