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Searched refs:PERI_CTRL_BASE (Results 1 – 3 of 3) sorted by relevance

/device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyUsbDxe/
DHiKeyUsbDxe.c109 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN0, BIT4); in HiKeyUsbPhyInit()
111 Value = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_CLKSTAT0); in HiKeyUsbPhyInit()
117 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS0, Data); in HiKeyUsbPhyInit()
119 Value = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_RSTSTAT0); in HiKeyUsbPhyInit()
123 Value = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_CTRL4); in HiKeyUsbPhyInit()
127 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CTRL4, Value); in HiKeyUsbPhyInit()
139 Value = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_CTRL5); in HiKeyUsbPhyInit()
141 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CTRL5, Value); in HiKeyUsbPhyInit()
151 Data = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_CTRL5); in HiKeyUsbPhyInit()
155 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CTRL5, Data); in HiKeyUsbPhyInit()
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/device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyDxe/
DHiKeyDxe.c68 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART1); in UartInit()
69 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART1); in UartInit()
71 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART2); in UartInit()
72 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART2); in UartInit()
74 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART3); in UartInit()
75 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART3); in UartInit()
77 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART4); in UartInit()
78 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART4); in UartInit()
81 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS0, PERIPH_RST0_MMC2); in UartInit()
113 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, Bits); in HiKeyInitPeripherals()
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/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi6220/Include/
DHi6220.h26 #define PERI_CTRL_BASE 0xF7030000 macro