Searched refs:PSCI_CPU_PWR_LVL (Results 1 – 9 of 9) sorted by relevance
82 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { in psci_stats_update_pwr_down()116 local_state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]; in psci_stats_update_pwr_up()117 stat_idx = get_stat_idx(local_state, PSCI_CPU_PWR_LVL); in psci_stats_update_pwr_up()120 residency = plat_psci_stat_get_residency(PSCI_CPU_PWR_LVL, in psci_stats_update_pwr_up()132 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { in psci_stats_update_pwr_up()199 if (pwrlvl > PSCI_CPU_PWR_LVL) { in psci_get_stat()202 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl < pwrlvl; lvl++) in psci_get_stat()
72 PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL, \201 assert(pwrlvl > PSCI_CPU_PWR_LVL); in psci_set_req_local_pwr_state()229 assert(pwrlvl > PSCI_CPU_PWR_LVL); in psci_get_req_local_pwr_states()290 pd_state[PSCI_CPU_PWR_LVL] = psci_get_cpu_local_state(); in psci_get_target_local_pwr_states()294 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { in psci_get_target_local_pwr_states()316 psci_set_cpu_local_state(pd_state[PSCI_CPU_PWR_LVL]); in psci_set_target_local_pwr_states()344 for (i = PSCI_CPU_PWR_LVL + 1; i <= end_lvl; i++) { in psci_get_parent_pwr_domain_nodes()361 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { in psci_set_pwr_domains_to_run()409 for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { in psci_do_state_coordination()481 for (i = target_lvl; i >= PSCI_CPU_PWR_LVL; i--) { in psci_validate_suspend_req()[all …]
39 if (level > PSCI_CPU_PWR_LVL) { in psci_init_pwr_domain_node()125 while (level >= PSCI_CPU_PWR_LVL) { in populate_power_domain_tree()155 if (level == PSCI_CPU_PWR_LVL) in populate_power_domain_tree()
92 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL]; in psci_cpu_suspend()120 psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info); in psci_cpu_suspend()215 if (lowest_affinity_level > PSCI_CPU_PWR_LVL) in psci_affinity_info()
24 for (lvl = PSCI_CPU_PWR_LVL; lvl <= PLAT_MAX_PWR_LVL; lvl++) in psci_set_power_off_state()
281 state_info->pwr_domain_state[PSCI_CPU_PWR_LVL])); in psci_cpu_suspend_finish()
93 assert(lvl >= PSCI_CPU_PWR_LVL && lvl <= PLAT_MAX_PWR_LVL); in plat_psci_stat_get_residency()97 if (lvl == PSCI_CPU_PWR_LVL) in plat_psci_stat_get_residency()105 state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]; in plat_psci_stat_get_residency()
32 #define PSCI_CPU_PWR_LVL (0) macro
323 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in zynqmp_get_sys_suspend_power_state()