| /device/google/trout/product_files/odm/ |
| D | ueventd.rc | 3 /sys/bus/iio/devices/iio:device* buffer/enable 0660 system system
4 /sys/bus/iio/devices/iio:device* buffer/length 0660 system system
5 /sys/bus/iio/devices/iio:device* in_accel_sampling_frequency 0660 system system
6 /sys/bus/iio/devices/iio:device* in_anglvel_sampling_frequency 0660 system system
7 /sys/bus/iio/devices/iio:device* in_magn_sampling_frequency 0660 system system
8 /sys/bus/iio/devices/iio:device* scan_elements/in_timestamp_en 0660 system system
9 /sys/bus/iio/devices/iio:device* scan_elements/in_accel_x_en 0660 system system
10 /sys/bus/iio/devices/iio:device* scan_elements/in_accel_y_en 0660 system system
11 /sys/bus/iio/devices/iio:device* scan_elements/in_accel_z_en 0660 system system
12 /sys/bus/iio/devices/iio:device* scan_elements/in_magn_x_en 0660 system system
[all …]
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| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Framework/Include/ |
| D | EfiPciCfg.h | 37 #define PEI_PCI_CFG_ADDRESS(bus, dev, func, reg) ( \ argument
38 … (UINT64) ((((UINTN) bus) << 24) + (((UINTN) dev) << 16) + (((UINTN) func) << 8) + ((UINTN) reg)) \
52 #define EFI_PEI_PCI_CFG_ADDRESS(bus, dev, func, reg) \ argument
53 (UINT64) ((((UINTN) (bus)) << 24) | \
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| /device/google/contexthub/firmware/os/platform/stm32/ |
| D | pwr.c | 109 void pwrUnitClock(uint32_t bus, uint32_t unit, bool on) in pwrUnitClock() argument
111 volatile uint32_t *reg = RCC_REG(bus, ENR); in pwrUnitClock()
119 void pwrUnitReset(uint32_t bus, uint32_t unit, bool on) in pwrUnitReset() argument
121 volatile uint32_t *reg = RCC_REG(bus, RSTR); in pwrUnitReset()
129 uint32_t pwrGetBusSpeed(uint32_t bus) in pwrGetBusSpeed() argument
144 if (bus == PERIPH_BUS_AHB1 || bus == PERIPH_BUS_AHB2 || bus == PERIPH_BUS_AHB3) in pwrGetBusSpeed()
147 if (bus == PERIPH_BUS_APB1) in pwrGetBusSpeed()
150 if (bus == PERIPH_BUS_APB2) in pwrGetBusSpeed()
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| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| D | io.h | 60 #define PCIADDR(bus,dev,fn,reg) ( \ argument
62 ((bus) << 20) + \
108 uint32_t bus,
115 uint32_t bus,
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| D | platform.c | 172 uint32_t bus, in pciwrite32() argument
178 Wr32(MMIO, PCIADDR(bus,dev,fn,reg), data); in pciwrite32()
185 uint32_t bus, in pciread32() argument
190 return Rd32(MMIO, PCIADDR(bus,dev,fn,reg)); in pciread32()
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| /device/linaro/bootloader/OpenPlatformPkg/Documentation/Marvell/Drivers/ |
| D | I2cDriver.txt | 5 IO functionality to drivers of specific devices on I2C bus.
38 required by I2C stack in order to allow changing I2C bus configuration from
44 devices on I2C bus.
54 /// Traverse the set of I2C devices on an I2C bus. This routine
55 /// returns the next I2C device on an I2C bus.
59 MvI2cDevice creates EFI_I2C_DEVICE structure for every device on the bus.
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| /device/linaro/bootloader/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Cst/ |
| D | Cpu0Cst.asl | 73 { // MWAIT C1, hardware coordinated with no bus master avoidance
80 { // MWAIT C2, hardware coordinated with no bus master avoidance
87 { // MWAIT C4, hardware coordinated with bus master avoidance enabled
94 { // MWAIT C6, hardware coordinated with bus master avoidance enabled
111 { // MWAIT C1, hardware coordinated with no bus master avoidance
118 { // MWAIT C2, hardware coordinated with no bus master avoidance
125 { // MWAIT C4, hardware coordinated with bus master avoidance enabled
142 { // MWAIT C1, hardware coordinated with no bus master avoidance
149 { // MWAIT C2, hardware coordinated with no bus master avoidance
164 { // MWAIT C1, hardware coordinated with no bus master avoidance
[all …]
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| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/I2c/I2cDxe/ |
| D | I2cBusDxe.uni | 2 // This driver enumerates I2C devices on I2C bus and produce I2C IO Protocol on I2C devices.
4 // This driver enumerates I2C devices on I2C bus and produce I2C IO Protocol on I2C devices.
18 …ACT #language en-US "This driver enumerates I2C devices on I2C bus and produce I2C IO …
20 …IPTION #language en-US "This driver enumerates I2C devices on I2C bus and produce I2C IO …
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| D | I2cDxe.uni | 5 // devices on I2C bus and produce I2C IO Protocol on I2C devices.
19 …e I2C Host Protocol on I2C controller handle, enumerate I2C devices on I2C bus and produce I2C IO …
21 …e I2C Host Protocol on I2C controller handle, enumerate I2C devices on I2C bus and produce I2C IO …
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| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/ |
| D | RhProxy.asl | 40 "\\_SB.SPI1", // ResourceSource: SPI bus controller name
48 0xFF, // SlaveAddress: bus address (TBD)
52 …"\\_SB.I2C6", // ResourceSource: I2C bus controller name (For MinnowBoard Max, hardware I…
69 "\\_SB.URT2", // ResourceSource: UART bus controller name
101 "\\_SB.URT1", // ResourceSource: UART bus controller name
149 Package(2) { "bus-SPI-SPI0", Package() { 0 }},
158 Package(2) { "bus-I2C-I2C5", Package() { 1 }},
160 Package(2) { "bus-UART-UART2", Package() { 2 }},
161 Package(2) { "bus-UART-UART1", Package() { 9 }},
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| D | IoTVirtualDevice.asl | 28 "\\_SB.SPI1", // ResourceSource: SPI bus controller name
36 0x00, // SlaveAddress: bus address (TBD)
40 …"\\_SB.I2C6", // ResourceSource: I2C bus controller name (For MinnowBoard Max, hardware I…
57 "\\_SB.URT2", // ResourceSource: UART bus controller name
89 "\\_SB.URT1", // ResourceSource: UART bus controller name
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| /device/google/sunfish/sunfish/ |
| D | init.sunfish.rc | 20 chown system system /sys/bus/i2c/drivers/fts/1-0049/stm_fts_cmd
21 chown system system /sys/bus/i2c/drivers/fts/1-0049/glove_mode
25 write /sys/bus/i2c/drivers/fts/1-0049/glove_mode 00
28 write /sys/bus/i2c/drivers/fts/1-0049/glove_mode 01
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| /device/amlogic/yukawa/sepolicy/ |
| D | file_contexts | 13 /sys/devices/platform/soc/ff800000.bus/ff8000a8.rtc/wakeup(/.*)? u:object_r:sysfs_suspend_stats:s0
14 /sys/devices/platform/soc/ff800000.bus/ff8000a8.rtc/rtc/rtc0/wakeup1(/.*)? u:object_r:sysfs_suspend…
15 /sys/devices/platform/soc/ff800000.bus/ff8000a8.rtc/rtc/rtc0/hctosys u:object_r:sysfs_rtc:s0
16 /sys/devices/platform/soc/ffd00000.bus/ffd24000.serial(/.*)? u:object_r:sysfs_suspend_stats:s0
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| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/ |
| D | PcieKernelApi.h | 319 extern int pcie_port_error_report_enable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERR…
321 extern int pcie_port_error_report_disable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ER…
323 extern int pcie_device_error_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 cle…
325 extern int pcie_port_aer_cap_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 *aer_cap);
327 extern int pcie_port_aer_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,pcie_uc_aer_st…
328 extern int pcie_port_aer_status_clr(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func);
336 extern int pcie_cfg_read(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT3…
338 extern int pcie_cfg_write(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT…
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| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/ |
| D | PcieKernelApi.h | 321 extern int pcie_port_error_report_enable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERR…
323 extern int pcie_port_error_report_disable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ER…
325 extern int pcie_device_error_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 cle…
327 extern int pcie_port_aer_cap_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 *aer_cap);
329 extern int pcie_port_aer_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,pcie_uc_aer_st…
330 extern int pcie_port_aer_status_clr(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func);
338 extern int pcie_cfg_read(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT3…
340 extern int pcie_cfg_write(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT…
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| /device/google/contexthub/firmware/os/platform/stm32/inc/plat/ |
| D | pwr.h | 180 void pwrUnitClock(uint32_t bus, uint32_t unit, bool on);
181 void pwrUnitReset(uint32_t bus, uint32_t unit, bool on);
182 uint32_t pwrGetBusSpeed(uint32_t bus);
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| /device/linaro/bootloader/edk2/IntelFrameworkPkg/Include/Ppi/ |
| D | PciCfg.h | 34 #define PEI_PCI_CFG_ADDRESS(bus, dev, func, reg) ( \ argument
35 … (UINT64) ((((UINTN) bus) << 24) + (((UINTN) dev) << 16) + (((UINTN) func) << 8) + ((UINTN) reg)) \
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| /device/linaro/bootloader/arm-trusted-firmware/fdts/ |
| D | fvp-foundation-motherboard.dtsi | 9 compatible = "arm,vexpress,v2m-p1", "simple-bus";
42 compatible = "arm,amba-bus", "simple-bus";
144 compatible = "arm,vexpress,config-bus", "simple-bus";
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| D | rtsm_ve-motherboard.dtsi | 9 compatible = "arm,vexpress,v2m-p1", "simple-bus";
54 compatible = "arm,amba-bus", "simple-bus";
202 compatible = "arm,vexpress,config-bus", "simple-bus";
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| /device/linaro/bootloader/edk2/MdePkg/Include/Ppi/ |
| D | PciCfg2.h | 31 #define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \ argument
33 (((UINTN) bus) << 24) | \
|
| /device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/ |
| D | IdeBusDxe.uni | 2 // IDE bus driver.
18 #string STR_MODULE_ABSTRACT #language en-US "IDE bus driver"
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| /device/linaro/bootloader/OpenPlatformPkg/Platforms/ARM/VExpress/DeviceTree/ |
| D | fvp-foundation-motherboard-no_psci.dtsi | 33 compatible = "arm,vexpress,v2m-p1", "simple-bus";
67 compatible = "arm,amba-bus", "simple-bus";
169 compatible = "arm,vexpress,config-bus", "simple-bus";
|
| D | fvp-foundation-motherboard.dtsi | 33 compatible = "arm,vexpress,v2m-p1", "simple-bus";
67 compatible = "arm,amba-bus", "simple-bus";
169 compatible = "arm,vexpress,config-bus", "simple-bus";
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| /device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/ |
| D | IsaSerialDxe.uni | 2 // Serial driver for standard UARTS on an ISA bus.
20 …ng STR_MODULE_ABSTRACT #language en-US "Serial driver for standard UARTS on an ISA bus"
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| /device/linaro/bootloader/edk2/SourceLevelDebugPkg/ |
| D | SourceLevelDebugPkg.dec | 54 # Note that the memory BAR address is only used before Pci bus resource allocation.
59 # Note that the memory BAR address is only used before Pci bus resource allocation.
70 # For the value 0x000EF000, it means the pci address at bus 0x0, device 0x1D, function 0x7.
94 ## Note that the memory BAR address is only used before Pci bus resource allocation.
105 # For the value 0x000A0000, it means the pci address at bus 0x0, device 0x14, function 0x0.
|