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Searched refs:mmio_clrbits_32 (Results 1 – 24 of 24) sorted by relevance

/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/
Ddram.c31 mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, in deidle_port()
77 mmio_clrbits_32(PHY_REG(0, 927), (1 << 22)); in handle_dram()
78 mmio_clrbits_32(PHY_REG(1, 927), (1 << 22)); in handle_dram()
Dsuspend.c21 mmio_clrbits_32(PMU_BASE + PMU_PWRMODE_CON, 0x01); in handle_suspend()
Dstopwatch.c72 mmio_clrbits_32(SYST_CST, ENABLE); in stopwatch_reset()
/device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt8173/
Dscu.c24 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, in enable_scu()
27 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, in enable_scu()
Dbl31_plat_setup.c56 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_rst_ctl, in platform_setup_cpu()
/device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt6795/
Dscu.c24 mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp1_miscdbg, in enable_scu()
27 mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp0_axi_config, in enable_scu()
Dplat_pm.c438 mmio_clrbits_32(MTK_WDT_BASE, in plat_system_reset()
Dbl31_plat_setup.c136 mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp1_rst_ctl, in platform_setup_cpu()
/device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt8173/drivers/mtcmos/
Dmtcmos.c137 mmio_clrbits_32(reg_pwr_con, SRAM_ISOINT_B); in mtcmos_ctrl_little_off()
143 mmio_clrbits_32(reg_pwr_con, PWR_RST_B); in mtcmos_ctrl_little_off()
145 mmio_clrbits_32(reg_pwr_con, PWR_ON); in mtcmos_ctrl_little_off()
146 mmio_clrbits_32(reg_pwr_con, PWR_ON_2ND); in mtcmos_ctrl_little_off()
269 mmio_clrbits_32(SPM_PCM_RESERVE, MTCMOS_CTRL_EN); in mtcmos_non_cpu_ctrl()
/device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/
Dspm_suspend.c283 mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_ISO_EN); in bigcore_pll_on()
289 mmio_clrbits_32(ARMCA15PLL_CON0, ARMCA15PLL_EN); in bigcore_pll_off()
291 mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_PWR_ON); in bigcore_pll_off()
Dspm_hotplug.c244 mmio_clrbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK); in spm_hotplug_on()
265 mmio_clrbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK); in spm_hotplug_off()
Dspm_mcdi.c260 mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR); in spm_mcdi_cpu_wake_up_event()
440 mmio_clrbits_32(SPM_PCM_RESERVE, in spm_mcdi_clear_cputop_pwrctrl_for_cluster_on()
443 mmio_clrbits_32(SPM_PCM_RESERVE, in spm_mcdi_clear_cputop_pwrctrl_for_cluster_on()
Dspm.c288 mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR); in spm_kick_pcm_to_run()
364 mmio_clrbits_32(AP_PLL_CON3, 0xFFFFF); in spm_boot_init()
365 mmio_clrbits_32(AP_PLL_CON4, 0xF); in spm_boot_init()
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/
Dhikey960_bl1_setup.c161 mmio_clrbits_32(PMU_SSI0_CLK_TOP_CTRL7_REG, NP_XO_ABB_DIG); in hikey960_pmu_init()
529 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()
534 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); in hikey960_ufs_reset()
535 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); in hikey960_ufs_reset()
561 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); in hikey960_ufs_reset()
567 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); in hikey960_ufs_reset()
568 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); in hikey960_ufs_reset()
569 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); in hikey960_ufs_reset()
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
Dsuspend.c253 mmio_clrbits_32(PI_REG(ch, 100), 0x3 << 8); in data_training()
299 mmio_clrbits_32(PI_REG(ch, 60), 0x3 << 8); in data_training()
347 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 24); in data_training()
380 mmio_clrbits_32(PI_REG(ch, 80), 0x3 << 16); in data_training()
394 mmio_clrbits_32(PI_REG(ch, 181), 0x1 << 8); in data_training()
415 mmio_clrbits_32(PI_REG(ch, 124), 0x3 << 16); in data_training()
419 mmio_clrbits_32(PHY_REG(ch, 927), (1 << 22)); in data_training()
611 mmio_clrbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); in pctl_start()
630 mmio_clrbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); in pctl_start()
Ddfs.c641 mmio_clrbits_32(CTL_REG(i, 213), 1 << 16); in gen_rk3399_ctl_params_f0()
890 mmio_clrbits_32(CTL_REG(i, 213), (1 << 24)); in gen_rk3399_ctl_params_f1()
1005 mmio_clrbits_32(CTL_REG(i, 305), 1 << 16); in gen_rk3399_disable_training()
1006 mmio_clrbits_32(CTL_REG(i, 71), 1); in gen_rk3399_disable_training()
1007 mmio_clrbits_32(CTL_REG(i, 70), 1 << 8); in gen_rk3399_disable_training()
1480 mmio_clrbits_32(PHY_REG(ch, 78 + i * 128), 0x07 << 8); in gen_rk3399_phy_dll_bypass()
1518 mmio_clrbits_32(PHY_REG(i, 913), 1); in gen_rk3399_phy_params()
1674 mmio_clrbits_32(PHY_REG(i, 84), 0x1 << 16); in gen_rk3399_phy_params()
1675 mmio_clrbits_32(PHY_REG(i, 212), 0x1 << 16); in gen_rk3399_phy_params()
1676 mmio_clrbits_32(PHY_REG(i, 340), 0x1 << 16); in gen_rk3399_phy_params()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/include/
Drk3399_mcu.h18 #define mmio_clrbits_32(addr, clear) \ macro
/device/linaro/bootloader/arm-trusted-firmware/include/lib/
Dmmio.h52 static inline void mmio_clrbits_32(uintptr_t addr, uint32_t clear) in mmio_clrbits_32() function
/device/linaro/bootloader/arm-trusted-firmware/plat/socionext/uniphier/
Duniphier_psci.c73 mmio_clrbits_32(UNIPHIER_SLFRSTSEL, UNIPHIER_SLFRSTSEL_MASK); in uniphier_self_system_reset()
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/
Dpmu.c412 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B)); in rk3399_flush_l2_b()
441 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG)); in pmu_scu_b_pwrup()
887 mmio_clrbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle); in clr_hw_idle()
943 mmio_clrbits_32(GPIO3_BASE + 0x04, 0x00ffffff); in suspend_apio()
960 mmio_clrbits_32(GPIO2_BASE + 0x04, 0x00001fff); in suspend_apio()
977 mmio_clrbits_32(GPIO2_BASE + 0x04, 0x1fff0000); in suspend_apio()
994 mmio_clrbits_32(GPIO4_BASE + 0x04, 0x7fff0000); in suspend_apio()
1010 mmio_clrbits_32(GPIO3_BASE + 0x04, 0xff000000); in suspend_apio()
1011 mmio_clrbits_32(GPIO4_BASE + 0x04, 0x000000ff); in suspend_apio()
1442 mmio_clrbits_32(PMU_BASE + PMU_PWRDN_CON, in rockchip_soc_sys_pwr_dm_resume()
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/drivers/pwrc/
Dhisi_pwrc.c145 mmio_clrbits_32(CPUIDLE_FLAG_REG(cluster), BIT(core)); in hisi_clear_cpuidle_flag()
218 mmio_clrbits_32(REG_SCBAKDATA3_OFFSET, flag); in hisi_clear_cpu_boot_flag()
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3328/drivers/pmu/
Dpmu.c494 mmio_clrbits_32(DDR_UPCTL_BASE + DDR_PCTL2_PWRCTL, SELFREF_EN); in ddr_suspend()
541 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(2)); in dmc_restore()
543 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(0)); in dmc_restore()
/device/linaro/bootloader/arm-trusted-firmware/drivers/synopsys/ufs/
Ddw_ufs.c80 mmio_clrbits_32(base + AHIT, 0x3FF); in dwufs_phy_init()
/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/
Dsoc.c297 mmio_clrbits_32(CRU_BASE + CRU_GLB_RST_CON, in soc_global_soft_reset_init()