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/device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/mt6795/aarch64/
Dplat_helpers.S23 adr x2, ptr_atf_crash_flag
24 ldr x2, [x2]
26 cbz x2, exit_putc
32 adr x2, ptr_atf_crash_flag
33 ldr x2, [x2]
36 str w1, [x2]
38 ldr w2, [x2]
47 and x2, x1, #MPIDR_CPU_MASK
50 add x1, x2, x1, LSR #6
52 adr x2, ptr_atf_except_write_pos_per_cpu
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/
Dplat_trampoline.S32 adr x2, __tegra186_cpu_reset_handler_data
33 ldr x2, [x2, #8]
37 cmp x2, #16
41 sub x2, x2, #16
45 cbz x2, boot_cpu
48 subs x2, x2, #1
/device/linaro/bootloader/edk2/ArmVirtPkg/PrePi/AArch64/
DModuleEntryPoint.S66 ldr x2, PcdGet64 (PcdSystemMemorySize)
67 sub x2, x2, #1
68 add x1, x1, x2 // x1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize
71 ldr x2, PcdGet64 (PcdFdBaseAddress)
73 add x3, x3, x2 // x3 = FdTop = PcdFdBaseAddress + PcdFdSize
89 mov x1, x2
116 MOV32 (x2, FixedPcdGet32(PcdCPUCorePrimaryStackSize))
117 sub x22, x1, x2
127 MOV32 (x2, FixedPcdGet32(PcdCPUCorePrimaryStackSize))
140 mov x2, x22
/device/linaro/bootloader/arm-trusted-firmware/lib/psci/
Dpsci_main.c341 u_register_t x2, in psci_smc_handler() argument
359 x2 = (uint32_t)x2; in psci_smc_handler()
370 return psci_cpu_suspend(x1, x2, x3); in psci_smc_handler()
373 return psci_cpu_on(x1, x2, x3); in psci_smc_handler()
376 return psci_affinity_info(x1, x2); in psci_smc_handler()
388 return psci_node_hw_state(x1, x2); in psci_smc_handler()
391 return psci_system_suspend(x1, x2); in psci_smc_handler()
406 return psci_stat_residency(x1, x2); in psci_smc_handler()
409 return psci_stat_count(x1, x2); in psci_smc_handler()
415 return psci_mem_chk_range(x1, x2); in psci_smc_handler()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/
Dplat_sip_calls.c36 uint64_t x2, in plat_sip_handler() argument
49 x2 = (uint32_t)x2; in plat_sip_handler()
51 if (!x1 || x2 > NS_SWITCH_AARCH32) { in plat_sip_handler()
58 (x2 == NS_SWITCH_AARCH32) ? SPSR32 : SPSR64); in plat_sip_handler()
61 cm_write_scr_el3_bit(NON_SECURE, SCR_RW_BITPOS, !x2); in plat_sip_handler()
64 (x2 == NS_SWITCH_AARCH32) ? "32" : "64"); in plat_sip_handler()
/device/linaro/bootloader/arm-trusted-firmware/lib/cpus/aarch64/
Dcpu_helpers.S40 ldr x2, [x0, #CPU_RESET_FUNC]
42 cbz x2, 1f
45 br x2
67 mov_imm x2, (CPU_MAX_PWR_DWN_OPS - 1)
68 cmp x0, x2
69 csel x2, x2, x0, hi
80 add x1, x1, x2, lsl #3
126 ldr x2, [x0, #CPU_REG_DUMP]
127 cbz x2, 1f
128 blr x2
[all …]
Ddenver.S52 lsl x2, x1, #16
53 msr s3_0_c15_c0_2, x2
57 1: mrs x2, s3_0_c15_c0_2
58 lsr x2, x2, #32
60 and x2, x2, x1
61 cbnz x2, 1b
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey/aarch64/
Dhikey_helpers.S47 mov_imm x2, PL011_BAUDRATE
75 ldr x2, =0xf7020000
77 str w1, [x2, #4]
79 str w1, [x2, #8]
81 str w1, [x2, #16]
83 str w1, [x2, #32]
85 mrs x2, currentel
86 and x2, x2, #0xc0
88 cmp x2, #0x04
/device/google/contexthub/lib/nanohub/
Daes.c206 …uint32_t x0, x1, x2, x3; //we CAN use an array, but then GCC will not use registers. so we use sep… in aesEncr() local
212 x2 = *src++ ^ *k++; in aesEncr()
222 ror(FwdTab0[(x2 >> 8) & 0xff], 16) ^ in aesEncr()
227 ror(FwdTab0[(x2 >> 16) & 0xff], 8) ^ in aesEncr()
232 ror(FwdTab0[(x2 >> 24) & 0xff], 0) ^ in aesEncr()
241 ror(FwdTab0[(x2 >> 0) & 0xff], 24); in aesEncr()
245 x2 = t2; in aesEncr()
252 (((uint32_t)(FwdSbox[(x2 >> 8) & 0xff])) << 8) ^ in aesEncr()
257 (((uint32_t)(FwdSbox[(x2 >> 16) & 0xff])) << 16) ^ in aesEncr()
262 (((uint32_t)(FwdSbox[(x2 >> 24) & 0xff])) << 24) ^ in aesEncr()
[all …]
/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/common/
Dtegra_sip_calls.c39 uint64_t x2, in plat_sip_handler() argument
54 uint64_t x2, in tegra_sip_handler() argument
65 err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); in tegra_sip_handler()
74 x2 = (uint32_t)x2; in tegra_sip_handler()
80 err = bl31_check_ns_address(x1, x2); in tegra_sip_handler()
87 if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) { in tegra_sip_handler()
105 tegra_memctrl_videomem_setup(x1, x2); in tegra_sip_handler()
/device/linaro/bootloader/edk2/AppPkg/Applications/Python/Python-2.7.2/Lib/test/
Ddouble_const.py21 x2 = eval(x_str)
22 assert x2 > 0.0
23 diff = abs(x - x2)
26 if x2 + (diff / 8.) != x2:
/device/linaro/bootloader/arm-trusted-firmware/plat/mediatek/common/
Dmtk_sip_svc.c24 uint64_t x2, in mediatek_plat_sip_handler() argument
39 uint64_t x2, in mediatek_sip_handler() argument
49 clean_top_32b_of_param(smc_fid, &x1, &x2, &x3, &x4); in mediatek_sip_handler()
65 (uint32_t)x2); in mediatek_sip_handler()
71 boot_to_kernel(x1, x2, x3, x4); in mediatek_sip_handler()
77 return mediatek_plat_sip_handler(smc_fid, x1, x2, x3, x4, in mediatek_sip_handler()
87 uint64_t x2, in sip_smc_handler() argument
110 return mediatek_sip_handler(smc_fid, x1, x2, x3, x4, in sip_smc_handler()
/device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/aarch64/
Dhikey960_helpers.S53 mov_imm x2, PL011_BAUDRATE
81 ldr x2, =0xf7020000
83 str w1, [x2, #4]
85 str w1, [x2, #8]
87 str w1, [x2, #16]
89 str w1, [x2, #32]
91 mrs x2, currentel
92 and x2, x2, #0x0c
94 cmp x2, #0x04
/device/linaro/bootloader/arm-trusted-firmware/lib/pmf/
Dpmf_smc.c17 u_register_t x2, in pmf_smc_handler() argument
30 x2 = (uint32_t)x2; in pmf_smc_handler()
41 rc = pmf_get_timestamp_smc(x1, x2, x3, &ts_value); in pmf_smc_handler()
57 rc = pmf_get_timestamp_smc(x1, x2, x3, &ts_value); in pmf_smc_handler()
/device/linaro/bootloader/edk2/ArmPlatformPkg/PrePi/AArch64/
DModuleEntryPoint.S36 MOV64 (x2, FixedPcdGet64(PcdFdBaseAddress))
39 add x3, x3, x2 // x3 = FdTop = PcdFdBaseAddress + PcdFdSize
55 mov x1, x2
82 MOV32 (x2, FixedPcdGet32(PcdCPUCorePrimaryStackSize))
83 sub x12, x1, x2
93 MOV32 (x2, FixedPcdGet32(PcdCPUCorePrimaryStackSize))
106 mov x2, x12
/device/linaro/bootloader/arm-trusted-firmware/plat/arm/css/drivers/sds/aarch64/
Dsds_helpers.S53 ubfx x2, x2, #SDS_HEADER_STRUCT_SIZE_SHIFT, #SDS_HEADER_STRUCT_SIZE_WIDTH
55 add x2, x2, #SDS_HEADER_SIZE
56 add x0, x0, x2
/device/linaro/bootloader/edk2/MdeModulePkg/Universal/EbcDxe/AArch64/
DEbcLowLevel.S47 sub x3, x2, x1 // Length = NewStackPointer - FramePtr
68 ldr x2, [x9, #16] // |
88 ldr x4, [x2, #-8]! // No? Then push one word
92 2: ldp x4, x5, [x2, #-16]!
94 3: cmp x2, x1
98 ldp x2, x3, [x9, #16]
141 mov x2, x16
/device/linaro/bootloader/arm-trusted-firmware/lib/aarch64/
Dmisc_helpers.S41 mov x2, #MPIDR_AFFLVL_SHIFT
42 lsl x2, x1, x2
43 lsr x0, x0, x2
44 lsl x0, x0, x2
94 add x2, x0, x1
191 stop_address .req x2 /* Address past the last zeroed byte */
432 cmp x2, #16
436 sub x2, x2, #16
440 cbz x2, m_end
443 subs x2, x2, #1
Dcache_helpers.S25 dcache_line_size x2, x3
27 sub x3, x2, #1
31 add x0, x0, x2
97 add x2, x10, x10, lsr #1 // work out 3x current cache level
98 lsr x1, x0, x2 // extract cache type bits from clidr
106 and x2, x1, #7 // extract the length of the cache lines
107 add x2, x2, #4 // add 4 (line length offset)
/device/linaro/bootloader/arm-trusted-firmware/plat/arm/board/fvp/aarch64/
Dfvp_helpers.S69 mrs x2, ICC_SRE_EL3
70 orr x2, x2, #(ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)
71 msr ICC_SRE_EL3, x2
77 fvp_choose_gicmmap x0, x1, x2, w2, x1
130 mrs x2, mpidr_el1
205 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
211 madd x0, x2, x5, x0
/device/linaro/bootloader/arm-trusted-firmware/include/lib/el3_runtime/aarch64/
Dcontext.h283 #define set_aapcs_args2(ctx, x0, x1, x2) do { \ argument
284 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \
287 #define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ argument
289 set_aapcs_args2(ctx, x0, x1, x2); \
291 #define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ argument
293 set_aapcs_args3(ctx, x0, x1, x2, x3); \
295 #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ argument
297 set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \
299 #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ argument
301 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \
[all …]
/device/linaro/bootloader/edk2/MdePkg/Library/BaseMemoryLibOptDxe/AArch64/
DCompareGuid.S33 mov x2, xzr
36 ldp x1, x2, [x1]
38 ccmp x2, x4, #0, eq
/device/linaro/bootloader/edk2/ArmPlatformPkg/PrePeiCore/AArch64/
DPrePeiCoreEntryPoint.S65 MOV32 (x2, FixedPcdGet32(PcdCPUCoreSecondaryStackSize))
66 mul x0, x0, x2
72 MOV64 (x2, FixedPcdGet64(PcdFvBaseAddress))
73 ldr x1, [x2, #8]
/device/linaro/bootloader/arm-trusted-firmware/plat/arm/common/
Darm_sip_svc.c33 u_register_t x2, in arm_sip_handler() argument
47 return pmf_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in arm_sip_handler()
60 pc = (u_register_t) ((x1 << 32) | (uint32_t) x2); in arm_sip_handler()
68 (uint32_t) x2, (uint32_t) x3, (uint32_t) x4, in arm_sip_handler()
/device/google/cuttlefish/host/frontend/gcastv2/https/
DSupport.cpp83 uint8_t x2 = data[i + 1]; in encodeBase64() local
87 out->append(1, encode6Bit((x1 << 4 | x2 >> 4) & 0x3f)); in encodeBase64()
88 out->append(1, encode6Bit((x2 << 2 | x3 >> 6) & 0x3f)); in encodeBase64()
97 uint8_t x2 = data[i + 1]; in encodeBase64() local
99 out->append(1, encode6Bit((x1 << 4 | x2 >> 4) & 0x3f)); in encodeBase64()
100 out->append(1, encode6Bit((x2 << 2) & 0x3f)); in encodeBase64()

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