| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 195 case ISD::ADDE: { in trySelect()
199 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in trySelect()
204 if (Opcode == ISD::ADDE) { in trySelect()
|
| D | MipsSEISelDAGToDAG.cpp | 245 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in selectAddESubE()
739 case ISD::ADDE: { in trySelect()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/RISCV/ |
| D | addc-adde-sube-subc.ll | 5 ; Ensure that the ISDOpcodes ADDC, ADDE, SUBC, SUBE are handled correctly
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 123 case ISD::ADDE: in isdToLanaiAluCode()
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 123 case ISD::ADDE: in isdToLanaiAluCode()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 223 ADDE, SUBE, enumerator
|
| D | SelectionDAG.h | 1185 case ISD::ADDE:
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 232 ADDE, SUBE, enumerator
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativePPC_32.c | 129 return push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2)); in emit_single_op()
|
| D | sljitNativePPC_64.c | 267 return push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2)); in emit_single_op()
|
| D | sljitNativeARM_64.c | 71 #define ADDE 0x8b200000 macro
1921 FAIL_IF(push_inst(compiler, ADDE | (0x3 << 13) | RD(dst_reg) | RN(SLJIT_SP) | RM(dst_reg))); in sljit_get_local_base()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 274 assert(Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!"); in selectAddE()
798 case ISD::ADDE: { in trySelect()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 72 ADDE, // Add using carry enumerator
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 227 case ISD::ADDE: return "adde"; in getOperationName()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 99 ADDE, // Add using carry enumerator
|
| D | ARMISelLowering.cpp | 1273 case ARMISD::ADDE: return "ARMISD::ADDE"; in getTargetNodeName()
4064 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32), in ConvertCarryFlagToBooleanCarry()
7740 Result = DAG.getNode(ARMISD::ADDE, DL, VTs, Op.getOperand(0), in LowerADDSUBCARRY()
10088 assert((AddeSubeNode->getOpcode() == ARMISD::ADDE || in AddCombineTo64bitMLAL()
10098 if ((AddeSubeNode->getOpcode() == ARMISD::ADDE && in AddCombineTo64bitMLAL()
10117 if (AddeSubeNode->getOpcode() == ARMISD::ADDE && in AddCombineTo64bitMLAL()
10296 (AddeNode->getOpcode() == ARMISD::ADDE) && in PerformUMLALCombine()
10317 if (LHS->getOpcode() == ARMISD::ADDE && in PerformAddcSubcCombine()
10357 unsigned Opcode = (N->getOpcode() == ARMISD::ADDE) ? ARMISD::SUBE in PerformAddeSubeCombine()
10358 : ARMISD::ADDE; in PerformAddeSubeCombine()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 478 case ISD::ADDE: in Select()
700 bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE); in SelectADD_SUB_I64()
703 bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE; in SelectADD_SUB_I64()
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 91 setOperationAction(ISD::ADDE, MVT::i64, Expand); in BPFTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 268 case ISD::ADDE: return "adde"; in getOperationName()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 99 ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, in WebAssemblyTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1594 setOperationAction(ISD::ADDE, MVT::i32, Custom); in SparcTargetLowering()
1600 setOperationAction(ISD::ADDE, MVT::i64, Custom); in SparcTargetLowering()
2963 case ISD::ADDC: hiOpc = ISD::ADDE; break; in LowerADDC_ADDE_SUBC_SUBE()
2964 case ISD::ADDE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
3112 case ISD::ADDE: in LowerOperation()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | ReleaseNotes.rst | 287 * ``ADDC``/``ADDE``/``SUBC``/``SUBE`` are now deprecated and will default to expand. Backends
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1834 setOperationAction(ISD::ADDE, MVT::i8, Expand); in HexagonTargetLowering()
1835 setOperationAction(ISD::ADDE, MVT::i16, Expand); in HexagonTargetLowering()
1836 setOperationAction(ISD::ADDE, MVT::i32, Expand); in HexagonTargetLowering()
1837 setOperationAction(ISD::ADDE, MVT::i64, Expand); in HexagonTargetLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 111 ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, in WebAssemblyTargetLowering()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1614 setOperationAction(ISD::ADDE, MVT::i64, Custom); in SparcTargetLowering()
2929 case ISD::ADDC: hiOpc = ISD::ADDE; break; in LowerADDC_ADDE_SUBC_SUBE()
2930 case ISD::ADDE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
3078 case ISD::ADDE: in LowerOperation()
|