Searched refs:AIPS1_BASE (Results 1 – 3 of 3) sorted by relevance
29 #define AIPS1_BASE 0x30000000 /* AIPS1 */ macro57 #define CCM_BASE (AIPS1_BASE + 0x380000)74 #define CSU_BASE (AIPS1_BASE + 0x3E0000)77 #define MXC_IO_MUXC_BASE (AIPS1_BASE + 0x330000)80 #define SNVS_BASE (AIPS1_BASE + 0x370000)83 #define GPT1_BASE_ADDR (AIPS1_BASE + 0x2d0000)86 #define USDHC1_BASE (AIPS1_BASE + 0xb40000)87 #define USDHC2_BASE (AIPS1_BASE + 0xb50000)88 #define USDHC3_BASE (AIPS1_BASE + 0xb60000)100 #define WDOG1_BASE (AIPS1_BASE + 0x280000)[all …]
34 #define AIPS1_BASE (0x41080000UL) macro142 #define PCC1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * PCC1_AIPS1_SLOT)))147 #define CMC0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * CMC0_AIPS1_SLOT)))149 #define OCOTP_BASE_ADDR ((AIPS1_BASE + (AIPS1_SLOT_SIZE * OCOTP_CTRL_AIPS1_SLOT)))150 #define SIM0_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM0_AIPS1_SLOT)))151 #define SIM1_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM1_AIPS1_SLOT)))171 #define LPUART2_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART2_AIPS1_SLOT)))172 #define LPUART3_RBASE ((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART3_AIPS1_SLOT)))
50 (struct aipstz_regs *)(AIPS1_BASE + AIPSTZ_CONFIG_OFFSET), in imx_aips_init()