Home
last modified time | relevance | path

Searched refs:AR71XX_RESET_REG_MISC_INT_ENABLE (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/mips/mach-ath79/qca956x/
Dclk.c320 misc = readl(regs + AR71XX_RESET_REG_MISC_INT_ENABLE); in get_clocks()
322 writel(misc, regs + AR71XX_RESET_REG_MISC_INT_ENABLE); in get_clocks()
/external/u-boot/arch/mips/mach-ath79/include/mach/
Dar71xx_regs.h600 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 macro