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Searched refs:ARG2 (Results 1 – 25 of 49) sorted by relevance

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/external/mesa3d/src/mesa/x86/
Dassyntax.h286 #define ALIGNTEXT32ifNOP CHOICE(.align 32, .balign ARG2(32,0x90), /*can't do it*/)
287 #define ALIGNTEXT16ifNOP CHOICE(.align 16, .balign ARG2(16,0x90), /*can't do it*/)
288 #define ALIGNTEXT8ifNOP CHOICE(.align 8, .balign ARG2(8,0x90), /*can't do it*/)
289 #define ALIGNTEXT4ifNOP CHOICE(.align 4, .balign ARG2(4,0x90), /*can't do it*/)
290 #define ALIGNDATA32 CHOICE(.align 32, .balign ARG2(32,0x0), .align 32)
291 #define ALIGNDATA16 CHOICE(.align 16, .balign ARG2(16,0x0), .align 16)
292 #define ALIGNDATA8 CHOICE(.align 8, .balign ARG2(8,0x0), .align 8)
293 #define ALIGNDATA4 CHOICE(.align 4, .balign ARG2(4,0x0), .align 4)
294 #define ALIGNDATA2 CHOICE(.align 2, .balign ARG2(2,0x0), .align 2)
297 #define ALIGNTEXT32 CHOICE(.align 32, .align ARG2(5,0x90), .align 32)
[all …]
/external/llvm/test/CodeGen/AArch64/GlobalISel/
Darm64-irtranslator.ll11 ; CHECK-NEXT: [[ARG2:%[0-9]+]](64) = COPY %x1
12 ; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_ADD i64 [[ARG1]], [[ARG2]]
45 ; CHECK-NEXT: [[ARG2:%[0-9]+]](64) = COPY %x1
46 ; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_OR i64 [[ARG1]], [[ARG2]]
56 ; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1
57 ; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_OR i32 [[ARG1]], [[ARG2]]
/external/pcre/dist2/src/sljit/
DsljitNativeSPARC_32.c36 #define ARG2(flags, src2) ((flags & SRC2_IMM) ? IMM(src2) : S2(src2)) macro
96 …return push_inst(compiler, ADD | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(d… in emit_single_op()
99 …return push_inst(compiler, ADDC | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(… in emit_single_op()
102 …return push_inst(compiler, SUB | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(d… in emit_single_op()
105 …return push_inst(compiler, SUBC | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(… in emit_single_op()
108 FAIL_IF(push_inst(compiler, SMUL | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst))); in emit_single_op()
116 …return push_inst(compiler, AND | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(d… in emit_single_op()
119 …return push_inst(compiler, OR | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(ds… in emit_single_op()
122 …return push_inst(compiler, XOR | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(d… in emit_single_op()
125 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst))); in emit_single_op()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/cconv/
Darguments-varargs.ll108 ; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]])
110 ; NEW-LE-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA2]])
111 ; NEW-BE-DAG: lw [[ARG2:\$[0-9]+]], 4([[VA2]])
114 ; ALL-DAG: sh [[ARG2]], 4([[GV]])
226 ; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]])
228 ; NEW-LE-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA2]])
229 ; NEW-BE-DAG: lw [[ARG2:\$[0-9]+]], 4([[VA2]])
232 ; ALL-DAG: sw [[ARG2]], 8([[GV]])
349 ; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]])
350 ; O32-DAG: sw [[ARG2]], 16([[GV]])
[all …]
/external/llvm/test/CodeGen/Mips/cconv/
Darguments-varargs.ll108 ; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]])
110 ; NEW-LE-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA2]])
111 ; NEW-BE-DAG: lw [[ARG2:\$[0-9]+]], 4([[VA2]])
114 ; ALL-DAG: sh [[ARG2]], 4([[GV]])
226 ; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]])
228 ; NEW-LE-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA2]])
229 ; NEW-BE-DAG: lw [[ARG2:\$[0-9]+]], 4([[VA2]])
232 ; ALL-DAG: sw [[ARG2]], 8([[GV]])
350 ; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]])
351 ; O32-DAG: sw [[ARG2]], 16([[GV]])
[all …]
/external/selinux/secilc/docs/
Dcil_call_macro_statements.md98 … calling namespace (`my_domain`) and replace `ARG1` with `appdomain` and `ARG2` with `binderservic…
104 (macro binder_call ((type ARG1) (type ARG2))
105 (allow ARG1 ARG2 (binder (call transfer)))
106 (allow ARG2 ARG1 (binder (transfer)))
107 (allow ARG1 ARG2 (fd (use)))
128 (macro build_nodecon ((ipaddr ARG1) (ipaddr ARG2))
129 (nodecon ARG1 ARG2 netlabel_1)
Dcil_network_labeling_statements.md51 (macro build_nodecon ((ipaddr ARG1) (ipaddr ARG2))
52 (nodecon ARG1 ARG2 netlabel_1))
/external/tensorflow/tensorflow/compiler/mlir/xla/tests/
Dlhlo-legalize-to-gpu.mlir17 // CHECK: func @reduce(%[[ARG0:.*]]: memref<100x10xf32>, %[[ARG1:.*]]: memref<f32>, %[[ARG2:.*]]: m…
22 // CHECK: store %[[ACC]], %[[ARG2]][%[[IDX:.*]]] : memref<100xf32>
27 // CHECK: %[[LHS:.*]] = linalg.slice %[[ARG2]][%[[IDX]]] : memref<100xf32>, index, memref<f32, #map…
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
Darm64-irtranslator.ll11 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
12 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_ADD [[ARG1]], [[ARG2]]
22 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
23 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_MUL [[ARG1]], [[ARG2]]
293 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
294 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_OR [[ARG1]], [[ARG2]]
304 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
305 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_OR [[ARG1]], [[ARG2]]
316 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
317 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_XOR [[ARG1]], [[ARG2]]
[all …]
/external/angle/tools/flex-bison/third_party/skeletons/
Dbison.m4152 # b4_error(KIND, START, END, FORMAT, [ARG1], [ARG2], ...)
154 # Write @KIND(START@,END@,FORMAT@,ARG1@,ARG2@,...@) to stdout.
167 # b4_warn(FORMAT, [ARG1], [ARG2], ...)
169 # Write @warn(FORMAT@,ARG1@,ARG2@,...@) to stdout.
197 # b4_warn_at(START, END, FORMAT, [ARG1], [ARG2], ...)
199 # Write @warn(START@,END@,FORMAT@,ARG1@,ARG2@,...@) to stdout.
207 # b4_complain(FORMAT, [ARG1], [ARG2], ...)
215 # b4_complain_at(START, END, FORMAT, [ARG1], [ARG2], ...)
217 # Write @complain(START@,END@,FORMAT@,ARG1@,ARG2@,...@) to stdout.
223 # b4_fatal(FORMAT, [ARG1], [ARG2], ...)
[all …]
/external/llvm/test/CodeGen/X86/
Dcombine-multiplies.ll34 ; CHECK-NEXT: leal ([[ARG2:%[a-z]+]],[[MUL]]), [[LEA:%[a-z]+]]
36 ; CHECK-NEXT: movl $22, {{[0-9]+}}([[ARG2]],[[MUL]])
37 ; CHECK-NEXT: movl $33, {{[0-9]+}}([[ARG2]],[[MUL]])
/external/llvm/test/CodeGen/AArch64/
Darm64-fast-isel.ll107 ; CHECK: mul x{{[0-9]+}}, [[ARG1:x[0-9]+]], [[ARG2:x[0-9]+]]
108 ; CHECK-NEXT: umulh x{{[0-9]+}}, [[ARG1]], [[ARG2]]
/external/tensorflow/tensorflow/compiler/mlir/tensorflow/tests/
Dannotate-parameter-replication.mlir23 // CHECK-SAME: %[[ARG2:.*]]: tensor<?xi32>)
59 …// CHECK-SAME: %[[ARG2:.*]]: tensor<!tf.resource<tensor<?xi32>>> {tf_device.is_same_data_across_re…
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-fast-isel.ll109 ; CHECK: mul x{{[0-9]+}}, [[ARG1:x[0-9]+]], [[ARG2:x[0-9]+]]
110 ; CHECK-NEXT: umulh x{{[0-9]+}}, [[ARG1]], [[ARG2]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/GlobalISel/
Darm-irtranslator.ll455 ; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY $r1
461 ; CHECK-DAG: [[V2:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)
475 ; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY $r1
481 ; CHECK-DAG: [[V2:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)
494 ; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY $r1
504 ; CHECK-DAG: [[V2:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)
/external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/MIR/Mips/
Dlive-debug-values-reg-copy.mir8 # CHECK: ![[ARG2:.*]] = !DILocalVariable(name: "arg2"
9 # CHECK: DBG_VALUE debug-use $s0_64, debug-use $noreg, ![[ARG2]], !DIExpression(), debug-location
11 # CHECK-NEXT: DBG_VALUE debug-use $s1_64, debug-use $noreg, ![[ARG2]], !DIExpression(), debug-locat…
/external/tensorflow/tensorflow/compiler/mlir/lite/tests/
Dprepare-tf.mlir78 // CHECK: %[[SUB:.*]] = "tf.Sub"(%[[ARG2:.*]], %[[MUL3]])
83 // CHECK: %[[BATCHNORM1_a:[^,]+]], {{.*}} = "tf.FusedBatchNorm"(%[[ADD2]], %[[ARG1]], %[[ARG2]], %…
84 // CHECK: "tf.FusedBatchNorm"(%[[BATCHNORM1_a]], %[[ARG1]], %[[ARG2]], %[[ARG3]], %[[ARG4]])
111 // CHECK: %[[SUB:.*]] = "tf.Sub"(%[[ARG2:.*]], %[[MUL3]])
116 // CHECK: %[[BATCHNORM1_a:[^,]+]], {{.*}} = "tf.FusedBatchNormV3"(%[[ADD2]], %[[ARG1]], %[[ARG2]],…
117 // CHECK: "tf.FusedBatchNormV3"(%[[BATCHNORM1_a]], %[[ARG1]], %[[ARG2]], %[[ARG3]], %[[ARG4]])
/external/angle/tools/flex-bison/third_party/m4sugar/
Dforeach.m4247 # EXPRESSION([ARG1], [ARG2]). If there are an odd number of ARGs, the
272 # m4_join(SEP, ARG1, ARG2...)
287 # m4_joinall(SEP, ARG1, ARG2...)
/external/wayland/m4/
Dltsugar.m417 # lt_join(SEP, ARG1, [ARG2...])
/external/curl/m4/
Dltsugar.m417 # lt_join(SEP, ARG1, [ARG2...])
/external/libexif/auto-m4/
Dltsugar.m416 # lt_join(SEP, ARG1, [ARG2...])
/external/ImageMagick/m4/
Dltsugar.m417 # lt_join(SEP, ARG1, [ARG2...])
/external/expat/m4/
Dltsugar.m417 # lt_join(SEP, ARG1, [ARG2...])
/external/lmfit/m4/
Dltsugar.m416 # lt_join(SEP, ARG1, [ARG2...])
/external/google-breakpad/m4/
Dltsugar.m416 # lt_join(SEP, ARG1, [ARG2...])

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