| /external/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 49 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
93 "mov $dst, $src", 0xB0, AddRegFrm,
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 49 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
93 "mov $dst, $src", 0xB0, AddRegFrm,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 253 AddRegFrm = 2, enumerator
702 case X86II::AddRegFrm: in getMemoryOperandNo()
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| D | X86MCCodeEmitter.cpp | 1059 case X86II::AddRegFrm: in DetermineREXPrefix()
1359 case X86II::AddRegFrm: in encodeInstruction()
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 235 AddRegFrm = 2, enumerator
668 case X86II::AddRegFrm: in getMemoryOperandNo()
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| D | X86MCCodeEmitter.cpp | 987 case X86II::AddRegFrm: in DetermineREXPrefix()
1271 case X86II::AddRegFrm: in encodeInstruction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | X86RecognizableInstr.h | 98 AddRegFrm = 2, enumerator
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| D | X86RecognizableInstr.cpp | 491 case X86Local::AddRegFrm: in emitInstructionSpecifier()
720 case X86Local::AddRegFrm: in emitDecodePath()
772 if (Form == X86Local::AddRegFrm) { in emitDecodePath()
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| /external/llvm/utils/TableGen/ |
| D | X86RecognizableInstr.cpp | 96 AddRegFrm = 2, enumerator
596 case X86Local::AddRegFrm: in emitInstructionSpecifier()
884 if (Form == X86Local::AddRegFrm) { in emitDecodePath()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.td | 1094 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
1096 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
1109 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1111 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1184 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1192 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1237 def BSWAP32r : I<0xC8, AddRegFrm,
1242 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1370 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1373 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
[all …]
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| D | X86InstrArithmetic.td | 475 def INC16r_alt : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
478 def INC32r_alt : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
521 def DEC16r_alt : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
524 def DEC32r_alt : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
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| D | X86RegisterInfo.td | 398 // GR32_NOAX - GR32 registers except EAX. Used by AddRegFrm of XCHG32 in 64-bit
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| D | X86InstrFormats.td | 22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.td | 1201 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
1203 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>,
1221 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
1223 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>,
1297 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>,
1309 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", []>,
1359 def BSWAP16r_BAD : I<0xC8, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1362 def BSWAP32r : I<0xC8, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1367 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1495 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
[all …]
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| D | X86InstrArithmetic.td | 445 def INC16r_alt : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
448 def INC32r_alt : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
491 def DEC16r_alt : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
494 def DEC32r_alt : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
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| D | X86InstrFormats.td | 23 def AddRegFrm : Format<2>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1843 case X86II::AddRegFrm: // for instructions that have one register operand
1878 for the ``X86II::AddRegFrm`` case, the first data emitted (by ``emitByte``) is
1889 case X86II::AddRegFrm:
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1803 case X86II::AddRegFrm: // for instructions that have one register operand
1838 for the ``X86II::AddRegFrm`` case, the first data emitted (by ``emitByte``) is
1849 case X86II::AddRegFrm:
|