| /external/boringssl/src/ssl/test/runner/poly1305/ |
| D | sum_arm.s | 117 BIC $0xfc000000, R0, R0
118 BIC $0xfc000000, g, g
120 BIC $0xfc000000, R11, R11
121 BIC $0xfc000000, R12, R12
173 BIC $0xfc000000, g, g
174 BIC $0xfc000000, R4, R4
183 BIC $0xfc000000, R0, R0
184 BIC $0xfc000000, R6, R6
192 BIC $0xfc000000, g, R5
193 BIC $0xfc000000, R2, R7
[all …]
|
| /external/arm-neon-tests/ |
| D | InitCache.s | 20 ;BIC r0, r0, #(0x1 <<12) ; Clear bit 0
22 ;BIC r0, r0, #(0x1 << 2) ; Clear bit 0
32 ;BIC r0, r0, #(0x1 << 1) ; L2EN bit, disable L2 cache
44 ;BIC r0, r0, #(0x1 << 11) ; Disable all forms of branch prediction
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | negative-immediates.s | 22 BIC r0, r1, #0xFFFFFF00
25 # CHECK-DISABLED: BIC
113 BIC r0, r1, #0xFFFFFF00
116 # CHECK-DISABLED: BIC
117 BIC.W r0, r1, #0xFFFFFF00
120 # CHECK-DISABLED: BIC.W
129 BIC r0, r1, #0xFEFFFEFF
132 # CHECK-DISABLED: BIC
|
| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_conv_ergtoamplitude.s | 50 BIC R11, R11, #1
77 BIC R11, R11, #1
105 BIC R11, R11, #1
|
| D | ixheaacd_conv_ergtoamplitudelp.s | 51 BIC R6, R6, #1
77 BIC R6, R6, #1
105 BIC R6, R6, #1
|
| D | ixheaacd_rescale_subbandsamples.s | 134 BIC R7, R3, #1
183 BIC R7, R3, #1
|
| D | ixheaacd_tns_ar_filter_fixed_32x16.s | 50 BIC r4, r4, #3
|
| /external/llvm/test/CodeGen/ARM/ |
| D | arm-abi-attr.ll | 13 ; The stack is 8 byte aligned on AAPCS and 4 on APCS, so we should get a BIC
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | arm-abi-attr.ll | 13 ; The stack is 8 byte aligned on AAPCS and 4 on APCS, so we should get a BIC
|
| /external/vixl/test/aarch32/config/ |
| D | cond-rd-rn-operand-rm-t32.json | 69 "Bic", // BIC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
70 // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
232 "Bic", // BIC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
|
| D | cond-rd-rn-operand-const-a32.json | 38 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
|
| D | cond-rd-rn-operand-rm-shift-rs-a32.json | 35 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
|
| D | cond-rd-rn-operand-const-t32.json | 44 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
|
| D | cond-rd-rn-operand-rm-shift-amount-1to32-a32.json | 37 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
|
| D | cond-rd-rn-operand-rm-shift-amount-1to31-a32.json | 37 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
|
| D | cond-rd-rn-operand-rm-shift-amount-1to32-t32.json | 41 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
|
| D | cond-rd-rn-operand-rm-shift-amount-1to31-t32.json | 41 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
|
| D | cond-rd-rn-operand-rm-a32.json | 46 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
|
| /external/tremolo/Tremolo/ |
| D | bitwiseARM.s | 199 BIC r3,r3,#3 @ r3 = Pointer to start (word)
224 BIC r2,r3,#3 @ r2 = b->headptr (word)
327 BIC r2,r6,#3 @ r2 = word ptr
364 BIC r2,r6,#3 @ r2 = word ptr
|
| D | dpen.s | 144 BIC r10,r10,#0x80 @ r3 = next &= ~0x80
163 BIC r7, r7, #0x8000 @ r7 = chase
204 BIC r10,r10,#0x8000 @ r3 = next &= ~0x8000
221 BIC r7, r7, #0x80000000 @ r7 = chase
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | optimize-imm.ll | 52 ; a BIC.
|
| /external/OpenCSD/decoder/tests/snapshots/TC2/ds5-dumps/ |
| D | etmv3_0x12.txt | 80 Instruction 75 S:0xC0021288 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
82 Instruction 77 S:0xC002128E 0xF023031F 0 BIC r3,r3,#0x1f false
91 Instruction 86 S:0xC0021494 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
92 Instruction 87 S:0xC0021498 0xF023031F 1 BIC r3,r3,#0x1f false
94 Instruction 89 S:0xC002149E 0xF0234378 2 BIC r3,r3,#0xf8000000 false
95 Instruction 90 S:0xC00214A2 0xF02303FF 1 BIC r3,r3,#0xff false
119 Instruction 112 S:0xC0021288 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
121 Instruction 114 S:0xC002128E 0xF023031F 0 BIC r3,r3,#0x1f false
130 Instruction 123 S:0xC0021494 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
131 Instruction 124 S:0xC0021498 0xF023031F 1 BIC r3,r3,#0x1f false
[all …]
|
| D | etmv3_0x10.txt | 120 Instruction 109 S:0xC0020A1C 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
121 Instruction 110 S:0xC0020A20 0xF023031F 1 BIC r3,r3,#0x1f false
132 Instruction 119 S:0xC002110E 0xF42354FF 1 BIC r4,r3,#0x1fe0 false
134 Instruction 121 S:0xC0021114 0xF024041F 1 BIC r4,r4,#0x1f false
146 Instruction 133 S:0xC0021134 0xF0234378 0 BIC r3,r3,#0xf8000000 false
147 Instruction 134 S:0xC0021138 0xF02303FF 1 BIC r3,r3,#0xff false
164 Instruction 149 S:0xC0020A1C 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
165 Instruction 150 S:0xC0020A20 0xF023031F 1 BIC r3,r3,#0x1f false
175 Instruction 158 S:0xC0020A1C 0xF42253FF 1 BIC r3,r2,#0x1fe0 false
176 Instruction 159 S:0xC0020A20 0xF023031F 1 BIC r3,r3,#0x1f false
[all …]
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 139 // ADD(S)rr,SUB(S)rr,AND(S)rr,BIC(S)rr,EONrr,EORrr,ORNrr,ORRrr
153 // ADD(S)rs,SUB(S)rs,AND(S)rs,BIC(S)rs,EONrs,EORrs,ORNrs,ORRrs
370 // BIC,ORR V,#imm are WriteV
410 // AND,BIC,CMTST,EOR,ORN,ORR
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 141 // ADD(S)rr,SUB(S)rr,AND(S)rr,BIC(S)rr,EONrr,EORrr,ORNrr,ORRrr
155 // ADD(S)rs,SUB(S)rs,AND(S)rs,BIC(S)rs,EONrs,EORrs,ORNrs,ORRrs
372 // BIC,ORR V,#imm are WriteV
412 // AND,BIC,CMTST,EOR,ORN,ORR
|