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Searched refs:BRW_OPCODE_SHL (Results 1 – 17 of 17) sorted by relevance

/external/mesa3d/src/intel/compiler/
Dbrw_eu.cpp611 { BRW_OPCODE_SHL, 9, "shl", 2, 1, GEN_LT(GEN12) },
612 { BRW_OPCODE_SHL, 105, "shl", 2, 1, GEN_GE(GEN12) },
Dbrw_shader.cpp980 case BRW_OPCODE_SHL: in can_do_saturate()
1032 case BRW_OPCODE_SHL: in can_do_cmod()
Dbrw_vec4_cse.cpp59 case BRW_OPCODE_SHL: in is_expression()
Dbrw_fs_cse.cpp58 case BRW_OPCODE_SHL: in is_expression()
Dbrw_vec4_copy_propagation.cpp196 case BRW_OPCODE_SHL: in try_constant_propagate()
Dbrw_eu_defines.h211 BRW_OPCODE_SHL, enumerator
Dbrw_fs_copy_propagation.cpp758 case BRW_OPCODE_SHL: in try_constant_propagate()
Dbrw_ir_performance.cpp302 case BRW_OPCODE_SHL: in instruction_desc()
Dbrw_vec4_generator.cpp1590 case BRW_OPCODE_SHL: in generate_code()
Dbrw_fs_generator.cpp2083 case BRW_OPCODE_SHL: in generate_code()
Dbrw_fs.cpp6520 case BRW_OPCODE_SHL: in get_lowered_simd_width()
/external/igt-gpu-tools/assembler/
Dlex.l128 "shl" { yylval.integer = BRW_OPCODE_SHL; return SHL; }
Dbrw_defines.h644 BRW_OPCODE_SHL = 9, enumerator
Dbrw_disasm.c65 [BRW_OPCODE_SHL] = { .name = "shl", .nsrc = 2, .ndst = 1 },
Dgram.y3062 (instr->header.opcode == BRW_OPCODE_SHL)) { in reset_instruction_src_region()
/external/mesa3d/src/intel/tools/
Di965_lex.l125 shl { yylval.integer = BRW_OPCODE_SHL; return SHL; }
Di965_gram.y231 case BRW_OPCODE_SHL: in i965_asm_binary_instruction()