Searched refs:BranchOp (Results 1 – 10 of 10) sorted by relevance
| /external/tensorflow/tensorflow/compiler/mlir/xla/transforms/ |
| D | legalize_control_flow.cc | 56 builder->create<mlir::BranchOp>(loc, target_block, return_op.getOperands()); in ReplaceTerminators()
144 builder.create<mlir::BranchOp>(loc, cond_block, while_op.getOperand()); in LowerWhileOp()
198 builder.create<mlir::BranchOp>(loc, cond_block, return_op.getOperands()); in LowerWhileOp()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.h | 84 unsigned BranchOp) const;
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| D | MipsSEISelLowering.cpp | 2977 MachineInstr &MI, MachineBasicBlock *BB, unsigned BranchOp) const { in emitMSACBranchPseudo()
3018 BuildMI(BB, DL, TII->get(BranchOp)) in emitMSACBranchPseudo()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.h | 94 unsigned BranchOp) const;
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| D | MipsSEISelLowering.cpp | 3068 MachineInstr &MI, MachineBasicBlock *BB, unsigned BranchOp) const { in emitMSACBranchPseudo()
3109 BuildMI(BB, DL, TII->get(BranchOp)) in emitMSACBranchPseudo()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.cpp | 410 bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp, in isBranchOffsetInRange() argument
415 switch (BranchOp) { in isBranchOffsetInRange()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.cpp | 532 bool AVRInstrInfo::isBranchOffsetInRange(unsigned BranchOp, in isBranchOffsetInRange() argument
535 switch (BranchOp) { in isBranchOffsetInRange()
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| /external/tensorflow/tensorflow/compiler/mlir/tensorflow/transforms/ |
| D | functional_control_flow_to_cfg.cc | 124 builder->create<BranchOp>(loc, block, operands); in JumpToBlock()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 168 bool AArch64InstrInfo::isBranchOffsetInRange(unsigned BranchOp, in isBranchOffsetInRange() argument
170 unsigned Bits = getBranchDisplacementBits(BranchOp); in isBranchOffsetInRange()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1439 bool SIInstrInfo::isBranchOffsetInRange(unsigned BranchOp, in isBranchOffsetInRange() argument
1443 assert(BranchOp != AMDGPU::S_SETPC_B64); in isBranchOffsetInRange()
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