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Searched refs:CACHE_LINE_SIZE (Results 1 – 10 of 10) sorted by relevance

/external/u-boot/arch/powerpc/cpu/mpc86xx/
Dcache.S10 #ifndef CACHE_LINE_SIZE
11 # define CACHE_LINE_SIZE L1_CACHE_BYTES macro
14 #if CACHE_LINE_SIZE == 128
16 #elif CACHE_LINE_SIZE == 32
18 #elif CACHE_LINE_SIZE == 16
20 #elif CACHE_LINE_SIZE == 8
57 lis r5,CACHE_LINE_SIZE
62 lis r5,CACHE_LINE_SIZE
75 li r5,CACHE_LINE_SIZE-1
84 addi r3,r3,CACHE_LINE_SIZE
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/external/ImageMagick/MagickCore/
Dmemory-private.h28 # define CACHE_LINE_SIZE (16 * MAGICKCORE_SIZEOF_VOID_P) macro
30 # define CACHE_LINE_SIZE (8 * MAGICKCORE_SIZEOF_VOID_P)
33 #define CACHE_ALIGNED(n) MAGICKCORE_ALIGN_UP(n,CACHE_LINE_SIZE)
38 __builtin_assume_aligned((address),CACHE_LINE_SIZE)
Dsemaphore.c149 alignment=CACHE_LINE_SIZE; in AcquireSemaphoreMemory()
150 extent=AlignedExtent(size,CACHE_LINE_SIZE); in AcquireSemaphoreMemory()
Dmemory.c262 return(aligned_alloc(CACHE_LINE_SIZE,extent)); in AcquireAlignedMemory_STDC()
271 if (posix_memalign(&memory,CACHE_LINE_SIZE,size)) in AcquireAlignedMemory_POSIX()
279 return(_aligned_malloc(size,CACHE_LINE_SIZE)); in AcquireAlignedMemory_WinAPI()
283 (MAGICKCORE_MAX_ALIGNMENT_PADDING(CACHE_LINE_SIZE) + MAGICKCORE_SIZEOF_VOID_P)
345 return(memory_methods.acquire_aligned_memory_handler(size,CACHE_LINE_SIZE)); in AcquireAlignedMemory()
Dcache.c4998 if (nexus_info->length < CACHE_LINE_SIZE) in PrefetchPixelCacheNexusPixels()
5002 MagickCachePrefetch((unsigned char *) nexus_info->pixels+CACHE_LINE_SIZE, in PrefetchPixelCacheNexusPixels()
5006 MagickCachePrefetch((unsigned char *) nexus_info->pixels+CACHE_LINE_SIZE,1,1); in PrefetchPixelCacheNexusPixels()
/external/u-boot/arch/nds32/lib/
Dcache.c31 static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache) in CACHE_LINE_SIZE() function
46 line_size = CACHE_LINE_SIZE(ICACHE); in invalidate_icache_all()
66 line_size = CACHE_LINE_SIZE(ICACHE); in invalidate_icache_range()
141 line_size = CACHE_LINE_SIZE(DCACHE); in dcache_wbinval_all()
164 line_size = CACHE_LINE_SIZE(DCACHE); in flush_dcache_range()
179 line_size = CACHE_LINE_SIZE(DCACHE); in invalidate_dcache_range()
/external/autotest/client/tests/tsc/src/
Dchecktsc.c127 #define CACHE_LINE_SIZE 256 macro
130 char pad[CACHE_LINE_SIZE];
/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_sdram.c574 flush_l1_v7(line + CACHE_LINE_SIZE); in ddr3_flush_l1_line()
578 flush_l1_v6(line + CACHE_LINE_SIZE); in ddr3_flush_l1_line()
Dddr3_hw_training.h89 #define CACHE_LINE_SIZE 0x20 macro
/external/mesa3d/src/gallium/drivers/panfrost/
Dpan_context.h29 #define CACHE_LINE_SIZE 1024 /* TODO */ macro