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Searched refs:CB_SIZE (Results 1 – 10 of 10) sorted by relevance

/external/mesa3d/src/gallium/drivers/nouveau/nvc0/
Dnvc0_compute.c117 BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3); in nvc0_screen_compute_setup()
209 BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3); in nvc0_compute_validate_constbufs()
223 BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3); in nvc0_compute_validate_constbufs()
254 BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3); in nvc0_compute_validate_driverconst()
272 BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3); in nvc0_compute_validate_buffers()
394 BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3); in nvc0_compute_upload_input()
408 BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3); in nvc0_compute_upload_input()
Dnvc0_state_validate.c131 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); in gm200_validate_sample_locations()
169 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); in nvc0_validate_sample_locations()
477 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); in nvc0_upload_uclip_planes()
641 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); in nvc0_validate_buffers()
852 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); in nvc0_validate_fbread()
Dnvc0_tex.c774 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); in nve4_set_tex_handles()
1209 BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3); in nvc0_validate_suf()
1211 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); in nvc0_validate_suf()
1272 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); in gm107_validate_surfaces()
1295 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); in nve4_update_surface_bindings()
1353 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); in nve4_create_image_handle()
Dnvc0_vbo.c824 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); in nvc0_draw_indirect()
1010 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); in nvc0_draw_vbo()
Dnvc0_screen.c984 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); in nvc0_screen_bind_cb_3d()
1295 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); in nvc0_screen_create()
Dnvc0_vbo_translate.c535 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); in nvc0_push_vbo_indirect()
Dnvc0_transfer.c592 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); in nvc0_cb_bo_push()
Dnvc0_query_hw_sm.c2518 BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3); in nvc0_hw_sm_upload_input()
/external/arm-trusted-firmware/plat/nvidia/tegra/common/drivers/smmu/
Dsmmu.c92 assert(!((pgshift != PGSHIFT) || (cb_size != CB_SIZE))); in tegra_smmu_save_context()
/external/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/
Dsmmu.h602 #define CB_SIZE 0x800000U macro
663 .reg = base_addr + (CB_SIZE >> 1) + (n * (1 << PGSHIFT)) \