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Searched refs:CLKID_FCLK_DIV2 (Results 1 – 10 of 10) sorted by relevance

/external/u-boot/include/dt-bindings/clock/
Daxg-clkc.h13 #define CLKID_FCLK_DIV2 2 macro
Dgxbb-clkc.h12 #define CLKID_FCLK_DIV2 4 macro
Dg12a-clkc.h13 #define CLKID_FCLK_DIV2 2 macro
/external/u-boot/arch/arm/dts/
Dmeson-gxbb.dtsi287 <&clkc CLKID_FCLK_DIV2>,
716 <&clkc CLKID_FCLK_DIV2>;
724 <&clkc CLKID_FCLK_DIV2>;
732 <&clkc CLKID_FCLK_DIV2>;
Dmeson-gxl.dtsi87 <&clkc CLKID_FCLK_DIV2>,
769 <&clkc CLKID_FCLK_DIV2>;
777 <&clkc CLKID_FCLK_DIV2>;
785 <&clkc CLKID_FCLK_DIV2>;
Dmeson-axg.dtsi149 <&clkc CLKID_FCLK_DIV2>,
1534 <&clkc CLKID_FCLK_DIV2>;
1546 <&clkc CLKID_FCLK_DIV2>;
Dmeson-g12-common.dtsi107 <&clkc CLKID_FCLK_DIV2>,
2316 <&clkc CLKID_FCLK_DIV2>;
2328 <&clkc CLKID_FCLK_DIV2>;
2340 <&clkc CLKID_FCLK_DIV2>;
/external/u-boot/drivers/clk/meson/
Dg12a.c124 MESON_GATE(CLKID_FCLK_DIV2, HHI_FIX_PLL_CNTL1, 24),
781 case CLKID_FCLK_DIV2: in meson_clk_get_rate_by_id()
898 case CLKID_FCLK_DIV2: in meson_clk_set_rate_by_id()
Daxg.c244 case CLKID_FCLK_DIV2: in meson_clk_get_rate_by_id()
Dgxbb.c732 case CLKID_FCLK_DIV2: in meson_clk_get_rate_by_id()
817 case CLKID_FCLK_DIV2: in meson_clk_set_rate_by_id()